update xserver dri2 pci_ids

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update xserver dri2 pci_ids

Jonathan Gray-11
The modesetting driver uses this when picking a dri driver.

Update to the latest ids in Mesa.

Equivalent to xserver git with a patch to add some more Intel ids
https://marc.info/?l=freedesktop-xorg-devel&m=154939183126418&w=2
and a patch I just sent to the xorg-devel list to sync radeonsi ids with
Mesa.

Index: i965_pci_ids.h
===================================================================
RCS file: /cvs/xenocara/xserver/hw/xfree86/dri2/pci_ids/i965_pci_ids.h,v
retrieving revision 1.3
diff -u -p -r1.3 i965_pci_ids.h
--- i965_pci_ids.h 8 Dec 2017 15:02:00 -0000 1.3
+++ i965_pci_ids.h 17 Feb 2019 10:24:52 -0000
@@ -151,7 +151,7 @@ CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabyl
 CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1")
 CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
 CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
-CHIPSET(0x5917, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
+CHIPSET(0x5917, kbl_gt2, "Intel(R) UHD Graphics 620 (Kabylake GT2)")
 CHIPSET(0x5912, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)")
 CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 (Kaby Lake GT2)")
 CHIPSET(0x591A, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)")
@@ -160,22 +160,35 @@ CHIPSET(0x591D, kbl_gt2, "Intel(R) HD Gr
 CHIPSET(0x591E, kbl_gt2, "Intel(R) HD Graphics 615 (Kaby Lake GT2)")
 CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F")
 CHIPSET(0x5923, kbl_gt3, "Intel(R) Kabylake GT3")
-CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3)")
-CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3)")
+CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3e)")
+CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3e)")
 CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
-CHIPSET(0x3184, glk,     "Intel(R) HD Graphics (Geminilake)")
-CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
-CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
-CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x591C, kbl_gt2, "Intel(R) Amber Lake (Kabylake) GT2")
+CHIPSET(0x87C0, kbl_gt2, "Intel(R) Amber Lake (Kabylake) GT2")
+CHIPSET(0x87CA, cfl_gt2, "Intel(R) Amber Lake (Coffeelake) GT2")
+CHIPSET(0x3184, glk,     "Intel(R) UHD Graphics 605 (Geminilake)")
+CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
+CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E9C, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E91, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E92, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
 CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
-CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E98, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E9A, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E9B, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
 CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3EA9, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
 CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
 CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
 CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
-CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 2x6 GT1)")
+CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT1)")
+CHIPSET(0x3EA0, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)")
+CHIPSET(0x3EA3, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)")
+CHIPSET(0x3EA2, cfl_gt3, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT3)")
 CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
 CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
 CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
@@ -188,3 +201,15 @@ CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Gr
 CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
 CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
 CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A56, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A57, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
+CHIPSET(0x8A58, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A59, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
+CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
+CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
+CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")
Index: radeonsi_pci_ids.h
===================================================================
RCS file: /cvs/xenocara/xserver/hw/xfree86/dri2/pci_ids/radeonsi_pci_ids.h,v
retrieving revision 1.4
diff -u -p -r1.4 radeonsi_pci_ids.h
--- radeonsi_pci_ids.h 8 Dec 2017 15:02:00 -0000 1.4
+++ radeonsi_pci_ids.h 17 Feb 2019 10:43:16 -0000
@@ -202,6 +202,54 @@ CHIPSET(0x67C9, POLARIS10_, POLARIS10)
 CHIPSET(0x67CA, POLARIS10_, POLARIS10)
 CHIPSET(0x67CC, POLARIS10_, POLARIS10)
 CHIPSET(0x67CF, POLARIS10_, POLARIS10)
+CHIPSET(0x67D0, POLARIS10_, POLARIS10)
 CHIPSET(0x67DF, POLARIS10_, POLARIS10)
+CHIPSET(0x6FDF, POLARIS10_, POLARIS10)
 
 CHIPSET(0x98E4, STONEY_, STONEY)
+
+CHIPSET(0x6980, POLARIS12_, POLARIS12)
+CHIPSET(0x6981, POLARIS12_, POLARIS12)
+CHIPSET(0x6985, POLARIS12_, POLARIS12)
+CHIPSET(0x6986, POLARIS12_, POLARIS12)
+CHIPSET(0x6987, POLARIS12_, POLARIS12)
+CHIPSET(0x6995, POLARIS12_, POLARIS12)
+CHIPSET(0x6997, POLARIS12_, POLARIS12)
+CHIPSET(0x699F, POLARIS12_, POLARIS12)
+
+CHIPSET(0x694C, VEGAM_, VEGAM)
+CHIPSET(0x694E, VEGAM_, VEGAM)
+CHIPSET(0x694F, VEGAM_, VEGAM)
+
+CHIPSET(0x6860, VEGA10_, VEGA10)
+CHIPSET(0x6861, VEGA10_, VEGA10)
+CHIPSET(0x6862, VEGA10_, VEGA10)
+CHIPSET(0x6863, VEGA10_, VEGA10)
+CHIPSET(0x6864, VEGA10_, VEGA10)
+CHIPSET(0x6867, VEGA10_, VEGA10)
+CHIPSET(0x6868, VEGA10_, VEGA10)
+CHIPSET(0x6869, VEGA10_, VEGA10)
+CHIPSET(0x686A, VEGA10_, VEGA10)
+CHIPSET(0x686B, VEGA10_, VEGA10)
+CHIPSET(0x686C, VEGA10_, VEGA10)
+CHIPSET(0x686D, VEGA10_, VEGA10)
+CHIPSET(0x686E, VEGA10_, VEGA10)
+CHIPSET(0x686F, VEGA10_, VEGA10)
+CHIPSET(0x687F, VEGA10_, VEGA10)
+
+CHIPSET(0x69A0, VEGA12_, VEGA12)
+CHIPSET(0x69A1, VEGA12_, VEGA12)
+CHIPSET(0x69A2, VEGA12_, VEGA12)
+CHIPSET(0x69A3, VEGA12_, VEGA12)
+CHIPSET(0x69AF, VEGA12_, VEGA12)
+
+CHIPSET(0x66A0, VEGA20_, VEGA20)
+CHIPSET(0x66A1, VEGA20_, VEGA20)
+CHIPSET(0x66A2, VEGA20_, VEGA20)
+CHIPSET(0x66A3, VEGA20_, VEGA20)
+CHIPSET(0x66A4, VEGA20_, VEGA20)
+CHIPSET(0x66A7, VEGA20_, VEGA20)
+CHIPSET(0x66AF, VEGA20_, VEGA20)
+
+CHIPSET(0x15DD, RAVEN_, RAVEN)
+CHIPSET(0x15D8, RAVEN_, RAVEN)

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Re: update xserver dri2 pci_ids

Mark Kettenis
> Date: Sun, 17 Feb 2019 22:13:51 +1100
> From: Jonathan Gray <[hidden email]>
>
> The modesetting driver uses this when picking a dri driver.
>
> Update to the latest ids in Mesa.
>
> Equivalent to xserver git with a patch to add some more Intel ids
> https://marc.info/?l=freedesktop-xorg-devel&m=154939183126418&w=2
> and a patch I just sent to the xorg-devel list to sync radeonsi ids with
> Mesa.

ok kettenis@

> Index: i965_pci_ids.h
> ===================================================================
> RCS file: /cvs/xenocara/xserver/hw/xfree86/dri2/pci_ids/i965_pci_ids.h,v
> retrieving revision 1.3
> diff -u -p -r1.3 i965_pci_ids.h
> --- i965_pci_ids.h 8 Dec 2017 15:02:00 -0000 1.3
> +++ i965_pci_ids.h 17 Feb 2019 10:24:52 -0000
> @@ -151,7 +151,7 @@ CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabyl
>  CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1")
>  CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
>  CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
> -CHIPSET(0x5917, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
> +CHIPSET(0x5917, kbl_gt2, "Intel(R) UHD Graphics 620 (Kabylake GT2)")
>  CHIPSET(0x5912, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)")
>  CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 (Kaby Lake GT2)")
>  CHIPSET(0x591A, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)")
> @@ -160,22 +160,35 @@ CHIPSET(0x591D, kbl_gt2, "Intel(R) HD Gr
>  CHIPSET(0x591E, kbl_gt2, "Intel(R) HD Graphics 615 (Kaby Lake GT2)")
>  CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F")
>  CHIPSET(0x5923, kbl_gt3, "Intel(R) Kabylake GT3")
> -CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3)")
> -CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3)")
> +CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3e)")
> +CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3e)")
>  CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
> -CHIPSET(0x3184, glk,     "Intel(R) HD Graphics (Geminilake)")
> -CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
> -CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> -CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> -CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> -CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x591C, kbl_gt2, "Intel(R) Amber Lake (Kabylake) GT2")
> +CHIPSET(0x87C0, kbl_gt2, "Intel(R) Amber Lake (Kabylake) GT2")
> +CHIPSET(0x87CA, cfl_gt2, "Intel(R) Amber Lake (Coffeelake) GT2")
> +CHIPSET(0x3184, glk,     "Intel(R) UHD Graphics 605 (Geminilake)")
> +CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
> +CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E9C, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E91, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3E92, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
>  CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> -CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3E98, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3E9A, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3E9B, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
>  CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3EA9, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>  CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>  CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>  CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
> -CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
> +CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 2x6 GT1)")
> +CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT1)")
> +CHIPSET(0x3EA0, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)")
> +CHIPSET(0x3EA3, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)")
> +CHIPSET(0x3EA2, cfl_gt3, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT3)")
>  CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
>  CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
>  CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
> @@ -188,3 +201,15 @@ CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Gr
>  CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>  CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>  CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
> +CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
> +CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
> +CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
> +CHIPSET(0x8A56, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
> +CHIPSET(0x8A57, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
> +CHIPSET(0x8A58, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
> +CHIPSET(0x8A59, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
> +CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
> +CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
> +CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
> +CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
> +CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")
> Index: radeonsi_pci_ids.h
> ===================================================================
> RCS file: /cvs/xenocara/xserver/hw/xfree86/dri2/pci_ids/radeonsi_pci_ids.h,v
> retrieving revision 1.4
> diff -u -p -r1.4 radeonsi_pci_ids.h
> --- radeonsi_pci_ids.h 8 Dec 2017 15:02:00 -0000 1.4
> +++ radeonsi_pci_ids.h 17 Feb 2019 10:43:16 -0000
> @@ -202,6 +202,54 @@ CHIPSET(0x67C9, POLARIS10_, POLARIS10)
>  CHIPSET(0x67CA, POLARIS10_, POLARIS10)
>  CHIPSET(0x67CC, POLARIS10_, POLARIS10)
>  CHIPSET(0x67CF, POLARIS10_, POLARIS10)
> +CHIPSET(0x67D0, POLARIS10_, POLARIS10)
>  CHIPSET(0x67DF, POLARIS10_, POLARIS10)
> +CHIPSET(0x6FDF, POLARIS10_, POLARIS10)
>  
>  CHIPSET(0x98E4, STONEY_, STONEY)
> +
> +CHIPSET(0x6980, POLARIS12_, POLARIS12)
> +CHIPSET(0x6981, POLARIS12_, POLARIS12)
> +CHIPSET(0x6985, POLARIS12_, POLARIS12)
> +CHIPSET(0x6986, POLARIS12_, POLARIS12)
> +CHIPSET(0x6987, POLARIS12_, POLARIS12)
> +CHIPSET(0x6995, POLARIS12_, POLARIS12)
> +CHIPSET(0x6997, POLARIS12_, POLARIS12)
> +CHIPSET(0x699F, POLARIS12_, POLARIS12)
> +
> +CHIPSET(0x694C, VEGAM_, VEGAM)
> +CHIPSET(0x694E, VEGAM_, VEGAM)
> +CHIPSET(0x694F, VEGAM_, VEGAM)
> +
> +CHIPSET(0x6860, VEGA10_, VEGA10)
> +CHIPSET(0x6861, VEGA10_, VEGA10)
> +CHIPSET(0x6862, VEGA10_, VEGA10)
> +CHIPSET(0x6863, VEGA10_, VEGA10)
> +CHIPSET(0x6864, VEGA10_, VEGA10)
> +CHIPSET(0x6867, VEGA10_, VEGA10)
> +CHIPSET(0x6868, VEGA10_, VEGA10)
> +CHIPSET(0x6869, VEGA10_, VEGA10)
> +CHIPSET(0x686A, VEGA10_, VEGA10)
> +CHIPSET(0x686B, VEGA10_, VEGA10)
> +CHIPSET(0x686C, VEGA10_, VEGA10)
> +CHIPSET(0x686D, VEGA10_, VEGA10)
> +CHIPSET(0x686E, VEGA10_, VEGA10)
> +CHIPSET(0x686F, VEGA10_, VEGA10)
> +CHIPSET(0x687F, VEGA10_, VEGA10)
> +
> +CHIPSET(0x69A0, VEGA12_, VEGA12)
> +CHIPSET(0x69A1, VEGA12_, VEGA12)
> +CHIPSET(0x69A2, VEGA12_, VEGA12)
> +CHIPSET(0x69A3, VEGA12_, VEGA12)
> +CHIPSET(0x69AF, VEGA12_, VEGA12)
> +
> +CHIPSET(0x66A0, VEGA20_, VEGA20)
> +CHIPSET(0x66A1, VEGA20_, VEGA20)
> +CHIPSET(0x66A2, VEGA20_, VEGA20)
> +CHIPSET(0x66A3, VEGA20_, VEGA20)
> +CHIPSET(0x66A4, VEGA20_, VEGA20)
> +CHIPSET(0x66A7, VEGA20_, VEGA20)
> +CHIPSET(0x66AF, VEGA20_, VEGA20)
> +
> +CHIPSET(0x15DD, RAVEN_, RAVEN)
> +CHIPSET(0x15D8, RAVEN_, RAVEN)
>
>

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Re: update xserver dri2 pci_ids

Matthieu Herrb-3
In reply to this post by Jonathan Gray-11
On Sun, Feb 17, 2019 at 10:13:51PM +1100, Jonathan Gray wrote:
> The modesetting driver uses this when picking a dri driver.
>
> Update to the latest ids in Mesa.
>
> Equivalent to xserver git with a patch to add some more Intel ids
> https://marc.info/?l=freedesktop-xorg-devel&m=154939183126418&w=2
> and a patch I just sent to the xorg-devel list to sync radeonsi ids with
> Mesa.

ok matthieu@

>
> Index: i965_pci_ids.h
> ===================================================================
> RCS file: /cvs/xenocara/xserver/hw/xfree86/dri2/pci_ids/i965_pci_ids.h,v
> retrieving revision 1.3
> diff -u -p -r1.3 i965_pci_ids.h
> --- i965_pci_ids.h 8 Dec 2017 15:02:00 -0000 1.3
> +++ i965_pci_ids.h 17 Feb 2019 10:24:52 -0000
> @@ -151,7 +151,7 @@ CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabyl
>  CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1")
>  CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
>  CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
> -CHIPSET(0x5917, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
> +CHIPSET(0x5917, kbl_gt2, "Intel(R) UHD Graphics 620 (Kabylake GT2)")
>  CHIPSET(0x5912, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)")
>  CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 (Kaby Lake GT2)")
>  CHIPSET(0x591A, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)")
> @@ -160,22 +160,35 @@ CHIPSET(0x591D, kbl_gt2, "Intel(R) HD Gr
>  CHIPSET(0x591E, kbl_gt2, "Intel(R) HD Graphics 615 (Kaby Lake GT2)")
>  CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F")
>  CHIPSET(0x5923, kbl_gt3, "Intel(R) Kabylake GT3")
> -CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3)")
> -CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3)")
> +CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3e)")
> +CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3e)")
>  CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
> -CHIPSET(0x3184, glk,     "Intel(R) HD Graphics (Geminilake)")
> -CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
> -CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> -CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> -CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> -CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x591C, kbl_gt2, "Intel(R) Amber Lake (Kabylake) GT2")
> +CHIPSET(0x87C0, kbl_gt2, "Intel(R) Amber Lake (Kabylake) GT2")
> +CHIPSET(0x87CA, cfl_gt2, "Intel(R) Amber Lake (Coffeelake) GT2")
> +CHIPSET(0x3184, glk,     "Intel(R) UHD Graphics 605 (Geminilake)")
> +CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
> +CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E9C, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E91, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3E92, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
>  CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> -CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3E98, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3E9A, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3E9B, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
>  CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3EA9, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
> +CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>  CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>  CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>  CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
> -CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
> +CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 2x6 GT1)")
> +CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT1)")
> +CHIPSET(0x3EA0, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)")
> +CHIPSET(0x3EA3, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)")
> +CHIPSET(0x3EA2, cfl_gt3, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT3)")
>  CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
>  CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
>  CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
> @@ -188,3 +201,15 @@ CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Gr
>  CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>  CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>  CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
> +CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
> +CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
> +CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
> +CHIPSET(0x8A56, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
> +CHIPSET(0x8A57, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
> +CHIPSET(0x8A58, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
> +CHIPSET(0x8A59, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
> +CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
> +CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
> +CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
> +CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
> +CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")
> Index: radeonsi_pci_ids.h
> ===================================================================
> RCS file: /cvs/xenocara/xserver/hw/xfree86/dri2/pci_ids/radeonsi_pci_ids.h,v
> retrieving revision 1.4
> diff -u -p -r1.4 radeonsi_pci_ids.h
> --- radeonsi_pci_ids.h 8 Dec 2017 15:02:00 -0000 1.4
> +++ radeonsi_pci_ids.h 17 Feb 2019 10:43:16 -0000
> @@ -202,6 +202,54 @@ CHIPSET(0x67C9, POLARIS10_, POLARIS10)
>  CHIPSET(0x67CA, POLARIS10_, POLARIS10)
>  CHIPSET(0x67CC, POLARIS10_, POLARIS10)
>  CHIPSET(0x67CF, POLARIS10_, POLARIS10)
> +CHIPSET(0x67D0, POLARIS10_, POLARIS10)
>  CHIPSET(0x67DF, POLARIS10_, POLARIS10)
> +CHIPSET(0x6FDF, POLARIS10_, POLARIS10)
>  
>  CHIPSET(0x98E4, STONEY_, STONEY)
> +
> +CHIPSET(0x6980, POLARIS12_, POLARIS12)
> +CHIPSET(0x6981, POLARIS12_, POLARIS12)
> +CHIPSET(0x6985, POLARIS12_, POLARIS12)
> +CHIPSET(0x6986, POLARIS12_, POLARIS12)
> +CHIPSET(0x6987, POLARIS12_, POLARIS12)
> +CHIPSET(0x6995, POLARIS12_, POLARIS12)
> +CHIPSET(0x6997, POLARIS12_, POLARIS12)
> +CHIPSET(0x699F, POLARIS12_, POLARIS12)
> +
> +CHIPSET(0x694C, VEGAM_, VEGAM)
> +CHIPSET(0x694E, VEGAM_, VEGAM)
> +CHIPSET(0x694F, VEGAM_, VEGAM)
> +
> +CHIPSET(0x6860, VEGA10_, VEGA10)
> +CHIPSET(0x6861, VEGA10_, VEGA10)
> +CHIPSET(0x6862, VEGA10_, VEGA10)
> +CHIPSET(0x6863, VEGA10_, VEGA10)
> +CHIPSET(0x6864, VEGA10_, VEGA10)
> +CHIPSET(0x6867, VEGA10_, VEGA10)
> +CHIPSET(0x6868, VEGA10_, VEGA10)
> +CHIPSET(0x6869, VEGA10_, VEGA10)
> +CHIPSET(0x686A, VEGA10_, VEGA10)
> +CHIPSET(0x686B, VEGA10_, VEGA10)
> +CHIPSET(0x686C, VEGA10_, VEGA10)
> +CHIPSET(0x686D, VEGA10_, VEGA10)
> +CHIPSET(0x686E, VEGA10_, VEGA10)
> +CHIPSET(0x686F, VEGA10_, VEGA10)
> +CHIPSET(0x687F, VEGA10_, VEGA10)
> +
> +CHIPSET(0x69A0, VEGA12_, VEGA12)
> +CHIPSET(0x69A1, VEGA12_, VEGA12)
> +CHIPSET(0x69A2, VEGA12_, VEGA12)
> +CHIPSET(0x69A3, VEGA12_, VEGA12)
> +CHIPSET(0x69AF, VEGA12_, VEGA12)
> +
> +CHIPSET(0x66A0, VEGA20_, VEGA20)
> +CHIPSET(0x66A1, VEGA20_, VEGA20)
> +CHIPSET(0x66A2, VEGA20_, VEGA20)
> +CHIPSET(0x66A3, VEGA20_, VEGA20)
> +CHIPSET(0x66A4, VEGA20_, VEGA20)
> +CHIPSET(0x66A7, VEGA20_, VEGA20)
> +CHIPSET(0x66AF, VEGA20_, VEGA20)
> +
> +CHIPSET(0x15DD, RAVEN_, RAVEN)
> +CHIPSET(0x15D8, RAVEN_, RAVEN)

--
Matthieu Herrb