sunxi: don't use sxitimer on the sun7i/A20

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sunxi: don't use sxitimer on the sun7i/A20

Patrick Wildt-3
Hi,

one of the reasons Allwinner A20/sun7i-based boards, like the
Cubieboard 2 or Banana Pi, don't boot is that the sxitimer does
not work for us.  We are getting no hardclock ticks and so the
system can't work.

There's a simple fix for that.  We can just not use the sxitimer
and instead use the ARM architected timer (agtimer) that is
supposed to be a generic implementation for all new cores and
already attaches anyway.  The sxitimer attachment currently
overrides the agtimer.  Removing sxitimer thus allows agtimer
to actually do its work.

Currently sxirtc uncondtionally ties into sxitimer.  To make
this work, just make sxirtc map its own page instead of relying
on the existence of a mapping created by sxitimer.

The address/size used for the sxirtc is from a device tree
source.

Patrick

diff --git sys/arch/armv7/sunxi/sunxi.c sys/arch/armv7/sunxi/sunxi.c
index accd475..80cc08f 100644
--- sys/arch/armv7/sunxi/sunxi.c
+++ sys/arch/armv7/sunxi/sunxi.c
@@ -67,9 +67,6 @@ struct board_dev sun4i_devs[] = {
 struct board_dev sun7i_devs[] = {
  { "sxipio", 0 },
  { "sxiccmu", 0 },
- { "sxitimer", 0 },
- { "sxitimer", 1 },
- { "sxitimer", 2 },
  { "sxidog", 0 },
  { "sxirtc", 0 },
  { "sxiuart", 0 },
diff --git sys/arch/armv7/sunxi/sunxireg.h sys/arch/armv7/sunxi/sunxireg.h
index e1d4f55..59eb0f2 100644
--- sys/arch/armv7/sunxi/sunxireg.h
+++ sys/arch/armv7/sunxi/sunxireg.h
@@ -69,8 +69,8 @@
 #define WDOG_SIZE 0x08
 #define WDOG_IRQ 24
 
-#define RTC_ADDR 0x0104
-#define RTC_SIZE 0x08
+#define RTC_ADDR 0x01c20d00
+#define RTC_SIZE 0x20
 
 /* Clock Control Module/Unit */
 #define CCMU_ADDR 0x01c20000
diff --git sys/arch/armv7/sunxi/sxirtc.c sys/arch/armv7/sunxi/sxirtc.c
index b0e0653..3ecbf5e 100644
--- sys/arch/armv7/sunxi/sxirtc.c
+++ sys/arch/armv7/sunxi/sxirtc.c
@@ -31,8 +31,8 @@
 #include <armv7/armv7/armv7var.h>
 #include <armv7/sunxi/sunxireg.h>
 
-#define SXIRTC_YYMMDD 0x00
-#define SXIRTC_HHMMSS 0x04
+#define SXIRTC_YYMMDD 0x04
+#define SXIRTC_HHMMSS 0x08
 
 #define LEAPYEAR(y)        \
     (((y) % 4 == 0 &&    \
@@ -76,8 +76,8 @@ sxirtc_attach(struct device *parent, struct device *self, void *args)
  panic("sxirtc_attach: couldn't allocate todr_handle");
 
  sc->sc_iot = aa->aa_iot;
- if (bus_space_subregion(sc->sc_iot, sxitimer_ioh,
-    aa->aa_dev->mem[0].addr, aa->aa_dev->mem[0].size, &sc->sc_ioh))
+ if (bus_space_map(sc->sc_iot, aa->aa_dev->mem[0].addr,
+    aa->aa_dev->mem[0].size, 0, &sc->sc_ioh))
  panic("sxirtc_attach: bus_space_subregion failed!");
 
  handle->cookie = self;

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Re: sunxi: don't use sxitimer on the sun7i/A20

Artturi Alm
On Sun, Jan 31, 2016 at 01:14:35AM +0100, Patrick Wildt wrote:

> Hi,
>
> one of the reasons Allwinner A20/sun7i-based boards, like the
> Cubieboard 2 or Banana Pi, don't boot is that the sxitimer does
> not work for us.  We are getting no hardclock ticks and so the
> system can't work.
>
> There's a simple fix for that.  We can just not use the sxitimer
> and instead use the ARM architected timer (agtimer) that is
> supposed to be a generic implementation for all new cores and
> already attaches anyway.  The sxitimer attachment currently
> overrides the agtimer.  Removing sxitimer thus allows agtimer
> to actually do its work.
>
> Currently sxirtc uncondtionally ties into sxitimer.  To make
> this work, just make sxirtc map its own page instead of relying
> on the existence of a mapping created by sxitimer.
>
> The address/size used for the sxirtc is from a device tree
> source.
>
> Patrick
>

Hi,

nothing i would change about your diff, given now there's agtimer,
but it doesn't really seem to even try fixing rtc on A20, and leaves
ugly glue into sxitimer written just for A20, which imho should also
get cleaned up.

-Artturi


diff --git a/sys/arch/armv7/sunxi/sun7i.c b/sys/arch/armv7/sunxi/sun7i.c
index 0d06b31..d8fcd45 100644
--- a/sys/arch/armv7/sunxi/sun7i.c
+++ b/sys/arch/armv7/sunxi/sun7i.c
@@ -39,19 +39,6 @@ struct armv7_dev sxia20_devs[] = {
   .mem = { { CCMU_ADDR, CCMU_SIZE } },
  },
 
- /* Timers/Counters, resources mapped on first unit */
- { .name = "sxitimer",
-  .unit = 0,
-  .mem = { { TIMER_ADDR, TIMERx_SIZE },
- { CPUCNTRS_ADDR, CPUCNTRS_ADDR } }
- },
- { .name = "sxitimer",
-  .unit = 1,
- },
- { .name = "sxitimer",
-  .unit = 2,
- },
-
  /* Watchdog Timer */
  { .name = "sxidog",
   .unit = 0,
diff --git a/sys/arch/armv7/sunxi/sxirtc.c b/sys/arch/armv7/sunxi/sxirtc.c
index 32460d6..cdd6716 100644
--- a/sys/arch/armv7/sunxi/sxirtc.c
+++ b/sys/arch/armv7/sunxi/sxirtc.c
@@ -15,9 +15,6 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-/* XXX this doesn't support A20 yet. */
- /* year & 0xff on A20, 0x3f on A10 */
- /* leap << 24 on A20, << 22 on A10 */
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -40,9 +37,6 @@
     (y) % 400 == 0)
 
 
-/* XXX other way around than bus_space_subregion? */
-extern bus_space_handle_t sxitimer_ioh;
-
 extern todr_chip_handle_t todr_handle;
 
 struct sxirtc_softc {
@@ -61,6 +55,8 @@ struct cfdriver sxirtc_cd = {
  NULL, "sxirtc", DV_DULL
 };
 
+uint32_t sxirtc_a20 = 0;
+
 int sxirtc_gettime(todr_chip_handle_t, struct timeval *);
 int sxirtc_settime(todr_chip_handle_t, struct timeval *);
 
@@ -78,7 +74,10 @@ sxirtc_attach(struct device *parent, struct device *self, void *args)
  sc->sc_iot = aa->aa_iot;
  if (bus_space_map(sc->sc_iot, aa->aa_dev->mem[0].addr,
     aa->aa_dev->mem[0].size, 0, &sc->sc_ioh))
- panic("sxirtc_attach: bus_space_subregion failed!");
+ panic("sxirtc_attach: bus_space_map failed!");
+
+ if (BOARD_ID_SUN7I_A20)
+ sxirtc_a20 = 1;
 
  handle->cookie = self;
  handle->todr_gettime = sxirtc_gettime;
@@ -97,6 +96,8 @@ sxirtc_gettime(todr_chip_handle_t handle, struct timeval *tv)
 {
  struct sxirtc_softc *sc = (struct sxirtc_softc *)handle->cookie;
  struct clock_ymdhms dt;
+ uint32_t base_year = sxirtc_a20 ? 1970 : 2010;
+ uint32_t year_mask = sxirtc_a20 ? 0xff : 0x3f;
  uint32_t reg;
 
  reg = SXIREAD4(sc, SXIRTC_HHMMSS);
@@ -108,7 +109,7 @@ sxirtc_gettime(todr_chip_handle_t handle, struct timeval *tv)
  reg = SXIREAD4(sc, SXIRTC_YYMMDD);
  dt.dt_day = reg & 0x1f;
  dt.dt_mon = reg >> 8 & 0x0f;
- dt.dt_year = (reg >> 16 & 0x3f) + 2010; /* 0xff on A20 */
+ dt.dt_year = (reg >> 16 & year_mask) + base_year;
 
  if (dt.dt_sec > 59 || dt.dt_min > 59 ||
     dt.dt_hour > 23 || dt.dt_wday > 6 ||
@@ -126,6 +127,8 @@ sxirtc_settime(todr_chip_handle_t handle, struct timeval *tv)
 {
  struct sxirtc_softc *sc = (struct sxirtc_softc *)handle->cookie;
  struct clock_ymdhms dt;
+ uint32_t base_year = sxirtc_a20 ? 1970 : 2010;
+ uint32_t leap_shift = sxirtc_a20 ? 24 : 22;
 
  clock_secs_to_ymdhms(tv->tv_sec, &dt);
 
@@ -140,8 +143,8 @@ sxirtc_settime(todr_chip_handle_t handle, struct timeval *tv)
     (dt.dt_wday << 29));
 
  SXICMS4(sc, SXIRTC_YYMMDD, 0x00400000 | 0x003f0000 | 0x0f00 | 0x1f,
-   dt.dt_day | (dt.dt_mon << 8) | ((dt.dt_year - 2010) << 16) |
-   (LEAPYEAR(dt.dt_year) << 22));
+   dt.dt_day | (dt.dt_mon << 8) | ((dt.dt_year - base_year) << 16) |
+   (LEAPYEAR(dt.dt_year) << leap_shift));
 
  return 0;
 }
diff --git a/sys/arch/armv7/sunxi/sxitimer.c b/sys/arch/armv7/sunxi/sxitimer.c
index c07f85a..97eb51b 100644
--- a/sys/arch/armv7/sunxi/sxitimer.c
+++ b/sys/arch/armv7/sunxi/sxitimer.c
@@ -44,11 +44,6 @@
 #define TIMER_INTV(x) (0x14 + (0x10 * (x)))
 #define TIMER_CURR(x) (0x18 + (0x10 * (x)))
 
-/* A20 counter, relative to CPUCNTRS_ADDR */
-#define OSC24M_CNT64_CTRL 0x80
-#define OSC24M_CNT64_LOW 0x84
-#define OSC24M_CNT64_HIGH 0x88
-
 /* A1X counter */
 #define CNT64_CTRL 0xa0
 #define CNT64_LOW 0xa4
@@ -56,7 +51,6 @@
 
 #define CNT64_CLR_EN (1 << 0) /* clear enable */
 #define CNT64_RL_EN (1 << 1) /* read latch enable */
-#define CNT64_SYNCH (1 << 4) /* sync to OSC24M counter */
 
 #define LOSC_CTRL 0x100
 #define OSC32K_SRC_SEL (1 << 0)
@@ -99,7 +93,6 @@ static struct timecounter sxitimer_timecounter = {
 
 bus_space_tag_t sxitimer_iot;
 bus_space_handle_t sxitimer_ioh;
-bus_space_handle_t sxitimer_cntr_ioh;
 
 uint32_t sxitimer_freq[] = {
  TIMER0_FREQUENCY,
@@ -120,10 +113,6 @@ uint32_t sxitimer_statvar, sxitimer_statmin;
 uint32_t sxitimer_tick_nextevt, sxitimer_stat_nextevt;
 uint32_t sxitimer_ticks_err_cnt, sxitimer_ticks_err_sum;
 
-bus_addr_t cntr64_ctrl = CNT64_CTRL;
-bus_addr_t cntr64_low = CNT64_LOW;
-bus_addr_t cntr64_high = CNT64_HIGH;
-
 struct sxitimer_softc {
  struct device sc_dev;
 };
@@ -140,7 +129,7 @@ void
 sxitimer_attach(struct device *parent, struct device *self, void *args)
 {
  struct armv7_attach_args *aa = args;
- uint32_t freq, ival, now, cr, v;
+ uint32_t freq, ival, now, cr;
  int unit = self->dv_unit;
 
  if (unit != 0)
@@ -152,29 +141,10 @@ sxitimer_attach(struct device *parent, struct device *self, void *args)
     aa->aa_dev->mem[0].size, 0, &sxitimer_ioh))
  panic("sxitimer_attach: bus_space_map failed!");
 
-
- if (board_id == BOARD_ID_SUN7I_A20) {
- if (bus_space_map(sxitimer_iot, CPUCNTRS_ADDR, CPUCNTRS_SIZE,
-    0, &sxitimer_cntr_ioh))
- panic("sxitimer_attach: bus_space_map failed!");
-
- cntr64_ctrl = OSC24M_CNT64_CTRL;
- cntr64_low = OSC24M_CNT64_LOW;
- cntr64_high = OSC24M_CNT64_HIGH;
-
- v = bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh,
-    cntr64_ctrl);
- bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl,
-    v | CNT64_SYNCH);
- bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl,
-    v & ~CNT64_SYNCH);
- } else
- sxitimer_cntr_ioh = sxitimer_ioh;
-
  /* clear counter, loop until ready */
- bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl,
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL,
     CNT64_CLR_EN); /* XXX as a side-effect counter clk src=OSC24M */
- while (bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl)
+ while (bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL)
     & CNT64_CLR_EN)
  continue;
 
@@ -398,9 +368,8 @@ sxitimer_readcnt64(void)
  uint32_t low, high;
 
  /* latch counter, loop until ready */
- bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh,
-    cntr64_ctrl, CNT64_RL_EN);
- while (bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl)
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL, CNT64_RL_EN);
+ while (bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL)
     & CNT64_RL_EN)
  continue;
 
@@ -409,8 +378,8 @@ sxitimer_readcnt64(void)
  * iirc. A20 manual mentions that low should be read first.
  */
  /* XXX check above */
- low = bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_low);
- high = bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_high);
+ low = bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_LOW);
+ high = bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_HIGH);
  return (uint64_t)high << 32 | low;
 }
 

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Re: sunxi: don't use sxitimer on the sun7i/A20

Jonathan Gray-11
On Sun, Jan 31, 2016 at 10:12:05AM +0200, Artturi Alm wrote:

> On Sun, Jan 31, 2016 at 01:14:35AM +0100, Patrick Wildt wrote:
> > Hi,
> >
> > one of the reasons Allwinner A20/sun7i-based boards, like the
> > Cubieboard 2 or Banana Pi, don't boot is that the sxitimer does
> > not work for us.  We are getting no hardclock ticks and so the
> > system can't work.
> >
> > There's a simple fix for that.  We can just not use the sxitimer
> > and instead use the ARM architected timer (agtimer) that is
> > supposed to be a generic implementation for all new cores and
> > already attaches anyway.  The sxitimer attachment currently
> > overrides the agtimer.  Removing sxitimer thus allows agtimer
> > to actually do its work.
> >
> > Currently sxirtc uncondtionally ties into sxitimer.  To make
> > this work, just make sxirtc map its own page instead of relying
> > on the existence of a mapping created by sxitimer.
> >
> > The address/size used for the sxirtc is from a device tree
> > source.
> >
> > Patrick
> >
>
> Hi,
>
> nothing i would change about your diff, given now there's agtimer,
> but it doesn't really seem to even try fixing rtc on A20, and leaves
> ugly glue into sxitimer written just for A20, which imho should also
> get cleaned up.
>
> -Artturi

There seem to be at least two diffs here, the different rtc handling
for a20 should be split out, store sxirtc_a20 in the softc and fix
the test from
if (BOARD_ID_SUN7I_A20)
to
if (board_id == BOARD_ID_SUN7I_A20)

>
>
> diff --git a/sys/arch/armv7/sunxi/sun7i.c b/sys/arch/armv7/sunxi/sun7i.c
> index 0d06b31..d8fcd45 100644
> --- a/sys/arch/armv7/sunxi/sun7i.c
> +++ b/sys/arch/armv7/sunxi/sun7i.c
> @@ -39,19 +39,6 @@ struct armv7_dev sxia20_devs[] = {
>    .mem = { { CCMU_ADDR, CCMU_SIZE } },
>   },
>  
> - /* Timers/Counters, resources mapped on first unit */
> - { .name = "sxitimer",
> -  .unit = 0,
> -  .mem = { { TIMER_ADDR, TIMERx_SIZE },
> - { CPUCNTRS_ADDR, CPUCNTRS_ADDR } }
> - },
> - { .name = "sxitimer",
> -  .unit = 1,
> - },
> - { .name = "sxitimer",
> -  .unit = 2,
> - },
> -
>   /* Watchdog Timer */
>   { .name = "sxidog",
>    .unit = 0,
> diff --git a/sys/arch/armv7/sunxi/sxirtc.c b/sys/arch/armv7/sunxi/sxirtc.c
> index 32460d6..cdd6716 100644
> --- a/sys/arch/armv7/sunxi/sxirtc.c
> +++ b/sys/arch/armv7/sunxi/sxirtc.c
> @@ -15,9 +15,6 @@
>   * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
>   * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
>   */
> -/* XXX this doesn't support A20 yet. */
> - /* year & 0xff on A20, 0x3f on A10 */
> - /* leap << 24 on A20, << 22 on A10 */
>  
>  #include <sys/param.h>
>  #include <sys/device.h>
> @@ -40,9 +37,6 @@
>      (y) % 400 == 0)
>  
>  
> -/* XXX other way around than bus_space_subregion? */
> -extern bus_space_handle_t sxitimer_ioh;
> -
>  extern todr_chip_handle_t todr_handle;
>  
>  struct sxirtc_softc {
> @@ -61,6 +55,8 @@ struct cfdriver sxirtc_cd = {
>   NULL, "sxirtc", DV_DULL
>  };
>  
> +uint32_t sxirtc_a20 = 0;
> +
>  int sxirtc_gettime(todr_chip_handle_t, struct timeval *);
>  int sxirtc_settime(todr_chip_handle_t, struct timeval *);
>  
> @@ -78,7 +74,10 @@ sxirtc_attach(struct device *parent, struct device *self, void *args)
>   sc->sc_iot = aa->aa_iot;
>   if (bus_space_map(sc->sc_iot, aa->aa_dev->mem[0].addr,
>      aa->aa_dev->mem[0].size, 0, &sc->sc_ioh))
> - panic("sxirtc_attach: bus_space_subregion failed!");
> + panic("sxirtc_attach: bus_space_map failed!");
> +
> + if (BOARD_ID_SUN7I_A20)
> + sxirtc_a20 = 1;
>  
>   handle->cookie = self;
>   handle->todr_gettime = sxirtc_gettime;
> @@ -97,6 +96,8 @@ sxirtc_gettime(todr_chip_handle_t handle, struct timeval *tv)
>  {
>   struct sxirtc_softc *sc = (struct sxirtc_softc *)handle->cookie;
>   struct clock_ymdhms dt;
> + uint32_t base_year = sxirtc_a20 ? 1970 : 2010;
> + uint32_t year_mask = sxirtc_a20 ? 0xff : 0x3f;
>   uint32_t reg;
>  
>   reg = SXIREAD4(sc, SXIRTC_HHMMSS);
> @@ -108,7 +109,7 @@ sxirtc_gettime(todr_chip_handle_t handle, struct timeval *tv)
>   reg = SXIREAD4(sc, SXIRTC_YYMMDD);
>   dt.dt_day = reg & 0x1f;
>   dt.dt_mon = reg >> 8 & 0x0f;
> - dt.dt_year = (reg >> 16 & 0x3f) + 2010; /* 0xff on A20 */
> + dt.dt_year = (reg >> 16 & year_mask) + base_year;
>  
>   if (dt.dt_sec > 59 || dt.dt_min > 59 ||
>      dt.dt_hour > 23 || dt.dt_wday > 6 ||
> @@ -126,6 +127,8 @@ sxirtc_settime(todr_chip_handle_t handle, struct timeval *tv)
>  {
>   struct sxirtc_softc *sc = (struct sxirtc_softc *)handle->cookie;
>   struct clock_ymdhms dt;
> + uint32_t base_year = sxirtc_a20 ? 1970 : 2010;
> + uint32_t leap_shift = sxirtc_a20 ? 24 : 22;
>  
>   clock_secs_to_ymdhms(tv->tv_sec, &dt);
>  
> @@ -140,8 +143,8 @@ sxirtc_settime(todr_chip_handle_t handle, struct timeval *tv)
>      (dt.dt_wday << 29));
>  
>   SXICMS4(sc, SXIRTC_YYMMDD, 0x00400000 | 0x003f0000 | 0x0f00 | 0x1f,
> -   dt.dt_day | (dt.dt_mon << 8) | ((dt.dt_year - 2010) << 16) |
> -   (LEAPYEAR(dt.dt_year) << 22));
> +   dt.dt_day | (dt.dt_mon << 8) | ((dt.dt_year - base_year) << 16) |
> +   (LEAPYEAR(dt.dt_year) << leap_shift));
>  
>   return 0;
>  }
> diff --git a/sys/arch/armv7/sunxi/sxitimer.c b/sys/arch/armv7/sunxi/sxitimer.c
> index c07f85a..97eb51b 100644
> --- a/sys/arch/armv7/sunxi/sxitimer.c
> +++ b/sys/arch/armv7/sunxi/sxitimer.c
> @@ -44,11 +44,6 @@
>  #define TIMER_INTV(x) (0x14 + (0x10 * (x)))
>  #define TIMER_CURR(x) (0x18 + (0x10 * (x)))
>  
> -/* A20 counter, relative to CPUCNTRS_ADDR */
> -#define OSC24M_CNT64_CTRL 0x80
> -#define OSC24M_CNT64_LOW 0x84
> -#define OSC24M_CNT64_HIGH 0x88
> -
>  /* A1X counter */
>  #define CNT64_CTRL 0xa0
>  #define CNT64_LOW 0xa4
> @@ -56,7 +51,6 @@
>  
>  #define CNT64_CLR_EN (1 << 0) /* clear enable */
>  #define CNT64_RL_EN (1 << 1) /* read latch enable */
> -#define CNT64_SYNCH (1 << 4) /* sync to OSC24M counter */
>  
>  #define LOSC_CTRL 0x100
>  #define OSC32K_SRC_SEL (1 << 0)
> @@ -99,7 +93,6 @@ static struct timecounter sxitimer_timecounter = {
>  
>  bus_space_tag_t sxitimer_iot;
>  bus_space_handle_t sxitimer_ioh;
> -bus_space_handle_t sxitimer_cntr_ioh;
>  
>  uint32_t sxitimer_freq[] = {
>   TIMER0_FREQUENCY,
> @@ -120,10 +113,6 @@ uint32_t sxitimer_statvar, sxitimer_statmin;
>  uint32_t sxitimer_tick_nextevt, sxitimer_stat_nextevt;
>  uint32_t sxitimer_ticks_err_cnt, sxitimer_ticks_err_sum;
>  
> -bus_addr_t cntr64_ctrl = CNT64_CTRL;
> -bus_addr_t cntr64_low = CNT64_LOW;
> -bus_addr_t cntr64_high = CNT64_HIGH;
> -
>  struct sxitimer_softc {
>   struct device sc_dev;
>  };
> @@ -140,7 +129,7 @@ void
>  sxitimer_attach(struct device *parent, struct device *self, void *args)
>  {
>   struct armv7_attach_args *aa = args;
> - uint32_t freq, ival, now, cr, v;
> + uint32_t freq, ival, now, cr;
>   int unit = self->dv_unit;
>  
>   if (unit != 0)
> @@ -152,29 +141,10 @@ sxitimer_attach(struct device *parent, struct device *self, void *args)
>      aa->aa_dev->mem[0].size, 0, &sxitimer_ioh))
>   panic("sxitimer_attach: bus_space_map failed!");
>  
> -
> - if (board_id == BOARD_ID_SUN7I_A20) {
> - if (bus_space_map(sxitimer_iot, CPUCNTRS_ADDR, CPUCNTRS_SIZE,
> -    0, &sxitimer_cntr_ioh))
> - panic("sxitimer_attach: bus_space_map failed!");
> -
> - cntr64_ctrl = OSC24M_CNT64_CTRL;
> - cntr64_low = OSC24M_CNT64_LOW;
> - cntr64_high = OSC24M_CNT64_HIGH;
> -
> - v = bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh,
> -    cntr64_ctrl);
> - bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl,
> -    v | CNT64_SYNCH);
> - bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl,
> -    v & ~CNT64_SYNCH);
> - } else
> - sxitimer_cntr_ioh = sxitimer_ioh;
> -
>   /* clear counter, loop until ready */
> - bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl,
> + bus_space_write_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL,
>      CNT64_CLR_EN); /* XXX as a side-effect counter clk src=OSC24M */
> - while (bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl)
> + while (bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL)
>      & CNT64_CLR_EN)
>   continue;
>  
> @@ -398,9 +368,8 @@ sxitimer_readcnt64(void)
>   uint32_t low, high;
>  
>   /* latch counter, loop until ready */
> - bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh,
> -    cntr64_ctrl, CNT64_RL_EN);
> - while (bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl)
> + bus_space_write_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL, CNT64_RL_EN);
> + while (bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL)
>      & CNT64_RL_EN)
>   continue;
>  
> @@ -409,8 +378,8 @@ sxitimer_readcnt64(void)
>   * iirc. A20 manual mentions that low should be read first.
>   */
>   /* XXX check above */
> - low = bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_low);
> - high = bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_high);
> + low = bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_LOW);
> + high = bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_HIGH);
>   return (uint64_t)high << 32 | low;
>  }
>  
>

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Re: sunxi: don't use sxitimer on the sun7i/A20

Artturi Alm
On Sun, Jan 31, 2016 at 10:45:42PM +1100, Jonathan Gray wrote:

> On Sun, Jan 31, 2016 at 10:12:05AM +0200, Artturi Alm wrote:
> > On Sun, Jan 31, 2016 at 01:14:35AM +0100, Patrick Wildt wrote:
> > > Hi,
> > >
> > > one of the reasons Allwinner A20/sun7i-based boards, like the
> > > Cubieboard 2 or Banana Pi, don't boot is that the sxitimer does
> > > not work for us.  We are getting no hardclock ticks and so the
> > > system can't work.
> > >
> > > There's a simple fix for that.  We can just not use the sxitimer
> > > and instead use the ARM architected timer (agtimer) that is
> > > supposed to be a generic implementation for all new cores and
> > > already attaches anyway.  The sxitimer attachment currently
> > > overrides the agtimer.  Removing sxitimer thus allows agtimer
> > > to actually do its work.
> > >
> > > Currently sxirtc uncondtionally ties into sxitimer.  To make
> > > this work, just make sxirtc map its own page instead of relying
> > > on the existence of a mapping created by sxitimer.
> > >
> > > The address/size used for the sxirtc is from a device tree
> > > source.
> > >
> > > Patrick
> > >
> >
> > Hi,
> >
> > nothing i would change about your diff, given now there's agtimer,
> > but it doesn't really seem to even try fixing rtc on A20, and leaves
> > ugly glue into sxitimer written just for A20, which imho should also
> > get cleaned up.
> >
> > -Artturi
>
> There seem to be at least two diffs here, the different rtc handling
> for a20 should be split out, store sxirtc_a20 in the softc and fix
> the test from
> if (BOARD_ID_SUN7I_A20)
> to
> if (board_id == BOARD_ID_SUN7I_A20)
>

Yes, it was quick try during my morning coffee, i'm sorry to have wasted
your time with the previous obviously wrong diff.

sxitimer a20 support glue cleanup diff inline.

-Artturi

diff --git a/sys/arch/armv7/sunxi/sun7i.c b/sys/arch/armv7/sunxi/sun7i.c
index 0d06b31..d8fcd45 100644
--- a/sys/arch/armv7/sunxi/sun7i.c
+++ b/sys/arch/armv7/sunxi/sun7i.c
@@ -39,19 +39,6 @@ struct armv7_dev sxia20_devs[] = {
   .mem = { { CCMU_ADDR, CCMU_SIZE } },
  },
 
- /* Timers/Counters, resources mapped on first unit */
- { .name = "sxitimer",
-  .unit = 0,
-  .mem = { { TIMER_ADDR, TIMERx_SIZE },
- { CPUCNTRS_ADDR, CPUCNTRS_ADDR } }
- },
- { .name = "sxitimer",
-  .unit = 1,
- },
- { .name = "sxitimer",
-  .unit = 2,
- },
-
  /* Watchdog Timer */
  { .name = "sxidog",
   .unit = 0,
diff --git a/sys/arch/armv7/sunxi/sxitimer.c b/sys/arch/armv7/sunxi/sxitimer.c
index c07f85a..97eb51b 100644
--- a/sys/arch/armv7/sunxi/sxitimer.c
+++ b/sys/arch/armv7/sunxi/sxitimer.c
@@ -44,11 +44,6 @@
 #define TIMER_INTV(x) (0x14 + (0x10 * (x)))
 #define TIMER_CURR(x) (0x18 + (0x10 * (x)))
 
-/* A20 counter, relative to CPUCNTRS_ADDR */
-#define OSC24M_CNT64_CTRL 0x80
-#define OSC24M_CNT64_LOW 0x84
-#define OSC24M_CNT64_HIGH 0x88
-
 /* A1X counter */
 #define CNT64_CTRL 0xa0
 #define CNT64_LOW 0xa4
@@ -56,7 +51,6 @@
 
 #define CNT64_CLR_EN (1 << 0) /* clear enable */
 #define CNT64_RL_EN (1 << 1) /* read latch enable */
-#define CNT64_SYNCH (1 << 4) /* sync to OSC24M counter */
 
 #define LOSC_CTRL 0x100
 #define OSC32K_SRC_SEL (1 << 0)
@@ -99,7 +93,6 @@ static struct timecounter sxitimer_timecounter = {
 
 bus_space_tag_t sxitimer_iot;
 bus_space_handle_t sxitimer_ioh;
-bus_space_handle_t sxitimer_cntr_ioh;
 
 uint32_t sxitimer_freq[] = {
  TIMER0_FREQUENCY,
@@ -120,10 +113,6 @@ uint32_t sxitimer_statvar, sxitimer_statmin;
 uint32_t sxitimer_tick_nextevt, sxitimer_stat_nextevt;
 uint32_t sxitimer_ticks_err_cnt, sxitimer_ticks_err_sum;
 
-bus_addr_t cntr64_ctrl = CNT64_CTRL;
-bus_addr_t cntr64_low = CNT64_LOW;
-bus_addr_t cntr64_high = CNT64_HIGH;
-
 struct sxitimer_softc {
  struct device sc_dev;
 };
@@ -140,7 +129,7 @@ void
 sxitimer_attach(struct device *parent, struct device *self, void *args)
 {
  struct armv7_attach_args *aa = args;
- uint32_t freq, ival, now, cr, v;
+ uint32_t freq, ival, now, cr;
  int unit = self->dv_unit;
 
  if (unit != 0)
@@ -152,29 +141,10 @@ sxitimer_attach(struct device *parent, struct device *self, void *args)
     aa->aa_dev->mem[0].size, 0, &sxitimer_ioh))
  panic("sxitimer_attach: bus_space_map failed!");
 
-
- if (board_id == BOARD_ID_SUN7I_A20) {
- if (bus_space_map(sxitimer_iot, CPUCNTRS_ADDR, CPUCNTRS_SIZE,
-    0, &sxitimer_cntr_ioh))
- panic("sxitimer_attach: bus_space_map failed!");
-
- cntr64_ctrl = OSC24M_CNT64_CTRL;
- cntr64_low = OSC24M_CNT64_LOW;
- cntr64_high = OSC24M_CNT64_HIGH;
-
- v = bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh,
-    cntr64_ctrl);
- bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl,
-    v | CNT64_SYNCH);
- bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl,
-    v & ~CNT64_SYNCH);
- } else
- sxitimer_cntr_ioh = sxitimer_ioh;
-
  /* clear counter, loop until ready */
- bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl,
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL,
     CNT64_CLR_EN); /* XXX as a side-effect counter clk src=OSC24M */
- while (bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl)
+ while (bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL)
     & CNT64_CLR_EN)
  continue;
 
@@ -398,9 +368,8 @@ sxitimer_readcnt64(void)
  uint32_t low, high;
 
  /* latch counter, loop until ready */
- bus_space_write_4(sxitimer_iot, sxitimer_cntr_ioh,
-    cntr64_ctrl, CNT64_RL_EN);
- while (bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_ctrl)
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL, CNT64_RL_EN);
+ while (bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL)
     & CNT64_RL_EN)
  continue;
 
@@ -409,8 +378,8 @@ sxitimer_readcnt64(void)
  * iirc. A20 manual mentions that low should be read first.
  */
  /* XXX check above */
- low = bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_low);
- high = bus_space_read_4(sxitimer_iot, sxitimer_cntr_ioh, cntr64_high);
+ low = bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_LOW);
+ high = bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_HIGH);
  return (uint64_t)high << 32 | low;
 }
 

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Re: sunxi: don't use sxitimer on the sun7i/A20

Artturi Alm
In reply to this post by Jonathan Gray-11
On Sun, Jan 31, 2016 at 10:45:42PM +1100, Jonathan Gray wrote:

> On Sun, Jan 31, 2016 at 10:12:05AM +0200, Artturi Alm wrote:
> > On Sun, Jan 31, 2016 at 01:14:35AM +0100, Patrick Wildt wrote:
> > > Hi,
> > >
> > > one of the reasons Allwinner A20/sun7i-based boards, like the
> > > Cubieboard 2 or Banana Pi, don't boot is that the sxitimer does
> > > not work for us.  We are getting no hardclock ticks and so the
> > > system can't work.
> > >
> > > There's a simple fix for that.  We can just not use the sxitimer
> > > and instead use the ARM architected timer (agtimer) that is
> > > supposed to be a generic implementation for all new cores and
> > > already attaches anyway.  The sxitimer attachment currently
> > > overrides the agtimer.  Removing sxitimer thus allows agtimer
> > > to actually do its work.
> > >
> > > Currently sxirtc uncondtionally ties into sxitimer.  To make
> > > this work, just make sxirtc map its own page instead of relying
> > > on the existence of a mapping created by sxitimer.
> > >
> > > The address/size used for the sxirtc is from a device tree
> > > source.
> > >
> > > Patrick
> > >
> >
> > Hi,
> >
> > nothing i would change about your diff, given now there's agtimer,
> > but it doesn't really seem to even try fixing rtc on A20, and leaves
> > ugly glue into sxitimer written just for A20, which imho should also
> > get cleaned up.
> >
> > -Artturi
>
> There seem to be at least two diffs here, the different rtc handling
> for a20 should be split out, store sxirtc_a20 in the softc and fix
> the test from
> if (BOARD_ID_SUN7I_A20)
> to
> if (board_id == BOARD_ID_SUN7I_A20)
>

And another version of a20 support for sxirtc, with another fix in _settime().

-Artturi

diff --git a/sys/arch/armv7/sunxi/sxirtc.c b/sys/arch/armv7/sunxi/sxirtc.c
index 32460d6..a902285 100644
--- a/sys/arch/armv7/sunxi/sxirtc.c
+++ b/sys/arch/armv7/sunxi/sxirtc.c
@@ -15,9 +15,6 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-/* XXX this doesn't support A20 yet. */
- /* year & 0xff on A20, 0x3f on A10 */
- /* leap << 24 on A20, << 22 on A10 */
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -40,15 +37,15 @@
     (y) % 400 == 0)
 
 
-/* XXX other way around than bus_space_subregion? */
-extern bus_space_handle_t sxitimer_ioh;
-
 extern todr_chip_handle_t todr_handle;
 
 struct sxirtc_softc {
  struct device sc_dev;
  bus_space_tag_t sc_iot;
  bus_space_handle_t sc_ioh;
+ uint32_t base_year;
+ uint32_t year_mask;
+ uint32_t leap_shift;
 };
 
 void sxirtc_attach(struct device *, struct device *, void *);
@@ -78,7 +75,17 @@ sxirtc_attach(struct device *parent, struct device *self, void *args)
  sc->sc_iot = aa->aa_iot;
  if (bus_space_map(sc->sc_iot, aa->aa_dev->mem[0].addr,
     aa->aa_dev->mem[0].size, 0, &sc->sc_ioh))
- panic("sxirtc_attach: bus_space_subregion failed!");
+ panic("sxirtc_attach: bus_space_map failed!");
+
+ if (board_id == BOARD_ID_SUN7I_A20) {
+ sc->base_year = 1970;
+ sc->year_mask = 0xff;
+ sc->leap_shift = 24;
+ } else {
+ sc->base_year = 2010;
+ sc->year_mask = 0x3f;
+ sc->leap_shift = 22;
+ }
 
  handle->cookie = self;
  handle->todr_gettime = sxirtc_gettime;
@@ -108,7 +115,7 @@ sxirtc_gettime(todr_chip_handle_t handle, struct timeval *tv)
  reg = SXIREAD4(sc, SXIRTC_YYMMDD);
  dt.dt_day = reg & 0x1f;
  dt.dt_mon = reg >> 8 & 0x0f;
- dt.dt_year = (reg >> 16 & 0x3f) + 2010; /* 0xff on A20 */
+ dt.dt_year = (reg >> 16 & sc->year_mask) + sc->base_year;
 
  if (dt.dt_sec > 59 || dt.dt_min > 59 ||
     dt.dt_hour > 23 || dt.dt_wday > 6 ||
@@ -139,9 +146,10 @@ sxirtc_settime(todr_chip_handle_t handle, struct timeval *tv)
     dt.dt_sec | (dt.dt_min << 8) | (dt.dt_hour << 16) |
     (dt.dt_wday << 29));
 
- SXICMS4(sc, SXIRTC_YYMMDD, 0x00400000 | 0x003f0000 | 0x0f00 | 0x1f,
-   dt.dt_day | (dt.dt_mon << 8) | ((dt.dt_year - 2010) << 16) |
-   (LEAPYEAR(dt.dt_year) << 22));
+ SXICMS4(sc, SXIRTC_YYMMDD, 0x00400000 | (sc->year_mask << 16) |
+    0x0f00 | 0x1f, dt.dt_day | (dt.dt_mon << 8) |
+    ((dt.dt_year - sc->base_year) << 16) |
+    (LEAPYEAR(dt.dt_year) << sc->leap_shift));
 
  return 0;
 }

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Re: sunxi: don't use sxitimer on the sun7i/A20

Jonathan Gray-11
In reply to this post by Artturi Alm
On Mon, Feb 01, 2016 at 02:55:52AM +0200, Artturi Alm wrote:

> On Sun, Jan 31, 2016 at 10:45:42PM +1100, Jonathan Gray wrote:
> > On Sun, Jan 31, 2016 at 10:12:05AM +0200, Artturi Alm wrote:
> > > On Sun, Jan 31, 2016 at 01:14:35AM +0100, Patrick Wildt wrote:
> > > > Hi,
> > > >
> > > > one of the reasons Allwinner A20/sun7i-based boards, like the
> > > > Cubieboard 2 or Banana Pi, don't boot is that the sxitimer does
> > > > not work for us.  We are getting no hardclock ticks and so the
> > > > system can't work.
> > > >
> > > > There's a simple fix for that.  We can just not use the sxitimer
> > > > and instead use the ARM architected timer (agtimer) that is
> > > > supposed to be a generic implementation for all new cores and
> > > > already attaches anyway.  The sxitimer attachment currently
> > > > overrides the agtimer.  Removing sxitimer thus allows agtimer
> > > > to actually do its work.
> > > >
> > > > Currently sxirtc uncondtionally ties into sxitimer.  To make
> > > > this work, just make sxirtc map its own page instead of relying
> > > > on the existence of a mapping created by sxitimer.
> > > >
> > > > The address/size used for the sxirtc is from a device tree
> > > > source.
> > > >
> > > > Patrick
> > > >
> > >
> > > Hi,
> > >
> > > nothing i would change about your diff, given now there's agtimer,
> > > but it doesn't really seem to even try fixing rtc on A20, and leaves
> > > ugly glue into sxitimer written just for A20, which imho should also
> > > get cleaned up.
> > >
> > > -Artturi
> >
> > There seem to be at least two diffs here, the different rtc handling
> > for a20 should be split out, store sxirtc_a20 in the softc and fix
> > the test from
> > if (BOARD_ID_SUN7I_A20)
> > to
> > if (board_id == BOARD_ID_SUN7I_A20)
> >
>
> Yes, it was quick try during my morning coffee, i'm sorry to have wasted
> your time with the previous obviously wrong diff.
>
> sxitimer a20 support glue cleanup diff inline.
>
> -Artturi

Thanks, both diffs committed.  Any chance you could create another to
move the sxitimer_* globals into the softc?

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Re: sunxi: don't use sxitimer on the sun7i/A20

Artturi Alm
On Tue, Feb 02, 2016 at 10:55:57AM +1100, Jonathan Gray wrote:

> On Mon, Feb 01, 2016 at 02:55:52AM +0200, Artturi Alm wrote:
> > On Sun, Jan 31, 2016 at 10:45:42PM +1100, Jonathan Gray wrote:
> > > On Sun, Jan 31, 2016 at 10:12:05AM +0200, Artturi Alm wrote:
> > > > On Sun, Jan 31, 2016 at 01:14:35AM +0100, Patrick Wildt wrote:
> > > > > Hi,
> > > > >
> > > > > one of the reasons Allwinner A20/sun7i-based boards, like the
> > > > > Cubieboard 2 or Banana Pi, don't boot is that the sxitimer does
> > > > > not work for us.  We are getting no hardclock ticks and so the
> > > > > system can't work.
> > > > >
> > > > > There's a simple fix for that.  We can just not use the sxitimer
> > > > > and instead use the ARM architected timer (agtimer) that is
> > > > > supposed to be a generic implementation for all new cores and
> > > > > already attaches anyway.  The sxitimer attachment currently
> > > > > overrides the agtimer.  Removing sxitimer thus allows agtimer
> > > > > to actually do its work.
> > > > >
> > > > > Currently sxirtc uncondtionally ties into sxitimer.  To make
> > > > > this work, just make sxirtc map its own page instead of relying
> > > > > on the existence of a mapping created by sxitimer.
> > > > >
> > > > > The address/size used for the sxirtc is from a device tree
> > > > > source.
> > > > >
> > > > > Patrick
> > > > >
> > > >
> > > > Hi,
> > > >
> > > > nothing i would change about your diff, given now there's agtimer,
> > > > but it doesn't really seem to even try fixing rtc on A20, and leaves
> > > > ugly glue into sxitimer written just for A20, which imho should also
> > > > get cleaned up.
> > > >
> > > > -Artturi
> > >
> > > There seem to be at least two diffs here, the different rtc handling
> > > for a20 should be split out, store sxirtc_a20 in the softc and fix
> > > the test from
> > > if (BOARD_ID_SUN7I_A20)
> > > to
> > > if (board_id == BOARD_ID_SUN7I_A20)
> > >
> >
> > Yes, it was quick try during my morning coffee, i'm sorry to have wasted
> > your time with the previous obviously wrong diff.
> >
> > sxitimer a20 support glue cleanup diff inline.
> >
> > -Artturi
>
> Thanks, both diffs committed.  Any chance you could create another to
> move the sxitimer_* globals into the softc?

Sure, here's fix for sxidog while waiting, i know the mapping does overlap
with sxitimer, but that is what sxirtc already does too since Patrick's diff
without problems.
As is, sxidog is the last user of 'extern bus_.._t sxitimer_ioh;', and use of
it on A20 is now obviously wrong, and might mean that reboot ends up spinning.

-Artturi


diff --git a/sys/arch/armv7/sunxi/sunxireg.h b/sys/arch/armv7/sunxi/sunxireg.h
index 323264b..c82990c 100644
--- a/sys/arch/armv7/sunxi/sunxireg.h
+++ b/sys/arch/armv7/sunxi/sunxireg.h
@@ -65,7 +65,7 @@
 #define TIMER2_IRQ 24
 #define STATTIMER_IRQ TIMER1_IRQ /* XXX */
 
-#define WDOG_ADDR 0x90
+#define WDOG_ADDR 0x01c20c90
 #define WDOG_SIZE 0x08
 #define WDOG_IRQ 24
 
diff --git a/sys/arch/armv7/sunxi/sxidog.c b/sys/arch/armv7/sunxi/sxidog.c
index 6212e58..347b534 100644
--- a/sys/arch/armv7/sunxi/sxidog.c
+++ b/sys/arch/armv7/sunxi/sxidog.c
@@ -30,9 +30,6 @@
 #include <armv7/sunxi/sunxireg.h>
 #include <armv7/armv7/armv7var.h>
 
-/* XXX other way around than bus_space_subregion? */
-extern bus_space_handle_t sxitimer_ioh;
-
 /* registers */
 #define WDOG_CR 0x00
 #define WDOG_MR 0x04
@@ -89,9 +86,9 @@ sxidog_attach(struct device *parent, struct device *self, void *args)
  struct sxidog_softc *sc = (struct sxidog_softc *)self;
 
  sc->sc_iot = aa->aa_iot;
- if (bus_space_subregion(sc->sc_iot, sxitimer_ioh,
-    aa->aa_dev->mem[0].addr, aa->aa_dev->mem[0].size, &sc->sc_ioh))
- panic("sxidog_attach: bus_space_subregion failed!");
+ if (bus_space_map(sc->sc_iot, aa->aa_dev->mem[0].addr,
+    aa->aa_dev->mem[0].size, 0, &sc->sc_ioh))
+ panic("sxidog_attach: bus_space_map failed!");
 
 #ifdef DEBUG
  printf(": ctrl %x mode %x\n", SXIREAD4(sc, WDOG_CR),

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Re: sunxi: don't use sxitimer on the sun7i/A20

Daniel Bolgheroni-3
In reply to this post by Jonathan Gray-11
On Tue, Feb 02, 2016 at 10:55:57AM +1100, Jonathan Gray wrote:
> Thanks, both diffs committed.  Any chance you could create another to
> move the sxitimer_* globals into the softc?

I didn't have time to test each diff separately, but now my Cubieboard 2 stops
at sxidog (log below). I'm expecting the same results on Banana Pi. The kernel
also includes the pmap bits, and since it stopped on uvm_fault(), maybe they
can be related.

U-Boot SPL 2015.10-dirty (Nov 10 2015 - 21:14:20)
DRAM: 1024 MiB
CPU: 912000000Hz, AXI/AHB/APB: 3/2/2


U-Boot 2015.10-dirty (Nov 10 2015 - 21:14:20 -0200) Allwinner Technology

CPU:   Allwinner A20 (SUN7I)
I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
SCSI:  SUNXI SCSI INIT
SATA link 0 timeout.
AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net:   eth0: ethernet@01c50000
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
USB2:   USB EHCI 1.00
USB3:   USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
Hit any key to stop autoboot:  0
=> setenv ipaddr 192.168.1.7; setenv serverip 192.168.1.5; tftpboot bsd.rd.SUNXI.umg; bootm
Speed: 100, full duplex
Using ethernet@01c50000 device
TFTP from server 192.168.1.5; our IP address is 192.168.1.7
Filename 'bsd.rd.SUNXI.umg'.
Load address: 0x42000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         ##############################
         3.2 MiB/s
done
Bytes transferred = 8066788 (7b16e4 hex)
## Booting kernel from Legacy Image at 42000000 ...
   Image Name:   boot
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    8066724 Bytes = 7.7 MiB
   Load Address: 40300000
   Entry Point:  40300000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

Starting kernel ...


OpenBSD/sunxi booting ...
arg0 0x0 arg1 0x10bb arg2 0x40000100
atag core flags 0 pagesize 0 rootdev 0
atag serial 0x16516616:0b01944c
atag mem start 0x40000000 size 0x40000000
bootfile:
bootargs:
memory size derived from u-boot
bootconf.mem[0].address = 40000000 pages 262144/0x40000000
physmemory: 262144 pages at 0x40000000 -> 0x7fffffff
Allocating page tables
freestart = 0x40ab2000, free_pages = 259406 (0x0003f54e)
IRQ stack: p0x40ae0000 v0xc0ae0000
ABT stack: p0x40ae1000 v0xc0ae1000
UND stack: p0x40ae2000 v0xc0ae2000
SVC stack: p0x40ae3000 v0xc0ae3000
Creating L1 page table at 0x40ab4000
Mapping kernel
Constructing L2 page tables
undefined page pmap board type: 4283
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2016 OpenBSD. All rights reserved.  http://www.OpenBSD.org

OpenBSD 5.9-beta (RAMDISK) #20: Sat Jan 30 16:37:27 BRST 2016
    [hidden email]:/usr/src/sys/arch/armv7/compile/RAMDISK
real mem  = 1073741824 (1024MB)
avail mem = 1041637376 (993MB)
mainbus0 at root
cortex0 at mainbus0
ampintc0 at cortex0 nirq 160
agtimer0 at cortex0: tick rate 24000 KHz
cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
sunxi0 at mainbus0: Allwinner A20
sxipio0 at sunxi0
sxiccmu0 at sunxi0
sxidog0 at sunxi0
uvm_fault(0xc0a4ecf8, 0, 1, 0) -> e
Fatal kernel mode data abort: 'Translation Fault (S)'
trapframe: 0xc0ae4dec
DFSR=00000005, DFAR=00000090, spsr=60000153
r0 =00000000, r1 =00000090, r2 =00000000, r3 =c0a04d74
r4 =c0a04d74, r5 =c53cb1c0, r6 =c0a0c498, r7 =c0a529b0
r8 =c53cb140, r9 =00000000, r10=c0ae4e88, r11=c0ae4e50
r12=c53cb1f4, ssp=c0ae4e38, slr=c04a3444, pc =c0413858

panic: Fatal abort
The operating system has halted.
Please press any key to reboot.

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Re: sunxi: don't use sxitimer on the sun7i/A20

Jonathan Gray-11
On Tue, Feb 02, 2016 at 10:57:41PM -0200, Daniel Bolgheroni wrote:
> On Tue, Feb 02, 2016 at 10:55:57AM +1100, Jonathan Gray wrote:
> > Thanks, both diffs committed.  Any chance you could create another to
> > move the sxitimer_* globals into the softc?
>
> I didn't have time to test each diff separately, but now my Cubieboard 2 stops
> at sxidog (log below). I'm expecting the same results on Banana Pi. The kernel
> also includes the pmap bits, and since it stopped on uvm_fault(), maybe they
> can be related.

You'll want a kernel with the sxidog patch that was committed earlier today.

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Re: sunxi: don't use sxitimer on the sun7i/A20

Daniel Bolgheroni-3
On Wed, Feb 03, 2016 at 12:31:33PM +1100, Jonathan Gray wrote:
> You'll want a kernel with the sxidog patch that was committed earlier today.

That's right. Thank you. However, stressing it out a little further, sometimes
I still get some pmap-related issues. Maybe something related to U-Boot?

I have 3 cases here. Most of the times I get what it's in case 3 (ok). However,
I occasionally get something like case 1 and case 2.

#################### case 1 ####################

U-Boot SPL 2015.10-dirty (Nov 10 2015 - 21:14:20)
DRAM: 1024 MiB
CPU: 912000000Hz, AXI/AHB/APB: 3/2/2


U-Boot 2015.10-dirty (Nov 10 2015 - 21:14:20 -0200) Allwinner Technology

CPU:   Allwinner A20 (SUN7I)
I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
SCSI:  SUNXI SCSI INIT
SATA link 0 timeout.
AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net:   eth0: ethernet@01c50000
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
USB2:   USB EHCI 1.00
USB3:   USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
Hit any key to stop autoboot:  0
=> setenv ipaddr 192.168.1.7; setenv serverip 192.168.1.5; tftpboot bsd.rd.SUNXI.umg; bootm
Speed: 100, full duplex
Using ethernet@01c50000 device
TFTP from server 192.168.1.5; our IP address is 192.168.1.7
Filename 'bsd.rd.SUNXI.umg'.
Load address: 0x42000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         ############################
         3.2 MiB/s
done
Bytes transferred = 8032508 (7a90fc hex)
## Booting kernel from Legacy Image at 42000000 ...
   Image Name:   boot
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    8032444 Bytes = 7.7 MiB
   Load Address: 40300000
   Entry Point:  40300000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

Starting kernel ...


OpenBSD/sunxi booting ...
arg0 0x0 arg1 0x10bb arg2 0x40000100
atag core flags 0 pagesize 0 rootdev 0
atag serial 0x16516616:0b01944c
atag mem start 0x40000000 size 0x40000000
bootfile:
bootargs:
memory size derived from u-boot
bootconf.mem[0].address = 40000000 pages 262144/0x40000000
Allocating page tables
freestart = 0x40aaa000, free_pages = 259414 (0x0003f556)
IRQ stack: p0x40ad8000 v0xc0ad8000
ABT stack: p0x40ad9000 v0xc0ad9000
UND stack: p0x40ada000 v0xc0ada000
SVC stack: p0x40adb000 v0xc0adb000
Creating L1 page table at 0x40aac000
Mapping kernel
Constructing L2 page tables
undefined page pmap board type: 4283
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2016 OpenBSD. All rights reserved.  http://www.OpenBSD.org

OpenBSD 5.9 (RAMDISK) #25: Sun Jan 31 23:07:09 BRST 2016
    [hidden email]:/usr/src/sys/arch/armv7/compile/RAMDISK
real mem  = 1073741824 (1024MB)
avail mem = 1041670144 (993MB)
mainbus0 at root
cortex0 at mainbus0
ampintc0 at cortex0 nirq 160
agtimer0 at cortex0: tick rate 24000 KHz
cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
sunxi0 at mainbus0: Allwinner A20
sxipio0 at sunxi0
sxiccmu0 at sunxi0
sxidog0 at sunxi0
sxirtc0 at sunxi0
sxiuart0 at sunxi0: console
sxiuart1 at sunxi0
sxiuart2 at sunxi0
sxiuart3 at sunxi0
sxiuart4 at sunxi0
sxiuart5 at sunxi0
sxiuart6 at sunxi0
sxiuart7 at sunxi0
sxie0 at sunxi0, address 02:16:0b:01:94:4c
rlphy0 at sxie0 phy 1: RTL8201L 10/100 PHY, rev. 1
ahci0 at sunxi0 AHCI 1.1
scsibus0 at ahci0: 32 targets
ehci0 at sunxi0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
ehci1 at sunxi0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
gpio0 at sxipio0: 18 pins
gpio1 at sxipio0: 24 pins
gpio2 at sxipio0: 25 pins
gpio3 at sxipio0: 28 pins
gpio4 at sxipio0: 12 pins
gpio5 at sxipio0: 6 pins
gpio6 at sxipio0: 12 pins
gpio7 at sxipio0: 28 pins
gpio8 at sxipio0: 22 pins
boot device: lookup '' failed.
root on rd0a swap on rd0b dump on rd0b
WARNING: clock lost 16831 days
WARNING: CHECK AND RESET THE DATE!
erase ^?, werase ^W, kill ^U, intr ^C, status ^T

uvm_fault(0xca4a91c8, 8000, 2, 0) -> d
Fatal kernel mode data abort: 'Translation Fault (P)'
trapframe: 0xcc3c6de0
DFSR=00002807, DFAR=00008000, spsr=80000113
r0 =00008000, r1 =00000fff, r2 =00000000, r3 =0000003f
r4 =cc3c7000, r5 =ca4a8838, r6 =00000005, r7 =00000000
r8 =c0a6a9e8, r9 =c0a6b1a0, r10=c0a6a9e8, r11=cc3c6e74
r12=00000040, ssp=cc3c6e2c, slr=c0410228, pc =c0408b08

panic: Fatal abort
syncing disks... done
rebooting...

#################### case 2 ####################

U-Boot 2015.10-dirty (Nov 10 2015 - 21:14:20 -0200) Allwinner Technology

CPU:   Allwinner A20 (SUN7I)
I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
SCSI:  SUNXI SCSI INIT
SATA link 0 timeout.
AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net:   eth0: ethernet@01c50000
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
USB2:   USB EHCI 1.00
USB3:   USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
Hit any key to stop autoboot:  0
=> setenv ipaddr 192.168.1.7; setenv serverip 192.168.1.5; tftpboot bsd.rd.SUNXI.umg; bootm
Speed: 100, full duplex
Using ethernet@01c50000 device
TFTP from server 192.168.1.5; our IP address is 192.168.1.7
Filename 'bsd.rd.SUNXI.umg'.
Load address: 0x42000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         ############################
         3.2 MiB/s
done
Bytes transferred = 8032508 (7a90fc hex)
## Booting kernel from Legacy Image at 42000000 ...
   Image Name:   boot
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    8032444 Bytes = 7.7 MiB
   Load Address: 40300000
   Entry Point:  40300000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

Starting kernel ...


OpenBSD/sunxi booting ...
arg0 0x0 arg1 0x10bb arg2 0x40000100
atag core flags 0 pagesize 0 rootdev 0
atag serial 0x16516616:0b01944c
atag mem start 0x40000000 size 0x40000000
bootfile:
bootargs:
memory size derived from u-boot
bootconf.mem[0].address = 40000000 pages 262144/0x40000000
Allocating page tables
freestart = 0x40aaa000, free_pages = 259414 (0x0003f556)
IRQ stack: p0x40ad8000 v0xc0ad8000
ABT stack: p0x40ad9000 v0xc0ad9000
UND stack: p0x40ada000 v0xc0ada000
SVC stack: p0x40adb000 v0xc0adb000
Creating L1 page table at 0x40aac000
Mapping kernel
Constructing L2 page tables
undefined page pmap board type: 4283
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2016 OpenBSD. All rights reserved.  http://www.OpenBSD.org

OpenBSD 5.9 (RAMDISK) #25: Sun Jan 31 23:07:09 BRST 2016
    [hidden email]:/usr/src/sys/arch/armv7/compile/RAMDISK
real mem  = 1073741824 (1024MB)
avail mem = 1041670144 (993MB)
mainbus0 at root
cortex0 at mainbus0
ampintc0 at cortex0 nirq 160
agtimer0 at cortex0: tick rate 24000 KHz
cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
sunxi0 at mainbus0: Allwinner A20
sxipio0 at sunxi0
sxiccmu0 at sunxi0
sxidog0 at sunxi0
sxirtc0 at sunxi0
sxiuart0 at sunxi0: console
sxiuart1 at sunxi0
sxiuart2 at sunxi0
sxiuart3 at sunxi0
sxiuart4 at sunxi0
sxiuart5 at sunxi0
sxiuart6 at sunxi0
sxiuart7 at sunxi0
sxie0 at sunxi0, address 02:16:0b:01:94:4c
rlphy0 at sxie0 phy 1: RTL8201L 10/100 PHY, rev. 1
ahci0 at sunxi0 AHCI 1.1
scsibus0 at ahci0: 32 targets
ehci0 at sunxi0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
ehci1 at sunxi0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
gpio0 at sxipio0: 18 pins
gpio1 at sxipio0: 24 pins
gpio2 at sxipio0: 25 pins
gpio3 at sxipio0: 28 pins
gpio4 at sxipio0: 12 pins
gpio5 at sxipio0: 6 pins
gpio6 at sxipio0: 12 pins
gpio7 at sxipio0: 28 pins
gpio8 at sxipio0: 22 pins
boot device: lookup '' failed.
root on rd0a swap on rd0b dump on rd0b
WARNING: clock lost 16832 days
WARNING: CHECK AND RESET THE DATE!
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
erase ^?, werase ^W, kill ^U, intr ^C, status ^T

Welcome to the OpenBSD/armv7 5.9 installation program.
(I)nstall, (U)pgrade, (A)utoinstall or (S)hell?

#################### case 3 ####################

U-Boot 2015.10-dirty (Nov 10 2015 - 21:14:20 -0200) Allwinner Technology

CPU:   Allwinner A20 (SUN7I)
I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
SCSI:  SUNXI SCSI INIT
SATA link 0 timeout.
AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net:   eth0: ethernet@01c50000
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
USB2:   USB EHCI 1.00
USB3:   USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
Hit any key to stop autoboot:  0
=> setenv ipaddr 192.168.1.7; setenv serverip 192.168.1.5; tftpboot bsd.rd.SUNXI.umg; bootm
Speed: 100, full duplex
Using ethernet@01c50000 device
TFTP from server 192.168.1.5; our IP address is 192.168.1.7
Filename 'bsd.rd.SUNXI.umg'.
Load address: 0x42000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         ############################
         3.2 MiB/s
done
Bytes transferred = 8032508 (7a90fc hex)
## Booting kernel from Legacy Image at 42000000 ...
   Image Name:   boot
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    8032444 Bytes = 7.7 MiB
   Load Address: 40300000
   Entry Point:  40300000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

Starting kernel ...


OpenBSD/sunxi booting ...
arg0 0x0 arg1 0x10bb arg2 0x40000100
atag core flags 0 pagesize 0 rootdev 0
atag serial 0x16516616:0b01944c
atag mem start 0x40000000 size 0x40000000
bootfile:
bootargs:
memory size derived from u-boot
bootconf.mem[0].address = 40000000 pages 262144/0x40000000
Allocating page tables
freestart = 0x40aaa000, free_pages = 259414 (0x0003f556)
IRQ stack: p0x40ad8000 v0xc0ad8000
ABT stack: p0x40ad9000 v0xc0ad9000
UND stack: p0x40ada000 v0xc0ada000
SVC stack: p0x40adb000 v0xc0adb000
Creating L1 page table at 0x40aac000
Mapping kernel
Constructing L2 page tables
undefined page pmap board type: 4283
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2016 OpenBSD. All rights reserved.  http://www.OpenBSD.org

OpenBSD 5.9 (RAMDISK) #25: Sun Jan 31 23:07:09 BRST 2016
    [hidden email]:/usr/src/sys/arch/armv7/compile/RAMDISK
real mem  = 1073741824 (1024MB)
avail mem = 1041670144 (993MB)
mainbus0 at root
cortex0 at mainbus0
ampintc0 at cortex0 nirq 160
agtimer0 at cortex0: tick rate 24000 KHz
cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
sunxi0 at mainbus0: Allwinner A20
sxipio0 at sunxi0
sxiccmu0 at sunxi0
sxidog0 at sunxi0
sxirtc0 at sunxi0
sxiuart0 at sunxi0: console
sxiuart1 at sunxi0
sxiuart2 at sunxi0
sxiuart3 at sunxi0
sxiuart4 at sunxi0
sxiuart5 at sunxi0
sxiuart6 at sunxi0
sxiuart7 at sunxi0
sxie0 at sunxi0, address 02:16:0b:01:94:4c
rlphy0 at sxie0 phy 1: RTL8201L 10/100 PHY, rev. 1
ahci0 at sunxi0 AHCI 1.1
scsibus0 at ahci0: 32 targets
ehci0 at sunxi0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
ehci1 at sunxi0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
gpio0 at sxipio0: 18 pins
gpio1 at sxipio0: 24 pins
gpio2 at sxipio0: 25 pins
gpio3 at sxipio0: 28 pins
gpio4 at sxipio0: 12 pins
gpio5 at sxipio0: 6 pins
gpio6 at sxipio0: 12 pins
gpio7 at sxipio0: 28 pins
gpio8 at sxipio0: 22 pins
boot device: lookup '' failed.
root on rd0a swap on rd0b dump on rd0b
WARNING: clock lost 16832 days
WARNING: CHECK AND RESET THE DATE!
erase ^?, werase ^W, kill ^U, intr ^C, status ^T

Welcome to the OpenBSD/armv7 5.9 installation program.
(I)nstall, (U)pgrade, (A)utoinstall or (S)hell?

--
db

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Re: sunxi: don't use sxitimer on the sun7i/A20

Patrick Wildt-3
On Wed, Feb 03, 2016 at 01:10:57PM -0200, Daniel Bolgheroni wrote:
> On Wed, Feb 03, 2016 at 12:31:33PM +1100, Jonathan Gray wrote:
> > You'll want a kernel with the sxidog patch that was committed earlier today.
>
> That's right. Thank you. However, stressing it out a little further, sometimes
> I still get some pmap-related issues. Maybe something related to U-Boot?
>
> I have 3 cases here. Most of the times I get what it's in case 3 (ok). However,
> I occasionally get something like case 1 and case 2.

Yes, that is known.  Here's what I told jsg@¬†about what it seems to be:

What happens is that for page reference emulation a page is first
inserted as not inserted.  Thus an access will fault and lead to the
fault fixup code.  The code realizes it's page referenced emulation,
hooks in the actual page and then returns.  Unfortunately the TLB seems
to not recognize the entry has changed and still remembers it as not
inserted.

The workaround I have is to invalidate the unified TLB on every PTE_SYNC
and PTE_SYNC_RANGE. PTE_SYNC is done directly after the page has
actually been inserted.

I need to get a better overview about when and how to handle the TLB
before I can propose anything.

Patrick

>
> #################### case 1 ####################
>
> U-Boot SPL 2015.10-dirty (Nov 10 2015 - 21:14:20)
> DRAM: 1024 MiB
> CPU: 912000000Hz, AXI/AHB/APB: 3/2/2
>
>
> U-Boot 2015.10-dirty (Nov 10 2015 - 21:14:20 -0200) Allwinner Technology
>
> CPU:   Allwinner A20 (SUN7I)
> I2C:   ready
> DRAM:  1 GiB
> MMC:   SUNXI SD/MMC: 0
> *** Warning - bad CRC, using default environment
>
> In:    serial
> Out:   serial
> Err:   serial
> SCSI:  SUNXI SCSI INIT
> SATA link 0 timeout.
> AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
> flags: ncq stag pm led clo only pmp pio slum part ccc apst
> Net:   eth0: ethernet@01c50000
> starting USB...
> USB0:   USB EHCI 1.00
> USB1:   USB OHCI 1.0
> USB2:   USB EHCI 1.00
> USB3:   USB OHCI 1.0
> scanning bus 0 for devices... 1 USB Device(s) found
> scanning bus 2 for devices... 1 USB Device(s) found
> Hit any key to stop autoboot:  0
> => setenv ipaddr 192.168.1.7; setenv serverip 192.168.1.5; tftpboot bsd.rd.SUNXI.umg; bootm
> Speed: 100, full duplex
> Using ethernet@01c50000 device
> TFTP from server 192.168.1.5; our IP address is 192.168.1.7
> Filename 'bsd.rd.SUNXI.umg'.
> Load address: 0x42000000
> Loading: #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          ############################
>          3.2 MiB/s
> done
> Bytes transferred = 8032508 (7a90fc hex)
> ## Booting kernel from Legacy Image at 42000000 ...
>    Image Name:   boot
>    Image Type:   ARM Linux Kernel Image (uncompressed)
>    Data Size:    8032444 Bytes = 7.7 MiB
>    Load Address: 40300000
>    Entry Point:  40300000
>    Verifying Checksum ... OK
>    Loading Kernel Image ... OK
>
> Starting kernel ...
>
>
> OpenBSD/sunxi booting ...
> arg0 0x0 arg1 0x10bb arg2 0x40000100
> atag core flags 0 pagesize 0 rootdev 0
> atag serial 0x16516616:0b01944c
> atag mem start 0x40000000 size 0x40000000
> bootfile:
> bootargs:
> memory size derived from u-boot
> bootconf.mem[0].address = 40000000 pages 262144/0x40000000
> Allocating page tables
> freestart = 0x40aaa000, free_pages = 259414 (0x0003f556)
> IRQ stack: p0x40ad8000 v0xc0ad8000
> ABT stack: p0x40ad9000 v0xc0ad9000
> UND stack: p0x40ada000 v0xc0ada000
> SVC stack: p0x40adb000 v0xc0adb000
> Creating L1 page table at 0x40aac000
> Mapping kernel
> Constructing L2 page tables
> undefined page pmap board type: 4283
> Copyright (c) 1982, 1986, 1989, 1991, 1993
>         The Regents of the University of California.  All rights reserved.
> Copyright (c) 1995-2016 OpenBSD. All rights reserved.  http://www.OpenBSD.org
>
> OpenBSD 5.9 (RAMDISK) #25: Sun Jan 31 23:07:09 BRST 2016
>     [hidden email]:/usr/src/sys/arch/armv7/compile/RAMDISK
> real mem  = 1073741824 (1024MB)
> avail mem = 1041670144 (993MB)
> mainbus0 at root
> cortex0 at mainbus0
> ampintc0 at cortex0 nirq 160
> agtimer0 at cortex0: tick rate 24000 KHz
> cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> sunxi0 at mainbus0: Allwinner A20
> sxipio0 at sunxi0
> sxiccmu0 at sunxi0
> sxidog0 at sunxi0
> sxirtc0 at sunxi0
> sxiuart0 at sunxi0: console
> sxiuart1 at sunxi0
> sxiuart2 at sunxi0
> sxiuart3 at sunxi0
> sxiuart4 at sunxi0
> sxiuart5 at sunxi0
> sxiuart6 at sunxi0
> sxiuart7 at sunxi0
> sxie0 at sunxi0, address 02:16:0b:01:94:4c
> rlphy0 at sxie0 phy 1: RTL8201L 10/100 PHY, rev. 1
> ahci0 at sunxi0 AHCI 1.1
> scsibus0 at ahci0: 32 targets
> ehci0 at sunxi0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
> ehci1 at sunxi0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
> gpio0 at sxipio0: 18 pins
> gpio1 at sxipio0: 24 pins
> gpio2 at sxipio0: 25 pins
> gpio3 at sxipio0: 28 pins
> gpio4 at sxipio0: 12 pins
> gpio5 at sxipio0: 6 pins
> gpio6 at sxipio0: 12 pins
> gpio7 at sxipio0: 28 pins
> gpio8 at sxipio0: 22 pins
> boot device: lookup '' failed.
> root on rd0a swap on rd0b dump on rd0b
> WARNING: clock lost 16831 days
> WARNING: CHECK AND RESET THE DATE!
> erase ^?, werase ^W, kill ^U, intr ^C, status ^T
>
> uvm_fault(0xca4a91c8, 8000, 2, 0) -> d
> Fatal kernel mode data abort: 'Translation Fault (P)'
> trapframe: 0xcc3c6de0
> DFSR=00002807, DFAR=00008000, spsr=80000113
> r0 =00008000, r1 =00000fff, r2 =00000000, r3 =0000003f
> r4 =cc3c7000, r5 =ca4a8838, r6 =00000005, r7 =00000000
> r8 =c0a6a9e8, r9 =c0a6b1a0, r10=c0a6a9e8, r11=cc3c6e74
> r12=00000040, ssp=cc3c6e2c, slr=c0410228, pc =c0408b08
>
> panic: Fatal abort
> syncing disks... done
> rebooting...
>
> #################### case 2 ####################
>
> U-Boot 2015.10-dirty (Nov 10 2015 - 21:14:20 -0200) Allwinner Technology
>
> CPU:   Allwinner A20 (SUN7I)
> I2C:   ready
> DRAM:  1 GiB
> MMC:   SUNXI SD/MMC: 0
> *** Warning - bad CRC, using default environment
>
> In:    serial
> Out:   serial
> Err:   serial
> SCSI:  SUNXI SCSI INIT
> SATA link 0 timeout.
> AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
> flags: ncq stag pm led clo only pmp pio slum part ccc apst
> Net:   eth0: ethernet@01c50000
> starting USB...
> USB0:   USB EHCI 1.00
> USB1:   USB OHCI 1.0
> USB2:   USB EHCI 1.00
> USB3:   USB OHCI 1.0
> scanning bus 0 for devices... 1 USB Device(s) found
> scanning bus 2 for devices... 1 USB Device(s) found
> Hit any key to stop autoboot:  0
> => setenv ipaddr 192.168.1.7; setenv serverip 192.168.1.5; tftpboot bsd.rd.SUNXI.umg; bootm
> Speed: 100, full duplex
> Using ethernet@01c50000 device
> TFTP from server 192.168.1.5; our IP address is 192.168.1.7
> Filename 'bsd.rd.SUNXI.umg'.
> Load address: 0x42000000
> Loading: #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          ############################
>          3.2 MiB/s
> done
> Bytes transferred = 8032508 (7a90fc hex)
> ## Booting kernel from Legacy Image at 42000000 ...
>    Image Name:   boot
>    Image Type:   ARM Linux Kernel Image (uncompressed)
>    Data Size:    8032444 Bytes = 7.7 MiB
>    Load Address: 40300000
>    Entry Point:  40300000
>    Verifying Checksum ... OK
>    Loading Kernel Image ... OK
>
> Starting kernel ...
>
>
> OpenBSD/sunxi booting ...
> arg0 0x0 arg1 0x10bb arg2 0x40000100
> atag core flags 0 pagesize 0 rootdev 0
> atag serial 0x16516616:0b01944c
> atag mem start 0x40000000 size 0x40000000
> bootfile:
> bootargs:
> memory size derived from u-boot
> bootconf.mem[0].address = 40000000 pages 262144/0x40000000
> Allocating page tables
> freestart = 0x40aaa000, free_pages = 259414 (0x0003f556)
> IRQ stack: p0x40ad8000 v0xc0ad8000
> ABT stack: p0x40ad9000 v0xc0ad9000
> UND stack: p0x40ada000 v0xc0ada000
> SVC stack: p0x40adb000 v0xc0adb000
> Creating L1 page table at 0x40aac000
> Mapping kernel
> Constructing L2 page tables
> undefined page pmap board type: 4283
> Copyright (c) 1982, 1986, 1989, 1991, 1993
>         The Regents of the University of California.  All rights reserved.
> Copyright (c) 1995-2016 OpenBSD. All rights reserved.  http://www.OpenBSD.org
>
> OpenBSD 5.9 (RAMDISK) #25: Sun Jan 31 23:07:09 BRST 2016
>     [hidden email]:/usr/src/sys/arch/armv7/compile/RAMDISK
> real mem  = 1073741824 (1024MB)
> avail mem = 1041670144 (993MB)
> mainbus0 at root
> cortex0 at mainbus0
> ampintc0 at cortex0 nirq 160
> agtimer0 at cortex0: tick rate 24000 KHz
> cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> sunxi0 at mainbus0: Allwinner A20
> sxipio0 at sunxi0
> sxiccmu0 at sunxi0
> sxidog0 at sunxi0
> sxirtc0 at sunxi0
> sxiuart0 at sunxi0: console
> sxiuart1 at sunxi0
> sxiuart2 at sunxi0
> sxiuart3 at sunxi0
> sxiuart4 at sunxi0
> sxiuart5 at sunxi0
> sxiuart6 at sunxi0
> sxiuart7 at sunxi0
> sxie0 at sunxi0, address 02:16:0b:01:94:4c
> rlphy0 at sxie0 phy 1: RTL8201L 10/100 PHY, rev. 1
> ahci0 at sunxi0 AHCI 1.1
> scsibus0 at ahci0: 32 targets
> ehci0 at sunxi0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
> ehci1 at sunxi0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
> gpio0 at sxipio0: 18 pins
> gpio1 at sxipio0: 24 pins
> gpio2 at sxipio0: 25 pins
> gpio3 at sxipio0: 28 pins
> gpio4 at sxipio0: 12 pins
> gpio5 at sxipio0: 6 pins
> gpio6 at sxipio0: 12 pins
> gpio7 at sxipio0: 28 pins
> gpio8 at sxipio0: 22 pins
> boot device: lookup '' failed.
> root on rd0a swap on rd0b dump on rd0b
> WARNING: clock lost 16832 days
> WARNING: CHECK AND RESET THE DATE!
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> pmap_fault_fixup: va 00008000 ftype 5 u pte 7ff3802e
> erase ^?, werase ^W, kill ^U, intr ^C, status ^T
>
> Welcome to the OpenBSD/armv7 5.9 installation program.
> (I)nstall, (U)pgrade, (A)utoinstall or (S)hell?
>
> #################### case 3 ####################
>
> U-Boot 2015.10-dirty (Nov 10 2015 - 21:14:20 -0200) Allwinner Technology
>
> CPU:   Allwinner A20 (SUN7I)
> I2C:   ready
> DRAM:  1 GiB
> MMC:   SUNXI SD/MMC: 0
> *** Warning - bad CRC, using default environment
>
> In:    serial
> Out:   serial
> Err:   serial
> SCSI:  SUNXI SCSI INIT
> SATA link 0 timeout.
> AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
> flags: ncq stag pm led clo only pmp pio slum part ccc apst
> Net:   eth0: ethernet@01c50000
> starting USB...
> USB0:   USB EHCI 1.00
> USB1:   USB OHCI 1.0
> USB2:   USB EHCI 1.00
> USB3:   USB OHCI 1.0
> scanning bus 0 for devices... 1 USB Device(s) found
> scanning bus 2 for devices... 1 USB Device(s) found
> Hit any key to stop autoboot:  0
> => setenv ipaddr 192.168.1.7; setenv serverip 192.168.1.5; tftpboot bsd.rd.SUNXI.umg; bootm
> Speed: 100, full duplex
> Using ethernet@01c50000 device
> TFTP from server 192.168.1.5; our IP address is 192.168.1.7
> Filename 'bsd.rd.SUNXI.umg'.
> Load address: 0x42000000
> Loading: #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          ############################
>          3.2 MiB/s
> done
> Bytes transferred = 8032508 (7a90fc hex)
> ## Booting kernel from Legacy Image at 42000000 ...
>    Image Name:   boot
>    Image Type:   ARM Linux Kernel Image (uncompressed)
>    Data Size:    8032444 Bytes = 7.7 MiB
>    Load Address: 40300000
>    Entry Point:  40300000
>    Verifying Checksum ... OK
>    Loading Kernel Image ... OK
>
> Starting kernel ...
>
>
> OpenBSD/sunxi booting ...
> arg0 0x0 arg1 0x10bb arg2 0x40000100
> atag core flags 0 pagesize 0 rootdev 0
> atag serial 0x16516616:0b01944c
> atag mem start 0x40000000 size 0x40000000
> bootfile:
> bootargs:
> memory size derived from u-boot
> bootconf.mem[0].address = 40000000 pages 262144/0x40000000
> Allocating page tables
> freestart = 0x40aaa000, free_pages = 259414 (0x0003f556)
> IRQ stack: p0x40ad8000 v0xc0ad8000
> ABT stack: p0x40ad9000 v0xc0ad9000
> UND stack: p0x40ada000 v0xc0ada000
> SVC stack: p0x40adb000 v0xc0adb000
> Creating L1 page table at 0x40aac000
> Mapping kernel
> Constructing L2 page tables
> undefined page pmap board type: 4283
> Copyright (c) 1982, 1986, 1989, 1991, 1993
>         The Regents of the University of California.  All rights reserved.
> Copyright (c) 1995-2016 OpenBSD. All rights reserved.  http://www.OpenBSD.org
>
> OpenBSD 5.9 (RAMDISK) #25: Sun Jan 31 23:07:09 BRST 2016
>     [hidden email]:/usr/src/sys/arch/armv7/compile/RAMDISK
> real mem  = 1073741824 (1024MB)
> avail mem = 1041670144 (993MB)
> mainbus0 at root
> cortex0 at mainbus0
> ampintc0 at cortex0 nirq 160
> agtimer0 at cortex0: tick rate 24000 KHz
> cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> sunxi0 at mainbus0: Allwinner A20
> sxipio0 at sunxi0
> sxiccmu0 at sunxi0
> sxidog0 at sunxi0
> sxirtc0 at sunxi0
> sxiuart0 at sunxi0: console
> sxiuart1 at sunxi0
> sxiuart2 at sunxi0
> sxiuart3 at sunxi0
> sxiuart4 at sunxi0
> sxiuart5 at sunxi0
> sxiuart6 at sunxi0
> sxiuart7 at sunxi0
> sxie0 at sunxi0, address 02:16:0b:01:94:4c
> rlphy0 at sxie0 phy 1: RTL8201L 10/100 PHY, rev. 1
> ahci0 at sunxi0 AHCI 1.1
> scsibus0 at ahci0: 32 targets
> ehci0 at sunxi0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
> ehci1 at sunxi0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1
> gpio0 at sxipio0: 18 pins
> gpio1 at sxipio0: 24 pins
> gpio2 at sxipio0: 25 pins
> gpio3 at sxipio0: 28 pins
> gpio4 at sxipio0: 12 pins
> gpio5 at sxipio0: 6 pins
> gpio6 at sxipio0: 12 pins
> gpio7 at sxipio0: 28 pins
> gpio8 at sxipio0: 22 pins
> boot device: lookup '' failed.
> root on rd0a swap on rd0b dump on rd0b
> WARNING: clock lost 16832 days
> WARNING: CHECK AND RESET THE DATE!
> erase ^?, werase ^W, kill ^U, intr ^C, status ^T
>
> Welcome to the OpenBSD/armv7 5.9 installation program.
> (I)nstall, (U)pgrade, (A)utoinstall or (S)hell?
>
> --
> db
>

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Re: sunxi: don't use sxitimer on the sun7i/A20

Artturi Alm
In reply to this post by Jonathan Gray-11
On Tue, Feb 02, 2016 at 10:55:57AM +1100, Jonathan Gray wrote:
>
> Thanks, both diffs committed.  Any chance you could create another to
> move the sxitimer_* globals into the softc?

I left out moving of sxitimer_iot and sxitimer_ioh on purpose, as
it would make reviewing this alot worse.
Now if this does get in somewhat as is, i wouldn't have much problems
producing diff to fix/unify armv7 timers allowing to remove some duplicate
code etc. with main reason being that afterwards all of them would be usable
with "-D_STANDALONE", being one of the ingredients to arch/armv7/stand :)
incase it does happen to be on your roadmap.

See the diff simplifying code and correcting comments in sxitimer below.

-Artturi


diff --git a/sys/arch/armv7/sunxi/sun4i.c b/sys/arch/armv7/sunxi/sun4i.c
index 6c3197a..1269b8c 100644
--- a/sys/arch/armv7/sunxi/sun4i.c
+++ b/sys/arch/armv7/sunxi/sun4i.c
@@ -44,17 +44,10 @@ struct armv7_dev sxia1x_devs[] = {
   .mem = { { INTC_ADDR, INTC_SIZE } },
  },
 
- /* Timers/Counters, resources mapped on first unit */
+ /* Timer/Counter */
  { .name = "sxitimer",
   .unit = 0,
-  .mem = { { TIMER_ADDR, TIMERx_SIZE },
- { CPUCNTRS_ADDR, CPUCNTRS_ADDR } }
- },
- { .name = "sxitimer",
-  .unit = 1,
- },
- { .name = "sxitimer",
-  .unit = 2,
+  .mem = { { TIMER_ADDR, TIMERx_SIZE } }
  },
 
  /* Watchdog Timer */
diff --git a/sys/arch/armv7/sunxi/sunxi.c b/sys/arch/armv7/sunxi/sunxi.c
index dac0348..a8efab96 100644
--- a/sys/arch/armv7/sunxi/sunxi.c
+++ b/sys/arch/armv7/sunxi/sunxi.c
@@ -41,8 +41,6 @@ struct board_dev sun4i_devs[] = {
  { "sxiccmu", 0 },
  { "a1xintc", 0 },
  { "sxitimer", 0 },
- { "sxitimer", 1 },
- { "sxitimer", 2 },
  { "sxidog", 0 },
  { "sxirtc", 0 },
  { "sxiuart", 0 },
diff --git a/sys/arch/armv7/sunxi/sunxireg.h b/sys/arch/armv7/sunxi/sunxireg.h
index 8153efa..9151669 100644
--- a/sys/arch/armv7/sunxi/sunxireg.h
+++ b/sys/arch/armv7/sunxi/sunxireg.h
@@ -60,10 +60,7 @@
 
 #define TIMER_ADDR 0x01c20c00
 #define TIMERx_SIZE 0x200
-#define TIMER0_IRQ 22
-#define TIMER1_IRQ 23
-#define TIMER2_IRQ 24
-#define STATTIMER_IRQ TIMER1_IRQ /* XXX */
+#define TIMER_IRQNUM(x) (22 + (x))
 
 #define WDOG_ADDR 0x01c20c90
 #define WDOG_SIZE 0x08
diff --git a/sys/arch/armv7/sunxi/sxitimer.c b/sys/arch/armv7/sunxi/sxitimer.c
index 4062b87..a5d5dd0 100644
--- a/sys/arch/armv7/sunxi/sxitimer.c
+++ b/sys/arch/armv7/sunxi/sxitimer.c
@@ -34,7 +34,6 @@
 
 #include <armv7/armv7/armv7var.h>
 #include <armv7/sunxi/sunxireg.h>
-/* #include <armv7/sunxi/sxipiovar.h> */
 
 #define TIMER_IER 0x00
 #define TIMER_ISR 0x04
@@ -75,6 +74,13 @@
 #define TICKTIMER 0
 #define STATTIMER 1
 #define CNTRTIMER 2
+#define TICKFREQ TIMER0_FREQUENCY
+#define STATFREQ TIMER1_FREQUENCY
+#define CNTRFREQ TIMER2_FREQUENCY
+/* timers are down-counters, from interval to 0 */
+#define MAX_IVAL 0xffffffff /* max interval */
+
+#define TIMER_MIN_CYCLES 0x20 /* 'feel good' value */
 
 void sxitimer_attach(struct device *, struct device *, void *);
 int sxitimer_tickintr(void *);
@@ -94,27 +100,13 @@ static struct timecounter sxitimer_timecounter = {
 bus_space_tag_t sxitimer_iot;
 bus_space_handle_t sxitimer_ioh;
 
-uint32_t sxitimer_freq[] = {
- TIMER0_FREQUENCY,
- TIMER1_FREQUENCY,
- TIMER2_FREQUENCY,
- 0
-};
-
-uint32_t sxitimer_irq[] = {
- TIMER0_IRQ,
- TIMER1_IRQ,
- TIMER2_IRQ,
- 0
-};
-
-uint32_t sxitimer_stat_tpi, sxitimer_tick_tpi;
-uint32_t sxitimer_statvar, sxitimer_statmin;
-uint32_t sxitimer_tick_nextevt, sxitimer_stat_nextevt;
-uint32_t sxitimer_ticks_err_cnt, sxitimer_ticks_err_sum;
-
 struct sxitimer_softc {
  struct device sc_dev;
+ uint32_t statvar, statmin;
+ uint32_t stat_tpi, stat_nextevt;
+ uint32_t tick_tpi, tick_nextevt;
+ uint32_t ticks_err_cnt, ticks_err_sum;
+
 };
 
 struct cfattach sxitimer_ca = {
@@ -128,12 +120,11 @@ struct cfdriver sxitimer_cd = {
 void
 sxitimer_attach(struct device *parent, struct device *self, void *args)
 {
+ struct sxitimer_softc *sc = (struct sxitimer_softc *)self;
  struct armv7_attach_args *aa = args;
- uint32_t freq, ival, now, cr;
- int unit = self->dv_unit;
-
- if (unit != 0)
- goto skip_init;
+
+ if (self->dv_unit != 0)
+ panic("sxitimer_attach: unit = %d", self->dv_unit);
 
  sxitimer_iot = aa->aa_iot;
 
@@ -143,83 +134,66 @@ sxitimer_attach(struct device *parent, struct device *self, void *args)
 
  /* clear counter, loop until ready */
  bus_space_write_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL,
-    CNT64_CLR_EN); /* XXX as a side-effect counter clk src=OSC24M */
+    CNT64_CLR_EN); /* as a side-effect counter clk src=OSC24M */
  while (bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_CTRL)
     & CNT64_CLR_EN)
  continue;
 
  /* setup timers */
- cr = bus_space_read_4(sxitimer_iot, sxitimer_ioh, LOSC_CTRL);
- cr |= OSC32K_SRC_SEL; /* ext 32.768KHz OSC src */
- bus_space_write_4(sxitimer_iot, sxitimer_ioh, LOSC_CTRL, cr);
-
-skip_init:
- /* timers are down-counters, from interval to 0 */
- now = 0xffffffff; /* known big value */
- freq = sxitimer_freq[unit];
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, LOSC_CTRL,
+    bus_space_read_4(sxitimer_iot, sxitimer_ioh, LOSC_CTRL) |
+    OSC32K_SRC_SEL); /* ext 32.768KHz OSC src */
 
  /* stop timer, and set clk src */
- bus_space_write_4(sxitimer_iot, sxitimer_ioh,
-    TIMER_CTRL(unit),
-    freq == 24000000 ? TIMER_OSC24M : TIMER_LSOSC);
-
- switch (unit) { /* XXX more XXXXTIMER magic for less lines? */
- case TICKTIMER:
- ival = sxitimer_tick_tpi = freq / hz;
- sxitimer_tick_nextevt = now - ival;
-
- sxitimer_ticks_err_cnt = freq % hz;
- sxitimer_ticks_err_sum = 0;
-
- printf(": ticktimer %dhz @ %dKHz", hz, freq / 1000);
- break;
- case STATTIMER:
- /* 100/1000 or 128/1024 ? */
- stathz = 128;
- profhz = 1024;
- sxitimer_setstatclockrate(stathz);
-
- ival = sxitimer_stat_tpi = freq / stathz;
- sxitimer_stat_nextevt = now - ival;
-
- printf(": stattimer %dhz @ %dKHz", stathz, freq / 1000);
- break;
- case CNTRTIMER:
- ival = now;
-
- sxitimer_timecounter.tc_frequency = freq;
- tc_init(&sxitimer_timecounter);
- arm_clock_register(sxitimer_cpu_initclocks, sxitimer_delay,
-    sxitimer_setstatclockrate, NULL);
-
- printf(": cntrtimer @ %dKHz", freq / 1000);
- break;
- default:
- panic("sxitimer_attach: unit = %d", unit);
- break;
- }
-
- bus_space_write_4(sxitimer_iot, sxitimer_ioh,
-    TIMER_INTV(unit), ival);
-
- printf("\n");
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, TIMER_CTRL(TICKTIMER),
+    TICKFREQ == 24000000 ? TIMER_OSC24M : TIMER_LSOSC);
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, TIMER_CTRL(STATTIMER),
+    STATFREQ == 24000000 ? TIMER_OSC24M : TIMER_LSOSC);
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, TIMER_CTRL(CNTRTIMER),
+    CNTRFREQ == 24000000 ? TIMER_OSC24M : TIMER_LSOSC);
+
+ /* prepare tick */
+ sc->tick_tpi = TICKFREQ / hz;
+ sc->tick_nextevt = MAX_IVAL - sc->tick_tpi;
+
+ sc->ticks_err_cnt = TICKFREQ % hz;
+ sc->ticks_err_sum = 0;
+
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, TIMER_INTV(TICKTIMER),
+    sc->tick_tpi);
+ printf(": tick %dhz @ %dKHz", hz, TICKFREQ / 1000);
+
+ /* prepare stat */
+ stathz = 128; /* 100/1000 or 128/1024 ? */
+ profhz = 1024;
+ sxitimer_setstatclockrate(stathz);
+
+ sc->stat_tpi = STATFREQ / stathz;
+ sc->stat_nextevt = MAX_IVAL - sc->stat_tpi;
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, TIMER_INTV(STATTIMER),
+    sc->stat_tpi);
+ printf(" stat %dhz @ %dKHz", stathz, STATFREQ / 1000);
+
+ /* prepare counter */
+ sxitimer_timecounter.tc_frequency = CNTRFREQ;
+ tc_init(&sxitimer_timecounter);
+ arm_clock_register(sxitimer_cpu_initclocks, sxitimer_delay,
+    sxitimer_setstatclockrate, NULL);
+
+ bus_space_write_4(sxitimer_iot, sxitimer_ioh, TIMER_INTV(CNTRTIMER),
+    MAX_IVAL);
+ printf(" counter @ %dKHz\n", CNTRFREQ / 1000);
 }
 
-/*
- * would be interesting to play with trigger mode while having one timer
- * in 32KHz mode, and the other timer running in sysclk mode and use
- * the high resolution speeds (matters more for delay than tick timer)
- */
-
 void
 sxitimer_cpu_initclocks(void)
 {
  uint32_t isr, ier;
 
  /* establish interrupts */
- arm_intr_establish(sxitimer_irq[TICKTIMER], IPL_CLOCK,
+ arm_intr_establish(TIMER_IRQNUM(TICKTIMER), IPL_CLOCK,
     sxitimer_tickintr, NULL, "tick");
- arm_intr_establish(sxitimer_irq[STATTIMER], IPL_STATCLOCK,
+ arm_intr_establish(TIMER_IRQNUM(STATTIMER), IPL_STATCLOCK,
     sxitimer_statintr, NULL, "stattick");
 
  /* clear timer interrupt pending bits */
@@ -247,25 +221,22 @@ sxitimer_cpu_initclocks(void)
 }
 
 /*
- * See comment in arm/xscale/i80321_clock.c
- *
- * Counter is count up, but with autoreload timers it is not possible
+ * Counter is count down, and with autoreload timers it is not possible
  * to detect how many interrupts passed while interrupts were blocked.
  * Also it is not possible to atomically add to the register.
  *
- * To work around this two timers are used, one is used as a reference
- * clock without reload, however we just disable the interrupt it
- * could generate.
+ * To work around this one of the timers is dedicated to be used as
+ * a restarting continuous reference clock without interrupt.
  *
- * Internally this keeps track of when the next timer should fire
+ * Internally this keeps track of when the timer should fire next,
  * and based on that time and the current value of the reference
- * clock a number is written into the timer count register to schedule
+ * clock a number is written into the timer interval register to schedule
  * the next event.
  */
-/* XXX update above comment */
 int
 sxitimer_tickintr(void *frame)
 {
+ struct sxitimer_softc *sc = sxitimer_cd.cd_devs[0];
  uint32_t now, nextevent;
  int rc = 0;
 
@@ -277,31 +248,31 @@ sxitimer_tickintr(void *frame)
 
  now = sxitimer_readcnt32();
 
- while ((int32_t)(now - sxitimer_tick_nextevt) < 0) {
- sxitimer_tick_nextevt -= sxitimer_tick_tpi;
- sxitimer_ticks_err_sum += sxitimer_ticks_err_cnt;
+ while ((int32_t)(now - sc->tick_nextevt) < 0) {
+ sc->tick_nextevt -= sc->tick_tpi;
+ sc->ticks_err_sum += sc->ticks_err_cnt;
 
- while (sxitimer_ticks_err_sum  > hz) {
- sxitimer_tick_nextevt += 1;
- sxitimer_ticks_err_sum -= hz;
+ while (sc->ticks_err_sum  > hz) {
+ sc->tick_nextevt += 1;
+ sc->ticks_err_sum -= hz;
  }
 
  rc = 1;
  hardclock(frame);
  }
- nextevent = now - sxitimer_tick_nextevt;
- if (nextevent < 10 /* XXX */)
- nextevent = 10;
+ nextevent = now - sc->tick_nextevt;
+ if (nextevent < TIMER_MIN_CYCLES)
+ nextevent = TIMER_MIN_CYCLES;
 
- if (nextevent > sxitimer_tick_tpi) {
+ if (nextevent > sc->tick_tpi) {
  /*
  * If interrupts are blocked too long, like during
  * the root prompt or ddb, the timer can roll over,
  * this will allow the system to continue to run
  * even if time is lost.
  */
- nextevent = sxitimer_tick_tpi;
- sxitimer_tick_nextevt = now;
+ nextevent = sc->tick_tpi;
+ sc->tick_nextevt = now;
  }
 
  bus_space_write_4(sxitimer_iot, sxitimer_ioh,
@@ -317,6 +288,7 @@ sxitimer_tickintr(void *frame)
 int
 sxitimer_statintr(void *frame)
 {
+ struct sxitimer_softc *sc = sxitimer_cd.cd_devs[0];
  uint32_t now, nextevent, r;
  int rc = 0;
 
@@ -327,29 +299,23 @@ sxitimer_statintr(void *frame)
     TIMER_ISR, TIMER_IRQ(STATTIMER));
 
  now = sxitimer_readcnt32();
- while ((int32_t)(now - sxitimer_stat_nextevt) < 0) {
+ while ((int32_t)(now - sc->stat_nextevt) < 0) {
  do {
- r = random() & (sxitimer_statvar -1);
+ r = random() & (sc->statvar - 1);
  } while (r == 0); /* random == 0 not allowed */
- sxitimer_stat_nextevt -= sxitimer_statmin + r;
+ sc->stat_nextevt -= sc->statmin + r;
  rc = 1;
  statclock(frame);
  }
 
- nextevent = now - sxitimer_stat_nextevt;
+ nextevent = now - sc->stat_nextevt;
 
- if (nextevent < 10 /* XXX */)
- nextevent = 10;
+ if (nextevent < TIMER_MIN_CYCLES)
+ nextevent = TIMER_MIN_CYCLES;
 
- if (nextevent > sxitimer_stat_tpi) {
- /*
- * If interrupts are blocked too long, like during
- * the root prompt or ddb, the timer can roll over,
- * this will allow the system to continue to run
- * even if time is lost.
- */
- nextevent = sxitimer_stat_tpi;
- sxitimer_stat_nextevt = now;
+ if (nextevent > sc->stat_tpi) {
+ nextevent = sc->stat_tpi;
+ sc->stat_nextevt = now;
  }
 
  bus_space_write_4(sxitimer_iot, sxitimer_ioh,
@@ -373,11 +339,6 @@ sxitimer_readcnt64(void)
     & CNT64_RL_EN)
  continue;
 
- /*
- * A10 usermanual doesn't mention anything about order, but fwiw
- * iirc. A20 manual mentions that low should be read first.
- */
- /* XXX check above */
  low = bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_LOW);
  high = bus_space_read_4(sxitimer_iot, sxitimer_ioh, CNT64_HIGH);
  return (uint64_t)high << 32 | low;
@@ -405,25 +366,21 @@ sxitimer_delay(u_int usecs)
 void
 sxitimer_setstatclockrate(int newhz)
 {
+ struct sxitimer_softc *sc = sxitimer_cd.cd_devs[0];
  int minint, statint, s;
 
  s = splstatclock();
 
- statint = sxitimer_freq[STATTIMER] / newhz;
+ statint = STATFREQ / newhz;
  /* calculate largest 2^n which is smaller than just over half statint */
- sxitimer_statvar = 0x40000000; /* really big power of two */
+ sc->statvar = 0x40000000; /* really big power of two */
  minint = statint / 2 + 100;
- while (sxitimer_statvar > minint)
- sxitimer_statvar >>= 1;
+ while (sc->statvar > minint)
+ sc->statvar >>= 1;
 
- sxitimer_statmin = statint - (sxitimer_statvar >> 1);
+ sc->statmin = statint - (sc->statvar >> 1);
 
  splx(s);
-
- /*
- * XXX this allows the next stat timer to occur then it switches
- * to the new frequency. Rather than switching instantly.
- */
 }
 
 u_int