(report) ethernet of Lichee Pi Zero(Allwinner V3s)

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(report) ethernet of Lichee Pi Zero(Allwinner V3s)

SASANO Takayoshi
Hello,

I am playing with Lichee Pi Zero, Allwinner V3s based board.

To use ehternet of this board, we have to enable network support of U-boot,
and tweak sun8i-v3s.dtsi and sun8i-v3s-licheepi-zero.dts.

To enable network support of U-boot, gmake menuconfig and mark
following items.

  Device Drivers
    -> [*] Network device support
      -> [*] Allwinner Sun8i Ethernet MAC support

There is no code that supports Allwinner V3s EMAC, but this EMAC has
compatibility with Allwinner H3. So device tree needs disguise like this:

--- u-boot-2019.01.orig/arch/arm/dts/sun8i-v3s.dtsi Tue Jan 15 07:02:36 2019
+++ u-boot-2019.01/arch/arm/dts/sun8i-v3s.dtsi Sat Mar  9 16:18:58 2019
@@ -94,10 +94,15 @@
  compatible = "simple-bus";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges;
 
+ syscon: syscon@01c00000 {
+ compatible = "allwinner,sun8i-v3s-syscon","syscon";
+ reg = <0x01c00000 0x34>;
+ };
+
  mmc0: mmc@01c0f000 {
  compatible = "allwinner,sun7i-a20-mmc";
  reg = <0x01c0f000 0x1000>;
  clocks = <&ccu CLK_BUS_MMC0>,
  <&ccu CLK_MMC0>,
@@ -266,10 +271,51 @@
  reg-shift = <2>;
  reg-io-width = <4>;
  clocks = <&ccu CLK_BUS_UART2>;
  resets = <&ccu RST_BUS_UART2>;
  status = "disabled";
+ };
+
+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio-mux {
+ compatible = "allwinner,sun8i-h3-mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio-parent-bus = <&mdio>;
+ /* Only one MDIO is usable at the time */
+ internal_mdio: mdio@1 {
+ compatible = "allwinner,sun8i-h3-mdio-internal";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+ };
  };
 
  gic: interrupt-controller@01c81000 {
  compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  reg = <0x01c81000 0x1000>,

--- u-boot-2019.01.orig/arch/arm/dts/sun8i-v3s-licheepi-zero.dts Tue Jan 15 07:02:36 2019
+++ u-boot-2019.01/arch/arm/dts/sun8i-v3s-licheepi-zero.dts Wed Mar  6 18:09:58 2019
@@ -47,10 +47,11 @@
 / {
  model = "Lichee Pi Zero";
  compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s";
 
  aliases {
+ ethernet0 = &emac;
  serial0 = &uart0;
  };
 
  chosen {
  stdout-path = "serial0:115200n8";
@@ -77,7 +78,14 @@
  status = "okay";
 };
 
 &usbphy {
  usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
  status = "okay";
 };


Current sys/dev/fdt/if_dwxe.c does not handle reset and clock of
integrated PHY, so we have to use U-boot to initialize them.
(This is same as Allwinner H3.)

Thanks to reading long message. Regards,
--
SASANO Takayoshi (JG1UAA) <[hidden email]>