looking for help on gpio setup on orange pi one

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looking for help on gpio setup on orange pi one

Stephen Graf
From the advice from Mark and the further reading that I did, I think I am
doing the right things.

 

I can set the status light from u-boot, but cannot configure the pin in
OpenBSD.

 

The attached console log shows the results of my testing with annotations in
caps.


gpio test log.txt (10K) Download Attachment
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Re: looking for help on gpio setup on orange pi one

Artturi Alm
On Wed, Aug 23, 2017 at 10:05:18AM -0700, Stephen Graf wrote:

> From the advice from Mark and the further reading that I did, I think I am
> doing the right things.
>
>  
>
> I can set the status light from u-boot, but cannot configure the pin in
> OpenBSD.
>
>  
>
> The attached console log shows the results of my testing with annotations in
> caps.
>

Hi,

if you can, i'd like to see the output in dmesg w/diff below,
might provide more clues.

-Artturi


diff --git a/sys/dev/fdt/sxipio.c b/sys/dev/fdt/sxipio.c
index 643226ecd19..40a742171a9 100644
--- a/sys/dev/fdt/sxipio.c
+++ b/sys/dev/fdt/sxipio.c
@@ -447,6 +447,7 @@ sxipio_attach_gpio(struct device *parent)
  int port, pin;
  int cfg, state;
  int i;
+ int m;
 
  for (i = 0; i < sc->sc_npins; i++) {
  /* Skip pins that have no gpio function. */
@@ -461,6 +462,15 @@ sxipio_attach_gpio(struct device *parent)
  reg = SXIREAD4(sc, SXIPIO_CFG(port, pin));
  cfg = (reg >> (pin & 0x7)) & 0x7;
 
+ for (m = 0; m < 8; m++)
+ if (sc->sc_pins[i].funcs[m].mux == cfg)
+ break;
+
+ printf("%c%d mux %d<%s>%s", 'A' + (u_int)sc->sc_pins[i].port,
+    sc->sc_pins[i].pin, cfg,
+    m >= 8 ? "invalid" : sc->sc_pins[i].funcs[m].name,
+    cfg < 2 ? "- adding\n" : "- skipping\n");
+
  /* Skip pins that have been assigned other functions. */
  if (cfg != SXIPIO_GPIO_IN && cfg != SXIPIO_GPIO_OUT)
  continue;

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Re: looking for help on gpio setup on orange pi one

Artturi Alm
On Thu, Aug 24, 2017 at 12:13:25AM +0300, Artturi Alm wrote:

> On Wed, Aug 23, 2017 at 10:05:18AM -0700, Stephen Graf wrote:
> > From the advice from Mark and the further reading that I did, I think I am
> > doing the right things.
> >
> >  
> >
> > I can set the status light from u-boot, but cannot configure the pin in
> > OpenBSD.
> >
> >  
> >
> > The attached console log shows the results of my testing with annotations in
> > caps.
> >
>
> Hi,
>
> if you can, i'd like to see the output in dmesg w/diff below,
> might provide more clues.
>

Actually, forget about that, as i guess you can 'fix' this by adding
what is necessary to the .dts of your board, or try from u-boot w/
 => fdt ... commands. You'll want to look out for allwinner pinctrl,
gpio dt-bindings, other sunxi dts files for examples etc..
if all you need is a simple output, faking it as a led for u-boot might
be the easiest.

gl hf:)
-Artturi

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Re: looking for help on gpio setup on orange pi one

Stephen Graf
In reply to this post by Artturi Alm
Thank you for your responses and suggestions.

I compared the dtbs of openbsd and a linux (armbian mainline) distribution
that runs on my orangepi one. The armbian dtb has more stuff in it but
mostly the items in the openbsd dtb match the armbian one.  Both have the
same item for PA15 in pinctrl@01c20800:

                        led_pins@0 {
                                pins = "PA15";
                                function = "gpio_out";
                                linux,phandle = <0x2b>;
                                phandle = <0x2b>;
                        };
Neither dtb has any reference to PC4 or PD14, which are brought out to the
header.

I also compared with the bananapi dtb and the pinctl is very similar with a
similar definition for a status led.

                        led_pins@0 {
                                pins = "PH24";
                                function = "gpio_out";
                                linux,phandle = <0x52>;
                                phandle = <0x52>;
                        };

Bananapi is an A20 device whereas orangepi is H3.

Does openbsd need some definition in the dtb to set up a gpio pin?  Could I
add something like:

                        led_pins@0 {
                                pins = "PC4";
                                function = "gpio_out";
                                linux,phandle = <0x2b>;
                                phandle = <0x2b>;
                        };

What are the phandle lines for?
Does the "led_pins@0" need to change?

What about something like this:

                        hdr_pin_16@0 {
                                pins = "PC4";
                                function = "gpio_out";
                        };

                        hdr_pin_12@0 {
                                pins = "PD14";
                                function = "gpio_out";
                        };

I reloaded the system with the 6.2 snapshot and added the above definition
for PD14 to the dtb
and added a set for PD14 to rc.securelevel.  I am still getting the same
error:

gpioctl: GPIOPINSET: Operation not supported by device

The gpio test log 61.txt has is annotated.

-----Original Message-----
From: [hidden email] [mailto:[hidden email]] On Behalf Of
Artturi Alm
Sent: Wednesday, August 23, 2017 2:51 PM
To: Stephen Graf <[hidden email]>
Cc: [hidden email]
Subject: Re: looking for help on gpio setup on orange pi one

On Thu, Aug 24, 2017 at 12:13:25AM +0300, Artturi Alm wrote:

> On Wed, Aug 23, 2017 at 10:05:18AM -0700, Stephen Graf wrote:
> > From the advice from Mark and the further reading that I did, I
> > think I am doing the right things.
> >
> >  
> >
> > I can set the status light from u-boot, but cannot configure the pin
> > in OpenBSD.
> >
> >  
> >
> > The attached console log shows the results of my testing with
> > annotations in caps.
> >
>
> Hi,
>
> if you can, i'd like to see the output in dmesg w/diff below, might
> provide more clues.
>
Actually, forget about that, as i guess you can 'fix' this by adding what is
necessary to the .dts of your board, or try from u-boot w/  => fdt ...
commands. You'll want to look out for allwinner pinctrl, gpio dt-bindings,
other sunxi dts files for examples etc..
if all you need is a simple output, faking it as a led for u-boot might be
the easiest.

gl hf:)
-Artturi


armbian.dts (37K) Download Attachment
openbsd.dts (21K) Download Attachment
bananapi.dts (52K) Download Attachment
dmesg.txt (2K) Download Attachment
openbsd_mod_test.dts (21K) Download Attachment
boot console log 62.txt (5K) Download Attachment
gpio test log 61.txt (10K) Download Attachment
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Re: looking for help on gpio setup on orange pi one

Artturi Alm
On Thu, Aug 24, 2017 at 10:26:05PM -0700, Stephen Graf wrote:

> Thank you for your responses and suggestions.
>
> I compared the dtbs of openbsd and a linux (armbian mainline) distribution
> that runs on my orangepi one. The armbian dtb has more stuff in it but
> mostly the items in the openbsd dtb match the armbian one.  Both have the
> same item for PA15 in pinctrl@01c20800:
>
> led_pins@0 {
> pins = "PA15";
> function = "gpio_out";
> linux,phandle = <0x2b>;
> phandle = <0x2b>;
> };
> Neither dtb has any reference to PC4 or PD14, which are brought out to the
> header.
>
> I also compared with the bananapi dtb and the pinctl is very similar with a
> similar definition for a status led.
>
> led_pins@0 {
> pins = "PH24";
> function = "gpio_out";
> linux,phandle = <0x52>;
> phandle = <0x52>;
> };
>
> Bananapi is an A20 device whereas orangepi is H3.
>
> Does openbsd need some definition in the dtb to set up a gpio pin?  Could I
> add something like:
>
> led_pins@0 {
> pins = "PC4";
> function = "gpio_out";
> linux,phandle = <0x2b>;
> phandle = <0x2b>;
> };
>
> What are the phandle lines for?
> Does the "led_pins@0" need to change?
>
> What about something like this:
>
> hdr_pin_16@0 {
> pins = "PC4";
> function = "gpio_out";
> };
>
> hdr_pin_12@0 {
> pins = "PD14";
> function = "gpio_out";
> };
>
> I reloaded the system with the 6.2 snapshot and added the above definition
> for PD14 to the dtb
> and added a set for PD14 to rc.securelevel.  I am still getting the same
> error:
>
> gpioctl: GPIOPINSET: Operation not supported by device
>
> The gpio test log 61.txt has is annotated.
>

Hi,

i just tested the diff that does print pinmuxes during boot, and unfortunately
it does seem as if something somewhere does reset the mux of leds from output
back to input in between toggling the led in u-boot & printing the mux in
sxipio_attach_gpio()..

 => gpio set ph20
gpio: pin ph20 (gpio 244) value is 1
=> gpio set ph21
gpio: pin ph21 (gpio 245) value is 1
=> run bootcmd
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found EFI removable media binary efi/boot/bootarm.efi
reading efi/boot/bootarm.efi
...

...
H21 mux 0<gpio_in>- adding
H22 mux 0<gpio_in>- adding
...

now those got added so that i can seemingly toggle w/o errors, once set back
to output, ymmv. different SoC and all..

Hit any key to stop autoboot:  0
=> gpio toggle ph21
gpio: pin ph21 (gpio 245) value is 1
=> run bootcmd
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found EFI removable media binary efi/boot/bootarm.efi
reading efi/boot/bootarm.efi
64908 bytes read in 39 ms (1.6 MiB/s)
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
## Starting EFI application at 42000000 ...
Scanning disks on scsi...
Scanning disks on usb...
Scanning disks on mmc...
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Found 6 disks

Error: ethernet@01c50000 address not set.
>> OpenBSD/armv7 BOOTARM 0.8
boot> set howto -s
boot>
booting sd0a:/bsd: 3897060+166632+496400 [281226+90+516352+242933]=0x55809c

OpenBSD/armv7 booting ...
arg0 0xc085809c arg1 0x0 arg2 0x48000000
Allocating page tables
freestart = 0x40859000, free_pages = 260007 (0x0003f7a7)
IRQ stack: p0x40887000 v0xc0887000
ABT stack: p0x40888000 v0xc0888000
UND stack: p0x40889000 v0xc0889000
SVC stack: p0x4088a000 v0xc088a000
Creating L1 page table at 0x4085c000
Mapping kernel
Constructing L2 page tables
undefined page pmap [ using 1041060 bytes of bsd ELF symbol table ]
board type: 0
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2017 OpenBSD. All rights reserved.  https://www.OpenBSD.org

OpenBSD 6.2-beta (GENERIC) #13: Fri Aug 25 23:47:49 EEST 2017
    [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
real mem  = 1073741824 (1024MB)
avail mem = 1043980288 (995MB)
mainbus0 at root: Cubietech Cubieboard2
cpu0 at mainbus0: ARM Cortex-A7 r0p4 (ARMv7)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
cortex0 at mainbus0
sxiccmu0 at mainbus0
psci0 at mainbus0
agtimer0 at mainbus0: tick rate 24000 KHz
simplebus0 at mainbus0: "soc"
sxipio0 at simplebus0: 175 pins
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
ehci0 at simplebus0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
sxiahci0 at simplebus0: AHCI 1.1
scsibus0 at sxiahci0: 32 targets
ehci1 at simplebus0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
sxidog0 at simplebus0
sxirtc0 at simplebus0
com0 at simplebus0: ns16550, no working fifo
com0: console
sxitwi0 at simplebus0
iic0 at sxitwi0
axppmic0 at iic0 addr 0x34: AXP209, ACIN
sxitwi1 at simplebus0
iic1 at sxitwi1
dwge0 at simplebus0
dwge0: address: fe:e1:ba:d0:20:5d
rlphy0 at dwge0 phy 1: RTL8201L 10/100 PHY, rev. 1
ampintc0 at simplebus0 nirq 160, ncpu 2
A0 mux 5<gmac>- skipping
A1 mux 2<emac>- skipping
A2 mux 5<gmac>- skipping
A3 mux 2<emac>- skipping
A4 mux 5<gmac>- skipping
A5 mux 2<emac>- skipping
A6 mux 5<gmac>- skipping
A7 mux 2<emac>- skipping
A8 mux 5<gmac>- skipping
A9 mux 2<emac>- skipping
A10 mux 5<gmac>- skipping
A11 mux 2<emac>- skipping
A12 mux 5<gmac>- skipping
A13 mux 2<emac>- skipping
A14 mux 5<gmac>- skipping
A15 mux 2<emac>- skipping
A16 mux 5<gmac>- skipping
A17 mux 2<emac>- skipping
B0 mux 2<i2c0>- skipping
B1 mux 1<gpio_out>- adding
B2 mux 0<gpio_in>- adding
B3 mux 4<spdif>- skipping
B4 mux 2<ir0>- skipping
B5 mux 1<gpio_out>- adding
B6 mux 0<gpio_in>- adding
B7 mux 0<gpio_in>- adding
B8 mux 1<gpio_out>- adding
B9 mux 0<gpio_in>- adding
B10 mux 0<gpio_in>- adding
B11 mux 0<gpio_in>- adding
B12 mux 0<gpio_in>- adding
B13 mux 0<gpio_in>- adding
B14 mux 0<gpio_in>- adding
B15 mux 0<gpio_in>- adding
B16 mux 0<gpio_in>- adding
B17 mux 0<gpio_in>- adding
B18 mux 0<gpio_in>- adding
B19 mux 0<gpio_in>- adding
B20 mux 0<gpio_in>- adding
B21 mux 0<gpio_in>- adding
B22 mux 0<gpio_in>- adding
B23 mux 4<invalid>- skipping
C0 mux 0<gpio_in>- adding
C1 mux 0<gpio_in>- adding
C2 mux 0<gpio_in>- adding
C3 mux 0<gpio_in>- adding
C4 mux 0<gpio_in>- adding
C5 mux 0<gpio_in>- adding
C6 mux 0<gpio_in>- adding
C7 mux 0<gpio_in>- adding
C8 mux 0<gpio_in>- adding
C9 mux 0<gpio_in>- adding
C10 mux 0<gpio_in>- adding
C11 mux 0<gpio_in>- adding
C12 mux 0<gpio_in>- adding
C13 mux 0<gpio_in>- adding
C14 mux 0<gpio_in>- adding
C15 mux 0<gpio_in>- adding
C16 mux 0<gpio_in>- adding
C17 mux 0<gpio_in>- adding
C18 mux 0<gpio_in>- adding
C19 mux 0<gpio_in>- adding
C20 mux 0<gpio_in>- adding
C21 mux 0<gpio_in>- adding
C22 mux 0<gpio_in>- adding
C23 mux 0<gpio_in>- adding
C24 mux 0<gpio_in>- adding
D0 mux 0<gpio_in>- adding
D1 mux 0<gpio_in>- adding
D2 mux 0<gpio_in>- adding
D3 mux 0<gpio_in>- adding
D4 mux 0<gpio_in>- adding
D5 mux 0<gpio_in>- adding
D6 mux 0<gpio_in>- adding
D7 mux 0<gpio_in>- adding
D8 mux 0<gpio_in>- adding
D9 mux 0<gpio_in>- adding
D10 mux 0<gpio_in>- adding
D11 mux 0<gpio_in>- adding
D12 mux 0<gpio_in>- adding
D13 mux 0<gpio_in>- adding
D14 mux 0<gpio_in>- adding
D15 mux 0<gpio_in>- adding
D16 mux 0<gpio_in>- adding
D17 mux 0<gpio_in>- adding
D18 mux 0<gpio_in>- adding
D19 mux 0<gpio_in>- adding
D20 mux 0<gpio_in>- adding
D21 mux 0<gpio_in>- adding
D22 mux 0<gpio_in>- adding
D23 mux 0<gpio_in>- adding
D24 mux 0<gpio_in>- adding
D25 mux 0<gpio_in>- adding
D26 mux 0<gpio_in>- adding
D27 mux 0<gpio_in>- adding
E0 mux 0<gpio_in>- adding
E1 mux 0<gpio_in>- adding
E2 mux 0<gpio_in>- adding
E3 mux 0<gpio_in>- adding
E4 mux 0<gpio_in>- adding
E5 mux 0<gpio_in>- adding
E6 mux 0<gpio_in>- adding
E7 mux 0<gpio_in>- adding
E8 mux 0<gpio_in>- adding
E9 mux 0<gpio_in>- adding
E10 mux 0<gpio_in>- adding
E11 mux 0<gpio_in>- adding
F0 mux 2<mmc0>- skipping
F1 mux 1<gpio_out>- adding
F2 mux 0<gpio_in>- adding
F3 mux 4<jtag>- skipping
F4 mux 2<mmc0>- skipping
F5 mux 1<gpio_out>- adding
G0 mux 0<gpio_in>- adding
G1 mux 0<gpio_in>- adding
G2 mux 0<gpio_in>- adding
G3 mux 0<gpio_in>- adding
G4 mux 0<gpio_in>- adding
G5 mux 0<gpio_in>- adding
G6 mux 0<gpio_in>- adding
G7 mux 0<gpio_in>- adding
G8 mux 0<gpio_in>- adding
G9 mux 0<gpio_in>- adding
G10 mux 0<gpio_in>- adding
G11 mux 0<gpio_in>- adding
H0 mux 0<gpio_in>- adding
H1 mux 0<gpio_in>- adding
H2 mux 0<gpio_in>- adding
H3 mux 0<gpio_in>- adding
H4 mux 0<gpio_in>- adding
H5 mux 0<gpio_in>- adding
H6 mux 0<gpio_in>- adding
H7 mux 0<gpio_in>- adding
H8 mux 0<gpio_in>- adding
H9 mux 0<gpio_in>- adding
H10 mux 0<gpio_in>- adding
H11 mux 0<gpio_in>- adding
H12 mux 0<gpio_in>- adding
H13 mux 0<gpio_in>- adding
H14 mux 0<gpio_in>- adding
H15 mux 0<gpio_in>- adding
H16 mux 0<gpio_in>- adding
H17 mux 0<gpio_in>- adding
H18 mux 0<gpio_in>- adding
H19 mux 0<gpio_in>- adding
H20 mux 0<gpio_in>- adding
H21 mux 0<gpio_in>- adding
H22 mux 0<gpio_in>- adding
H23 mux 0<gpio_in>- adding
H24 mux 0<gpio_in>- adding
H25 mux 0<gpio_in>- adding
H26 mux 0<gpio_in>- adding
H27 mux 0<gpio_in>- adding
I0 mux 0<gpio_in>- adding
I1 mux 0<gpio_in>- adding
I2 mux 0<gpio_in>- adding
I3 mux 0<gpio_in>- adding
I4 mux 0<gpio_in>- adding
I5 mux 0<gpio_in>- adding
I6 mux 0<gpio_in>- adding
I7 mux 0<gpio_in>- adding
I8 mux 0<gpio_in>- adding
I9 mux 0<gpio_in>- adding
I10 mux 0<gpio_in>- adding
I11 mux 0<gpio_in>- adding
I12 mux 0<gpio_in>- adding
I13 mux 0<gpio_in>- adding
I14 mux 0<gpio_in>- adding
I15 mux 0<gpio_in>- adding
I16 mux 0<gpio_in>- adding
I17 mux 0<gpio_in>- adding
I18 mux 0<gpio_in>- adding
I19 mux 0<gpio_in>- adding
I20 mux 0<gpio_in>- adding
I21 mux 0<gpio_in>- adding
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
gpio7 at sxipio0: 32 pins
gpio8 at sxipio0: 32 pins
scsibus1 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus1 targ 1 lun 0: <SD/MMC, USD, 0002> SCSI2 0/direct removable
sd0: 7517MB, 512 bytes/sector, 15394816 sectors
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
scsibus3 at softraid0: 256 targets
boot device: sd0
root on sd0a (82aa3db79c6ad6cb.a) swap on sd0b dump on sd0b
Enter pathname of shell or RETURN for sh:
# mount -a
NFS Portmap: RPC: Port mapper failure - RPC: Unable to send

^C
# mount
/dev/sd0a on / type ffs (local)
/dev/sd0e on /home type ffs (local, nodev, nosuid)
/dev/sd0d on /usr type ffs (local, nodev, wxallowed)
# gp
gpioctl   gprof
# gpioctl gpio7
/dev/gpio7: 32 pins
# gpioctl gpio7 20 set out green_led
pin 20: caps: in out, flags: in -> out
# gpioctl gpio7 green_led
pin green_led: state 0
# gpioctl gpio7 green_led toggle
pin green_led: state 0 -> 1
# exit
setting tty flags
pf enabled
starting network
DHCPDISCOVER on dwge0 - interval 1
DHCPDISCOVER on dwge0 - interval 1
DHCPOFFER from 192.168.2.2 (00:22:68:10:3d:f0)
DHCPREQUEST on dwge0 to 255.255.255.255
DHCPACK from 192.168.2.2 (00:22:68:10:3d:f0)
bound to 192.168.2.49 -- renewal in 21600 seconds.
reordering libraries:^C^C failed.
starting early daemons: syslogd pflogd(failed) ntpd.
starting RPC daemons:.
savecore: no core dump
checking quotas: done.
clearing /tmp
kern.securelevel: 0 -> 1
creating runtime link editor directory cache.
preserving editor files.
starting network daemons: sshd smtpd sndiod.
starting local daemons: cron.
Fri Aug 25 19:34:14 EEST 2017
/etc/rc: kernel relinking failed; see /usr/share/compile/GENERIC/relink.log

OpenBSD/armv7 (cubie2.my.domain) (console)

login: root
Password:
Last login: Fri Aug 25 19:22:25 on console
OpenBSD 6.2-beta (GENERIC) #13: Fri Aug 25 23:47:49 EEST 2017

Welcome to OpenBSD: The proactively secure Unix-like operating system.

Please use the sendbug(1) utility to report bugs in the system.
Before reporting a bug, please try to reproduce it with the latest
version of the code.  With bug reports, please try to ensure that
enough information to reproduce the problem is enclosed, and if a
known fix for it exists, include that as well.

You have mail.
root@cubie2:~ # gpioctl gpio7 green_led
pin green_led: state 1
root@cubie2:~ # gpioctl gpio7 green_led toggle
pin green_led: state 1 -> 0
root@cubie2:~ # gpioctl gpio7 green_led toggle
pin green_led: state 0 -> 1
root@cubie2:~ # it does work. :)

testing is easier in singleuser, so:
>> OpenBSD/armv7 BOOTARM 0.8
boot> set howto -s
boot>

-Artturi

> -----Original Message-----
> From: [hidden email] [mailto:[hidden email]] On Behalf Of
> Artturi Alm
> Sent: Wednesday, August 23, 2017 2:51 PM
> To: Stephen Graf <[hidden email]>
> Cc: [hidden email]
> Subject: Re: looking for help on gpio setup on orange pi one
>
> On Thu, Aug 24, 2017 at 12:13:25AM +0300, Artturi Alm wrote:
> > On Wed, Aug 23, 2017 at 10:05:18AM -0700, Stephen Graf wrote:
> > > From the advice from Mark and the further reading that I did, I
> > > think I am doing the right things.
> > >
> > >  
> > >
> > > I can set the status light from u-boot, but cannot configure the pin
> > > in OpenBSD.
> > >
> > >  
> > >
> > > The attached console log shows the results of my testing with
> > > annotations in caps.
> > >
> >
> > Hi,
> >
> > if you can, i'd like to see the output in dmesg w/diff below, might
> > provide more clues.
> >
>
> Actually, forget about that, as i guess you can 'fix' this by adding what is
> necessary to the .dts of your board, or try from u-boot w/  => fdt ...
> commands. You'll want to look out for allwinner pinctrl, gpio dt-bindings,
> other sunxi dts files for examples etc..
> if all you need is a simple output, faking it as a led for u-boot might be
> the easiest.
>
> gl hf:)
> -Artturi
>




> OpenBSD 6.2-beta (GENERIC) #43: Tue Aug 22 11:20:56 MDT 2017
>     [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
> real mem  = 536870912 (512MB)
> avail mem = 517414912 (493MB)
> mainbus0 at root: Xunlong Orange Pi One
> cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> cortex0 at mainbus0
> sxiccmu0 at mainbus0
> psci0 at mainbus0
> simplebus0 at mainbus0: "soc"
> sxiccmu1 at simplebus0
> sxipio0 at simplebus0: 94 pins
> sxipio1 at simplebus0: 12 pins
> sximmc0 at simplebus0
> sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
> ehci0 at simplebus0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
> ehci1 at simplebus0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
> sxidog0 at simplebus0
> com0 at simplebus0: ns16550, no working fifo
> com0: console
> ampintc0 at simplebus0 nirq 160, ncpu 4
> sxirtc0 at simplebus0
> gpio0 at sxipio0: 32 pins
> gpio1 at sxipio0: 32 pins
> gpio2 at sxipio0: 32 pins
> gpio3 at sxipio0: 32 pins
> gpio4 at sxipio0: 32 pins
> gpio5 at sxipio0: 32 pins
> gpio6 at sxipio0: 32 pins
> gpio7 at sxipio1: 32 pins
> agtimer0 at mainbus0: tick rate 24000 KHz
> scsibus0 at sdmmc0: 2 targets, initiator 0
> sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SL16G, 0080> SCSI2 0/direct removable
> sd0: 15193MB, 512 bytes/sector, 31116288 sectors
> umass0 at uhub1 port 1 configuration 1 interface 0 "Lexar JD Secure II +" rev 2.00/11.00 addr 2
> umass0: using SCSI over Bulk-Only
> scsibus1 at umass0: 2 targets, initiator 0
> sd1 at scsibus1 targ 1 lun 0: <Lexar, JD Secure II +, 1100> SCSI0 0/direct removable serial.05dca732012100015339
> sd1: 1912MB, 512 bytes/sector, 3915776 sectors
> vscsi0 at root
> scsibus2 at vscsi0: 256 targets
> softraid0 at root
> scsibus3 at softraid0: 256 targets
> boot device: sd0
> root on sd0a (37e89bdc6451a368.a) swap on sd0b dump on sd0b
> WARNING: preposterous clock chip time
> WARNING: CHECK AND RESET THE DATE!


> U-Boot SPL 2017.09-rc2 (Aug 22 2017 - 00:26:16)
> DRAM: 512 MiB
> Trying to boot from MMC1
>
>
> U-Boot 2017.09-rc2 (Aug 22 2017 - 00:26:16 -0600) Allwinner Technology
>
> CPU:   Allwinner H3 (SUN8I 1680)
> Model: Xunlong Orange Pi One
> DRAM:  512 MiB
> MMC:   SUNXI SD/MMC: 0
> *** Warning - bad CRC, using default environment
>
> In:    serial
> Out:   serial
> Err:   serial
> Net:   phy interface0
> eth0: ethernet@1c30000
> starting USB...
> USB0:   USB EHCI 1.00
> USB1:   USB OHCI 1.0
> scanning bus 0 for devices... 2 USB Device(s) found
>        scanning usb for storage devices... 1 Storage Device(s) found
> Hit any key to stop autoboot:  0
> switch to partitions #0, OK
> mmc0 is current device
> Scanning mmc 0:1...
> reading /sun8i-h3-orangepi-one.dtb
> 14504 bytes read in 28 ms (505.9 KiB/s)
> Found EFI removable media binary efi/boot/bootarm.efi
> reading efi/boot/bootarm.efi
> 67356 bytes read in 35 ms (1.8 MiB/s)
> ## Starting EFI application at 42000000 ...
> Scanning disks on usb...
> Scanning disks on mmc...
> MMC Device 1 not found
> MMC Device 2 not found
> MMC Device 3 not found
> Found 5 disks
> >> OpenBSD/armv7 BOOTARM 1.0
> boot>
> booting sd0a:/bsd: 3886716+164372+498568 [281602+90+516256+242888]=0x558128
>
> OpenBSD/armv7 booting ...
> arg0 0xc0858128 arg1 0x0 arg2 0x48000000
> Allocating page tables
> freestart = 0x40859000, free_pages = 128935 (0x0001f7a7)
> IRQ stack: p0x40887000 v0xc0887000
> ABT stack: p0x40888000 v0xc0888000
> UND stack: p0x40889000 v0xc0889000
> SVC stack: p0x4088a000 v0xc088a000
> Creating L1 page table at 0x4085c000
> Mapping kernel
> Constructing L2 page tables
> undefined page pmap [ using 1041292 bytes of bsd ELF symbol table ]
> board type: 0
> Copyright (c) 1982, 1986, 1989, 1991, 1993
>         The Regents of the University of California.  All rights reserved.
> Copyright (c) 1995-2017 OpenBSD. All rights reserved.  https://www.OpenBSD.org
>
> OpenBSD 6.2-beta (GENERIC) #43: Tue Aug 22 11:20:56 MDT 2017
>     [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
> real mem  = 536870912 (512MB)
> avail mem = 517414912 (493MB)
> mainbus0 at root: Xunlong Orange Pi One
> cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> cortex0 at mainbus0
> sxiccmu0 at mainbus0
> psci0 at mainbus0
> simplebus0 at mainbus0: "soc"
> sxiccmu1 at simplebus0
> sxipio0 at simplebus0: 94 pins
> sxipio1 at simplebus0: 12 pins
> sximmc0 at simplebus0
> sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
> ehci0 at simplebus0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
> ehci1 at simplebus0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
> sxidog0 at simplebus0
> com0 at simplebus0: ns16550, no working fifo
> com0: console
> ampintc0 at simplebus0 nirq 160, ncpu 4
> sxirtc0 at simplebus0
> gpio0 at sxipio0: 32 pins
> gpio1 at sxipio0: 32 pins
> gpio2 at sxipio0: 32 pins
> gpio3 at sxipio0: 32 pins
> gpio4 at sxipio0: 32 pins
> gpio5 at sxipio0: 32 pins
> gpio6 at sxipio0: 32 pins
> gpio7 at sxipio1: 32 pins
> agtimer0 at mainbus0: tick rate 24000 KHz
> scsibus0 at sdmmc0: 2 targets, initiator 0
> sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SL16G, 0080> SCSI2 0/direct removable
> sd0: 15193MB, 512 bytes/sector, 31116288 sectors
> umass0 at uhub1 port 1 configuration 1 interface 0 "Lexar JD Secure II +" rev 2.00/11.00 addr 2
> umass0: using SCSI over Bulk-Only
> scsibus1 at umass0: 2 targets, initiator 0
> sd1 at scsibus1 targ 1 lun 0: <Lexar, JD Secure II +, 1100> SCSI0 0/direct removable serial.05dca732012100015339
> sd1: 1912MB, 512 bytes/sector, 3915776 sectors
> vscsi0 at root
> scsibus2 at vscsi0: 256 targets
> softraid0 at root
> scsibus3 at softraid0: 256 targets
> boot device: sd0
> root on sd0a (37e89bdc6451a368.a) swap on sd0b dump on sd0b
> WARNING: preposterous clock chip time
> WARNING: CHECK AND RESET THE DATE!
> Automatic boot in progress: starting file system checks.
> /dev/sd0a (37e89bdc6451a368.a): file system is clean; not checking
> /dev/sd0l (37e89bdc6451a368.l): file system is clean; not checking
> /dev/sd0d (37e89bdc6451a368.d): file system is clean; not checking
> /dev/sd0f (37e89bdc6451a368.f): file system is clean; not checking
> /dev/sd0g (37e89bdc6451a368.g): file system is clean; not checking
> /dev/sd0h (37e89bdc6451a368.h): file system is clean; not checking
> /dev/sd0k (37e89bdc6451a368.k): file system is clean; not checking
> /dev/sd0j (37e89bdc6451a368.j): file system is clean; not checking
> /dev/sd0e (37e89bdc6451a368.e): file system is clean; not checking
> setting tty flags
> pf enabled
> starting network
> reordering libraries: done.
> starting early daemons: syslogd pflogd ntpd.
> starting RPC daemons:.
> savecore: no core dump
> checking quotas: done.
> clearing /tmp
> In rc.securelevel, setting gpio.
> PD14
> gpioctl: GPIOPINSET: Operation not supported by device
> kern.securelevel: 0 -> 1
> creating runtime link editor directory cache.
> preserving editor files.
> starting network daemons: sshd smtpd sndiod.
> starting local daemons: cron.
> Thu Aug 24 03:08:27 PDT 2017
>
> OpenBSD/armv7 (openbsdtestdtb.graf.lan) (console)
>
> login:

> U-Boot SPL 2017.07 (Aug 15 2017 - 07:39:48)
> DRAM: 512 MiB
> Trying to boot from MMC1
>
>
> U-Boot 2017.07 (Aug 15 2017 - 07:39:48 -0600) Allwinner Technology
>
> CPU:   Allwinner H3 (SUN8I 1680)
> Model: Xunlong Orange Pi One
> DRAM:  512 MiB
> MMC:   SUNXI SD/MMC: 0
> *** Warning - bad CRC, using default environment
>
> In:    serial
> Out:   serial
> Err:   serial
> Net:   phy interface0
> eth0: ethernet@1c30000
> starting USB...
> USB0:   USB EHCI 1.00
> USB1:   USB OHCI 1.0
> scanning bus 0 for devices... 1 USB Device(s) found
>        scanning usb for storage devices... 0 Storage Device(s) found
> Hit any key to stop autoboot:  0
>
>
> THE FOLLOWING WORKS AND TURNS ON AND OFF THE RED STATUS LIGHT ON THE BOARD
>
> => gpio set PA15
> gpio: pin PA15 (gpio 15) value is 1
> => gpio clear PA15
> gpio: pin PA15 (gpio 15) value is 0
> => gpio set PA15
> gpio: pin PA15 (gpio 15) value is 1
> => gpio status -a PA15
> Bank PA:
> PA15: output: 1 [ ]
>
>
>
> => boot
> switch to partitions #0, OK
> mmc0 is current device
> Scanning mmc 0:1...
> reading /sun8i-h3-orangepi-one.dtb
> 14436 bytes read in 25 ms (563.5 KiB/s)
> Found EFI removable media binary efi/boot/bootarm.efi
> reading efi/boot/bootarm.efi
> 65448 bytes read in 39 ms (1.6 MiB/s)
> ## Starting EFI application at 42000000 ...
> Scanning disks on usb...
> Scanning disks on mmc...
> MMC Device 1 not found
> MMC Device 2 not found
> MMC Device 3 not found
> Found 5 disks
> >> OpenBSD/armv7 BOOTARM 0.9
> boot>
> booting sd0a:/bsd: 3887120+167224+496676 [281343+90+515936+242597]=0x558184
>
> OpenBSD/armv7 booting ...
> arg0 0xc0858184 arg1 0x0 arg2 0x48000000
> Allocating page tables
> freestart = 0x40859000, free_pages = 128935 (0x0001f7a7)
> IRQ stack: p0x40887000 v0xc0887000
> ABT stack: p0x40888000 v0xc0888000
> UND stack: p0x40889000 v0xc0889000
> SVC stack: p0x4088a000 v0xc088a000
> Creating L1 page table at 0x4085c000
> Mapping kernel
> Constructing L2 page tables
> undefined page pmap [ using 1040424 bytes of bsd ELF symbol table ]
> board type: 0
> Copyright (c) 1982, 1986, 1989, 1991, 1993
>         The Regents of the University of California.  All rights reserved.
> Copyright (c) 1995-2017 OpenBSD. All rights reserved.  https://www.OpenBSD.org
>
> OpenBSD 6.1-current (GENERIC) #36: Wed Aug 16 00:34:41 MDT 2017
>     [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
> real mem  = 536870912 (512MB)
> avail mem = 517414912 (493MB)
> mainbus0 at root: Xunlong Orange Pi One
> cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> cortex0 at mainbus0
> sxiccmu0 at mainbus0
> psci0 at mainbus0
> simplebus0 at mainbus0: "soc"
> sxiccmu1 at simplebus0
> sxipio0 at simplebus0: 94 pins
> sxipio1 at simplebus0: 12 pins
> sximmc0 at simplebus0
> sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
> ehci0 at simplebus0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
> ehci1 at simplebus0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
> sxidog0 at simplebus0
> com0 at simplebus0: ns16550, no working fifo
> com0: console
> ampintc0 at simplebus0 nirq 160, ncpu 4
> sxirtc0 at simplebus0
> gpio0 at sxipio0: 32 pins
> gpio1 at sxipio0: 32 pins
> gpio2 at sxipio0: 32 pins
> gpio3 at sxipio0: 32 pins
> gpio4 at sxipio0: 32 pins
> gpio5 at sxipio0: 32 pins
> gpio6 at sxipio0: 32 pins
> gpio7 at sxipio1: 32 pins
> agtimer0 at mainbus0: tick rate 24000 KHz
> scsibus0 at sdmmc0: 2 targets, initiator 0
> sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SL16G, 0080> SCSI2 0/direct removable
> sd0: 15193MB, 512 bytes/sector, 31116288 sectors
> vscsi0 at root
> scsibus1 at vscsi0: 256 targets
> softraid0 at root
> scsibus2 at softraid0: 256 targets
> boot device: sd0
> root on sd0a (da77471dbf10221d.a) swap on sd0b dump on sd0b
> WARNING: preposterous clock chip time
> WARNING: CHECK AND RESET THE DATE!
> Automatic boot in progress: starting file system checks.
> /dev/sd0a (da77471dbf10221d.a): file system is clean; not checking
> /dev/sd0l (da77471dbf10221d.l): file system is clean; not checking
> /dev/sd0d (da77471dbf10221d.d): file system is clean; not checking
> /dev/sd0f (da77471dbf10221d.f): file system is clean; not checking
> /dev/sd0g (da77471dbf10221d.g): file system is clean; not checking
> /dev/sd0h (da77471dbf10221d.h): file system is clean; not checking
> /dev/sd0k (da77471dbf10221d.k): file system is clean; not checking
> /dev/sd0j (da77471dbf10221d.j): file system is clean; not checking
> /dev/sd0e (da77471dbf10221d.e): file system is clean; not checking
> setting tty flags
> pf enabled
> starting network
> reordering libraries: done.
> starting early daemons: syslogd pflogd ntpd.
> starting RPC daemons:.
> savecore: no core dump
> checking quotas: done.
> clearing /tmp
>
> SETTING UP THE GPIO PINS
> I AM PRETTY SURE MY SYNTAX IS CORRECT BUT AM PUZZLED BY THE INVALID ARGUMENT RESPONSE TO UNSET
>
> In rc.securelevel, setting gpio.
> PA15
> gpioctl: GPIOPINUNSET: Invalid argument
> gpioctl: GPIOPINSET: Operation not supported by device
> PD14
> gpioctl: GPIOPINSET: Operation not supported by device
>
>
>
> kern.securelevel: 0 -> 1
> creating runtime link editor directory cache.
> preserving editor files.
> starting network daemons: sshd smtpd sndiod.
> starting local daemons: cron.
> Tue Aug 22 11:30:38 PDT 2017
>
> OpenBSD/armv7 (orangepibsd.graf.lan) (console)
>
> login: sysadmin
> Password:
> Last login: Tue Aug 22 11:23:47 on console
> OpenBSD 6.1-current (GENERIC) #36: Wed Aug 16 00:34:41 MDT 2017
>
> Welcome to OpenBSD: The proactively secure Unix-like operating system.
>
> Please use the sendbug(1) utility to report bugs in the system.
> Before reporting a bug, please try to reproduce it with the latest
> version of the code.  With bug reports, please try to ensure that
> enough information to reproduce the problem is enclosed, and if a
> known fix for it exists, include that as well.
>
> You have new mail.
> $ su
> Password:
> # gpioctl gpio0
> /dev/gpio0: 0 pins
> # gpioctl
> usage: gpioctl [-q] device pin [0 | 1 | 2 | on | off | toggle]
>        gpioctl [-q] device pin set [flags] [name]
>        gpioctl [-q] device pin unset
>        gpioctl [-q] device attach device offset mask [flag]
>        gpioctl [-q] device detach device
>
>
> RC.SECURELEVEL
>
> # more /etc/rc.securelevel
>
>   echo "In rc.securelevel, setting gpio."
>   #
>   # PA15 is status led defined in dtb
>   echo "PA15"
>   /usr/sbin/gpioctl /dev/gpio0 15 unset
>   /usr/sbin/gpioctl /dev/gpio0 15 set out status_led
>   #
>   # PD14 is on pin 12 of the header, not defined in dtb
>   echo "PD14"
>   /usr/sbin/gpioctl /dev/gpio3 14 set out hdr_pin_12
>
>
>
> # /usr/sbin/gpioctl /dev/gpio0 15 unset
> gpioctl: GPIOPINUNSET: Operation not permitted
> # /usr/sbin/gpioctl /dev/gpio0 15 set out status_led
> gpioctl: GPIOPINSET: Operation not permitted
> # man gpioctl
> GPIOCTL(8)                  System Manager's Manual                 GPIOCTL(8)
>
> NAME
>      gpioctl - control GPIO devices
>
> SYNOPSIS
>      gpioctl [-q] device pin [0 | 1 | 2 | on | off | toggle]
>      gpioctl [-q] device pin set [flags] [name]
>      gpioctl [-q] device pin unset
>      gpioctl [-q] device attach device offset mask [flag]
>      gpioctl [-q] device detach device
>
> DESCRIPTION
>      The gpioctl program allows manipulation of GPIO (General Purpose
>      Input/Output) device pins.  Such devices can be either part of the
>      chipset or embedded CPU, or a separate chip.  The usual way of using GPIO
>      is to connect some simple devices such as LEDs and 1-wire thermal sensors
>      to its pins.
>
>      Each GPIO device has an associated device file in the /dev directory.
>      device can be specified with or without the /dev prefix.  For example,
>      /dev/gpio0 or gpio0.
>
>      GPIO pins can be either "read" or "written" with the values of logical 0
>      or 1.  If only a pin number is specified on the command line, the pin
>      state will be read from the GPIO controller and displayed.  To write to a
>      pin, a value must be specified after the pin number.  Values can be
>      either 0 or 1.  A value of 2 has a special meaning: it "toggles" the pin,
>      i.e. changes its state to the opposite.  Instead of the numerical values,
>      the word on, off, or toggle can be used.
>
>      Only pins that have been configured at securelevel 0, typically during
>      system startup, are accessible once the securelevel has been raised.
>      Pins can be given symbolic names for easier use.  Besides using
>      individual pins, device drivers that use GPIO pins can be attached to a
>      gpio(4) device using the gpioctl command.
>
>      The following configuration flags are supported by the GPIO framework.
>      Note that not all the flags can be supported by the particular GPIO
>      controller.
>
>            in      input direction
>            out     output direction
>            inout   bi-directional
>            od      open-drain output
>            pp      push-pull output
>            tri     tri-state (output disabled)
>            pu      internal pull-up enabled
>            pd      internal pull-down enabled
>            iin     invert input
>            iout    invert output
>
>      When attaching an I2C device, if the flag argument is set to 0x01, the
>      order of the SDA and SCL signals is reversed (see gpioiic(4)).
>
>      When executed with only the gpio(4) device name as argument, gpioctl
>      reads information about the GPIO device and displays it.  At securelevel
>      0 the number of physically available pins is displayed, at higher
>      securelevels the number of configured (set) pins is displayed.
>
>      The options are as follows:
>
>      -q      Operate quietly i.e. nothing is printed to stdout.
>
> FILES
>      /dev/gpiou  GPIO device unit u file.
>
> EXAMPLES
>      Configure pin 20 to have push-pull output:
>
>            # gpioctl gpio0 20 set out pp
>
>      Write logical 1 to pin 20:
>
>            # gpioctl gpio0 20 1
>
>      Attach a onewire(4) bus on a gpioow(4) device on pin 4:
>
>            # gpioctl gpio0 attach gpioow 4 0x01
>
>      Detach the gpioow0 device:
>
>            # gpioctl gpio0 detach gpioow0
>
>      Configure pin 5 as output and name it error_led:
>
>            # gpioctl gpio0 5 set out error_led
>
>      Toggle the error_led:
>
>            # gpioctl gpio0 error_led 2
>
> SEE ALSO
>      gpio(4)
>
> HISTORY
>      The gpioctl command first appeared in OpenBSD 3.6.
>
> AUTHORS
>      The gpioctl program was written by Alexander Yurchenko
>      <[hidden email]>.  Device attachment was added by Marc Balmer
>      <[hidden email]>.
>
> OpenBSD 6.1                   September 11, 2015                   OpenBSD 6.1
> #
> #
> #

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Re: looking for help on gpio setup on orange pi one

Stephen Graf
In reply to this post by Stephen Graf
Thank you again for your suggestions. I tried to follow your example but it
did not work out as expected.
For some reason the gpioctl set command is not working at secure level 0 and
without that it is impossible to do anything with the device later.

I can turn the led off and on from u-boot and from openbsd at secure level
0.

See console log below:



-----Original Message-----U-Boot SPL 2017.09-rc2 (Aug 22 2017 - 00:26:16)
DRAM: 512 MiB
Trying to boot from MMC1


U-Boot 2017.09-rc2 (Aug 22 2017 - 00:26:16 -0600) Allwinner Technology

CPU:   Allwinner H3 (SUN8I 1680)
Model: Xunlong Orange Pi One
DRAM:  512 MiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   phy interface0
eth0: ethernet@1c30000
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
scanning bus 0 for devices... 2 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found



Hit any key to stop autoboot:  0
=> gpio set pa15
gpio: pin pa15 (gpio 15) value is 1
=> run bootcmd

**** RED STATUS LED TURNS ON


switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
reading /sun8i-h3-orangepi-one.dtb
14504 bytes read in 28 ms (505.9 KiB/s)
Found EFI removable media binary efi/boot/bootarm.efi
reading efi/boot/bootarm.efi
67356 bytes read in 36 ms (1.8 MiB/s)
## Starting EFI application at 42000000 ...
Scanning disks on usb...
Scanning disks on mmc...
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Found 5 disks
>> OpenBSD/armv7 BOOTARM 1.0
boot> set howto -s
boot>
booting sd0a:/bsd: 3896260+165624+497368 [281717+90+516256+242888]=0x5581d0

OpenBSD/armv7 booting ...
arg0 0xc08581d0 arg1 0x0 arg2 0x48000000
Allocating page tables
freestart = 0x40859000, free_pages = 128935 (0x0001f7a7)
IRQ stack: p0x40887000 v0xc0887000
ABT stack: p0x40888000 v0xc0888000
UND stack: p0x40889000 v0xc0889000
SVC stack: p0x4088a000 v0xc088a000
Creating L1 page table at 0x4085c000
Mapping kernel
Constructing L2 page tables
undefined page pmap [ using 1041408 bytes of bsd ELF symbol table ]
board type: 0
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2017 OpenBSD. All rights reserved.
https://www.OpenBSD.org

OpenBSD 6.2-beta (GENERIC) #43: Tue Aug 22 11:20:56 MDT 2017
    [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
real mem  = 536870912 (512MB)
avail mem = 517414912 (493MB)
mainbus0 at root: Xunlong Orange Pi One
cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
cortex0 at mainbus0
sxiccmu0 at mainbus0
psci0 at mainbus0
simplebus0 at mainbus0: "soc"
sxiccmu1 at simplebus0
sxipio0 at simplebus0: 94 pins
sxipio1 at simplebus0: 12 pins
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
ehci0 at simplebus0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev
2.00/1.00 addr 1
ehci1 at simplebus0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev
2.00/1.00 addr 1
sxidog0 at simplebus0
com0 at simplebus0: ns16550, no working fifo
com0: console
ampintc0 at simplebus0 nirq 160, ncpu 4
sxirtc0 at simplebus0
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
gpio7 at sxipio1: 32 pins
agtimer0 at mainbus0: tick rate 24000 KHz
scsibus0 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SL16G, 0080> SCSI2 0/direct removable
sd0: 15193MB, 512 bytes/sector, 31116288 sectors
umass0 at uhub1 port 1 configuration 1 interface 0 "Lexar JD Secure II +"
rev 2.00/11.00 addr 2
umass0: using SCSI over Bulk-Only
scsibus1 at umass0: 2 targets, initiator 0
sd1 at scsibus1 targ 1 lun 0: <Lexar, JD Secure II +, 1100> SCSI0 0/direct
removable serial.05dca732012100015339
sd1: 1912MB, 512 bytes/sector, 3915776 sectors
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
scsibus3 at softraid0: 256 targets
boot device: sd0
root on sd0a (e50fea1f8609b974.a) swap on sd0b dump on sd0b
WARNING: preposterous clock chip time
WARNING: CHECK AND RESET THE DATE!



Enter pathname of shell or RETURN for sh:
# mount /dev/sd0a /
# mount /dev/sd0f /usr
# mount /dev/sd0e /var
# mount /dev/sd0l /home
# gpioctl gpio0
/dev/gpio0: 32 pins
# gpioctl gpio0 15 set out red_led
gpioctl: GPIOPINSET: Operation not supported by device
# gpioctl gpio0 15 set out
gpioctl: GPIOPINSET: Operation not supported by device
# gpioctl gpio0 15
pin 15: state 1
# gpioctl gpio0 15 toggle
pin 15: state 0 -> 1
# gpioctl gpio0 15 toggle
pin 15: state 1 -> 0
# gpioctl gpio0 15 toggle
pin 15: state 0 -> 1
# exit

**** AGAIN THE RED LED TURNS OFF AND ON AS EXPECTED BUT THE SET COMMAND
FAILS


setting tty flags
pf enabled
starting network
reordering libraries: done.
starting early daemons: syslogd pflogd ntpd.
starting RPC daemons:.
savecore: no core dump
checking quotas: done.
clearing /tmp
kern.securelevel: 0 -> 1
creating runtime link editor directory cache.
preserving editor files.
starting network daemons: sshd smtpd sndiod.
starting local daemons: cron.
Sat Aug 26 05:03:37 PDT 2017

OpenBSD/armv7 (openbsdop1.graf.lan) (console)

login: sysadmin
Password:
Last login: Sat Aug 26 04:52:26 on console
OpenBSD 6.2-beta (GENERIC) #43: Tue Aug 22 11:20:56 MDT 2017

Welcome to OpenBSD: The proactively secure Unix-like operating system.

Please use the sendbug(1) utility to report bugs in the system.
Before reporting a bug, please try to reproduce it with the latest
version of the code.  With bug reports, please try to ensure that
enough information to reproduce the problem is enclosed, and if a
known fix for it exists, include that as well.

You have new mail.
$ su
Password:
# gpioctl gpio0
/dev/gpio0: 0 pins
# gpioctl gpio0 15
gpioctl: GPIOPINREAD: Operation not permitted
#


**** NO PINS ?





From: Artturi Alm [mailto:[hidden email]]
Sent: Friday, August 25, 2017 3:05 PM
To: Stephen Graf <[hidden email]>
Cc: [hidden email]
Subject: Re: looking for help on gpio setup on orange pi one

On Thu, Aug 24, 2017 at 10:26:05PM -0700, Stephen Graf wrote:

> Thank you for your responses and suggestions.
>
> I compared the dtbs of openbsd and a linux (armbian mainline)
> distribution that runs on my orangepi one. The armbian dtb has more
> stuff in it but mostly the items in the openbsd dtb match the armbian
> one.  Both have the same item for PA15 in pinctrl@01c20800:
>
> led_pins@0 {
> pins = "PA15";
> function = "gpio_out";
> linux,phandle = <0x2b>;
> phandle = <0x2b>;
> };
> Neither dtb has any reference to PC4 or PD14, which are brought out to
> the header.
>
> I also compared with the bananapi dtb and the pinctl is very similar
> with a similar definition for a status led.
>
> led_pins@0 {
> pins = "PH24";
> function = "gpio_out";
> linux,phandle = <0x52>;
> phandle = <0x52>;
> };
>
> Bananapi is an A20 device whereas orangepi is H3.
>
> Does openbsd need some definition in the dtb to set up a gpio pin?  
> Could I add something like:
>
> led_pins@0 {
> pins = "PC4";
> function = "gpio_out";
> linux,phandle = <0x2b>;
> phandle = <0x2b>;
> };
>
> What are the phandle lines for?
> Does the "led_pins@0" need to change?
>
> What about something like this:
>
> hdr_pin_16@0 {
> pins = "PC4";
> function = "gpio_out";
> };
>
> hdr_pin_12@0 {
> pins = "PD14";
> function = "gpio_out";
> };
>
> I reloaded the system with the 6.2 snapshot and added the above
> definition for PD14 to the dtb and added a set for PD14 to
> rc.securelevel.  I am still getting the same
> error:
>
> gpioctl: GPIOPINSET: Operation not supported by device
>
> The gpio test log 61.txt has is annotated.
>

Hi,

i just tested the diff that does print pinmuxes during boot, and
unfortunately it does seem as if something somewhere does reset the mux of
leds from output back to input in between toggling the led in u-boot &
printing the mux in sxipio_attach_gpio()..

 => gpio set ph20
gpio: pin ph20 (gpio 244) value is 1
=> gpio set ph21
gpio: pin ph21 (gpio 245) value is 1
=> run bootcmd
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found EFI removable media binary efi/boot/bootarm.efi reading
efi/boot/bootarm.efi ...

...
H21 mux 0<gpio_in>- adding
H22 mux 0<gpio_in>- adding
...

now those got added so that i can seemingly toggle w/o errors, once set back
to output, ymmv. different SoC and all..

Hit any key to stop autoboot:  0
=> gpio toggle ph21
gpio: pin ph21 (gpio 245) value is 1
=> run bootcmd
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found EFI removable media binary efi/boot/bootarm.efi reading
efi/boot/bootarm.efi
64908 bytes read in 39 ms (1.6 MiB/s)
libfdt fdt_check_header(): FDT_ERR_BADMAGIC ## Starting EFI application at
42000000 ...
Scanning disks on scsi...
Scanning disks on usb...
Scanning disks on mmc...
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Found 6 disks

Error: ethernet@01c50000 address not set.
>> OpenBSD/armv7 BOOTARM 0.8
boot> set howto -s
boot>
booting sd0a:/bsd: 3897060+166632+496400 [281226+90+516352+242933]=0x55809c

OpenBSD/armv7 booting ...
arg0 0xc085809c arg1 0x0 arg2 0x48000000 Allocating page tables freestart =
0x40859000, free_pages = 260007 (0x0003f7a7) IRQ stack: p0x40887000
v0xc0887000 ABT stack: p0x40888000 v0xc0888000 UND stack: p0x40889000
v0xc0889000 SVC stack: p0x4088a000 v0xc088a000 Creating L1 page table at
0x4085c000 Mapping kernel Constructing L2 page tables undefined page pmap [
using 1041060 bytes of bsd ELF symbol table ] board type: 0 Copyright (c)
1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2017 OpenBSD. All rights reserved.
https://www.OpenBSD.org

OpenBSD 6.2-beta (GENERIC) #13: Fri Aug 25 23:47:49 EEST 2017
    [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
real mem  = 1073741824 (1024MB)
avail mem = 1043980288 (995MB)
mainbus0 at root: Cubietech Cubieboard2
cpu0 at mainbus0: ARM Cortex-A7 r0p4 (ARMv7)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
cortex0 at mainbus0
sxiccmu0 at mainbus0
psci0 at mainbus0
agtimer0 at mainbus0: tick rate 24000 KHz
simplebus0 at mainbus0: "soc"
sxipio0 at simplebus0: 175 pins
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
ehci0 at simplebus0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev
2.00/1.00 addr 1
sxiahci0 at simplebus0: AHCI 1.1
scsibus0 at sxiahci0: 32 targets
ehci1 at simplebus0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev
2.00/1.00 addr 1
sxidog0 at simplebus0
sxirtc0 at simplebus0
com0 at simplebus0: ns16550, no working fifo
com0: console
sxitwi0 at simplebus0
iic0 at sxitwi0
axppmic0 at iic0 addr 0x34: AXP209, ACIN
sxitwi1 at simplebus0
iic1 at sxitwi1
dwge0 at simplebus0
dwge0: address: fe:e1:ba:d0:20:5d
rlphy0 at dwge0 phy 1: RTL8201L 10/100 PHY, rev. 1
ampintc0 at simplebus0 nirq 160, ncpu 2
A0 mux 5<gmac>- skipping
A1 mux 2<emac>- skipping
A2 mux 5<gmac>- skipping
A3 mux 2<emac>- skipping
A4 mux 5<gmac>- skipping
A5 mux 2<emac>- skipping
A6 mux 5<gmac>- skipping
A7 mux 2<emac>- skipping
A8 mux 5<gmac>- skipping
A9 mux 2<emac>- skipping
A10 mux 5<gmac>- skipping
A11 mux 2<emac>- skipping
A12 mux 5<gmac>- skipping
A13 mux 2<emac>- skipping
A14 mux 5<gmac>- skipping
A15 mux 2<emac>- skipping
A16 mux 5<gmac>- skipping
A17 mux 2<emac>- skipping
B0 mux 2<i2c0>- skipping
B1 mux 1<gpio_out>- adding
B2 mux 0<gpio_in>- adding
B3 mux 4<spdif>- skipping
B4 mux 2<ir0>- skipping
B5 mux 1<gpio_out>- adding
B6 mux 0<gpio_in>- adding
B7 mux 0<gpio_in>- adding
B8 mux 1<gpio_out>- adding
B9 mux 0<gpio_in>- adding
B10 mux 0<gpio_in>- adding
B11 mux 0<gpio_in>- adding
B12 mux 0<gpio_in>- adding
B13 mux 0<gpio_in>- adding
B14 mux 0<gpio_in>- adding
B15 mux 0<gpio_in>- adding
B16 mux 0<gpio_in>- adding
B17 mux 0<gpio_in>- adding
B18 mux 0<gpio_in>- adding
B19 mux 0<gpio_in>- adding
B20 mux 0<gpio_in>- adding
B21 mux 0<gpio_in>- adding
B22 mux 0<gpio_in>- adding
B23 mux 4<invalid>- skipping
C0 mux 0<gpio_in>- adding
C1 mux 0<gpio_in>- adding
C2 mux 0<gpio_in>- adding
C3 mux 0<gpio_in>- adding
C4 mux 0<gpio_in>- adding
C5 mux 0<gpio_in>- adding
C6 mux 0<gpio_in>- adding
C7 mux 0<gpio_in>- adding
C8 mux 0<gpio_in>- adding
C9 mux 0<gpio_in>- adding
C10 mux 0<gpio_in>- adding
C11 mux 0<gpio_in>- adding
C12 mux 0<gpio_in>- adding
C13 mux 0<gpio_in>- adding
C14 mux 0<gpio_in>- adding
C15 mux 0<gpio_in>- adding
C16 mux 0<gpio_in>- adding
C17 mux 0<gpio_in>- adding
C18 mux 0<gpio_in>- adding
C19 mux 0<gpio_in>- adding
C20 mux 0<gpio_in>- adding
C21 mux 0<gpio_in>- adding
C22 mux 0<gpio_in>- adding
C23 mux 0<gpio_in>- adding
C24 mux 0<gpio_in>- adding
D0 mux 0<gpio_in>- adding
D1 mux 0<gpio_in>- adding
D2 mux 0<gpio_in>- adding
D3 mux 0<gpio_in>- adding
D4 mux 0<gpio_in>- adding
D5 mux 0<gpio_in>- adding
D6 mux 0<gpio_in>- adding
D7 mux 0<gpio_in>- adding
D8 mux 0<gpio_in>- adding
D9 mux 0<gpio_in>- adding
D10 mux 0<gpio_in>- adding
D11 mux 0<gpio_in>- adding
D12 mux 0<gpio_in>- adding
D13 mux 0<gpio_in>- adding
D14 mux 0<gpio_in>- adding
D15 mux 0<gpio_in>- adding
D16 mux 0<gpio_in>- adding
D17 mux 0<gpio_in>- adding
D18 mux 0<gpio_in>- adding
D19 mux 0<gpio_in>- adding
D20 mux 0<gpio_in>- adding
D21 mux 0<gpio_in>- adding
D22 mux 0<gpio_in>- adding
D23 mux 0<gpio_in>- adding
D24 mux 0<gpio_in>- adding
D25 mux 0<gpio_in>- adding
D26 mux 0<gpio_in>- adding
D27 mux 0<gpio_in>- adding
E0 mux 0<gpio_in>- adding
E1 mux 0<gpio_in>- adding
E2 mux 0<gpio_in>- adding
E3 mux 0<gpio_in>- adding
E4 mux 0<gpio_in>- adding
E5 mux 0<gpio_in>- adding
E6 mux 0<gpio_in>- adding
E7 mux 0<gpio_in>- adding
E8 mux 0<gpio_in>- adding
E9 mux 0<gpio_in>- adding
E10 mux 0<gpio_in>- adding
E11 mux 0<gpio_in>- adding
F0 mux 2<mmc0>- skipping
F1 mux 1<gpio_out>- adding
F2 mux 0<gpio_in>- adding
F3 mux 4<jtag>- skipping
F4 mux 2<mmc0>- skipping
F5 mux 1<gpio_out>- adding
G0 mux 0<gpio_in>- adding
G1 mux 0<gpio_in>- adding
G2 mux 0<gpio_in>- adding
G3 mux 0<gpio_in>- adding
G4 mux 0<gpio_in>- adding
G5 mux 0<gpio_in>- adding
G6 mux 0<gpio_in>- adding
G7 mux 0<gpio_in>- adding
G8 mux 0<gpio_in>- adding
G9 mux 0<gpio_in>- adding
G10 mux 0<gpio_in>- adding
G11 mux 0<gpio_in>- adding
H0 mux 0<gpio_in>- adding
H1 mux 0<gpio_in>- adding
H2 mux 0<gpio_in>- adding
H3 mux 0<gpio_in>- adding
H4 mux 0<gpio_in>- adding
H5 mux 0<gpio_in>- adding
H6 mux 0<gpio_in>- adding
H7 mux 0<gpio_in>- adding
H8 mux 0<gpio_in>- adding
H9 mux 0<gpio_in>- adding
H10 mux 0<gpio_in>- adding
H11 mux 0<gpio_in>- adding
H12 mux 0<gpio_in>- adding
H13 mux 0<gpio_in>- adding
H14 mux 0<gpio_in>- adding
H15 mux 0<gpio_in>- adding
H16 mux 0<gpio_in>- adding
H17 mux 0<gpio_in>- adding
H18 mux 0<gpio_in>- adding
H19 mux 0<gpio_in>- adding
H20 mux 0<gpio_in>- adding
H21 mux 0<gpio_in>- adding
H22 mux 0<gpio_in>- adding
H23 mux 0<gpio_in>- adding
H24 mux 0<gpio_in>- adding
H25 mux 0<gpio_in>- adding
H26 mux 0<gpio_in>- adding
H27 mux 0<gpio_in>- adding
I0 mux 0<gpio_in>- adding
I1 mux 0<gpio_in>- adding
I2 mux 0<gpio_in>- adding
I3 mux 0<gpio_in>- adding
I4 mux 0<gpio_in>- adding
I5 mux 0<gpio_in>- adding
I6 mux 0<gpio_in>- adding
I7 mux 0<gpio_in>- adding
I8 mux 0<gpio_in>- adding
I9 mux 0<gpio_in>- adding
I10 mux 0<gpio_in>- adding
I11 mux 0<gpio_in>- adding
I12 mux 0<gpio_in>- adding
I13 mux 0<gpio_in>- adding
I14 mux 0<gpio_in>- adding
I15 mux 0<gpio_in>- adding
I16 mux 0<gpio_in>- adding
I17 mux 0<gpio_in>- adding
I18 mux 0<gpio_in>- adding
I19 mux 0<gpio_in>- adding
I20 mux 0<gpio_in>- adding
I21 mux 0<gpio_in>- adding
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
gpio7 at sxipio0: 32 pins
gpio8 at sxipio0: 32 pins
scsibus1 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus1 targ 1 lun 0: <SD/MMC, USD, 0002> SCSI2 0/direct removable
sd0: 7517MB, 512 bytes/sector, 15394816 sectors
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
scsibus3 at softraid0: 256 targets
boot device: sd0
root on sd0a (82aa3db79c6ad6cb.a) swap on sd0b dump on sd0b Enter pathname
of shell or RETURN for sh:
# mount -a
NFS Portmap: RPC: Port mapper failure - RPC: Unable to send

^C
# mount
/dev/sd0a on / type ffs (local)
/dev/sd0e on /home type ffs (local, nodev, nosuid) /dev/sd0d on /usr type
ffs (local, nodev, wxallowed) # gp
gpioctl   gprof
# gpioctl gpio7
/dev/gpio7: 32 pins
# gpioctl gpio7 20 set out green_led
pin 20: caps: in out, flags: in -> out
# gpioctl gpio7 green_led
pin green_led: state 0
# gpioctl gpio7 green_led toggle
pin green_led: state 0 -> 1
# exit
setting tty flags
pf enabled
starting network
DHCPDISCOVER on dwge0 - interval 1
DHCPDISCOVER on dwge0 - interval 1
DHCPOFFER from 192.168.2.2 (00:22:68:10:3d:f0) DHCPREQUEST on dwge0 to
255.255.255.255 DHCPACK from 192.168.2.2 (00:22:68:10:3d:f0) bound to
192.168.2.49 -- renewal in 21600 seconds.
reordering libraries:^C^C failed.
starting early daemons: syslogd pflogd(failed) ntpd.
starting RPC daemons:.
savecore: no core dump
checking quotas: done.
clearing /tmp
kern.securelevel: 0 -> 1
creating runtime link editor directory cache.
preserving editor files.
starting network daemons: sshd smtpd sndiod.
starting local daemons: cron.
Fri Aug 25 19:34:14 EEST 2017
/etc/rc: kernel relinking failed; see /usr/share/compile/GENERIC/relink.log

OpenBSD/armv7 (cubie2.my.domain) (console)

login: root
Password:
Last login: Fri Aug 25 19:22:25 on console OpenBSD 6.2-beta (GENERIC) #13:
Fri Aug 25 23:47:49 EEST 2017

Welcome to OpenBSD: The proactively secure Unix-like operating system.

Please use the sendbug(1) utility to report bugs in the system.
Before reporting a bug, please try to reproduce it with the latest version
of the code.  With bug reports, please try to ensure that enough information
to reproduce the problem is enclosed, and if a known fix for it exists,
include that as well.

You have mail.
root@cubie2:~ # gpioctl gpio7 green_led
pin green_led: state 1
root@cubie2:~ # gpioctl gpio7 green_led toggle pin green_led: state 1 -> 0
root@cubie2:~ # gpioctl gpio7 green_led toggle pin green_led: state 0 -> 1
root@cubie2:~ # it does work. :)

testing is easier in singleuser, so:
>> OpenBSD/armv7 BOOTARM 0.8
boot> set howto -s
boot>

-Artturi

> -----Original Message-----
> From: [hidden email] [mailto:[hidden email]] On Behalf
> Of Artturi Alm
> Sent: Wednesday, August 23, 2017 2:51 PM
> To: Stephen Graf <[hidden email]>
> Cc: [hidden email]
> Subject: Re: looking for help on gpio setup on orange pi one
>
> On Thu, Aug 24, 2017 at 12:13:25AM +0300, Artturi Alm wrote:
> > On Wed, Aug 23, 2017 at 10:05:18AM -0700, Stephen Graf wrote:
> > > From the advice from Mark and the further reading that I did, I
> > > think I am doing the right things.
> > >
> > >  
> > >
> > > I can set the status light from u-boot, but cannot configure the
> > > pin in OpenBSD.
> > >
> > >  
> > >
> > > The attached console log shows the results of my testing with
> > > annotations in caps.
> > >
> >
> > Hi,
> >
> > if you can, i'd like to see the output in dmesg w/diff below, might
> > provide more clues.
> >
>
> Actually, forget about that, as i guess you can 'fix' this by adding
> what is necessary to the .dts of your board, or try from u-boot w/  => fdt
...
> commands. You'll want to look out for allwinner pinctrl, gpio
> dt-bindings, other sunxi dts files for examples etc..
> if all you need is a simple output, faking it as a led for u-boot
> might be the easiest.
>
> gl hf:)
> -Artturi
>




> OpenBSD 6.2-beta (GENERIC) #43: Tue Aug 22 11:20:56 MDT 2017
>     [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
> real mem  = 536870912 (512MB)
> avail mem = 517414912 (493MB)
> mainbus0 at root: Xunlong Orange Pi One
> cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> cortex0 at mainbus0
> sxiccmu0 at mainbus0
> psci0 at mainbus0
> simplebus0 at mainbus0: "soc"
> sxiccmu1 at simplebus0
> sxipio0 at simplebus0: 94 pins
> sxipio1 at simplebus0: 12 pins
> sximmc0 at simplebus0
> sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
> ehci0 at simplebus0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev
> 2.00/1.00 addr 1
> ehci1 at simplebus0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev
> 2.00/1.00 addr 1
> sxidog0 at simplebus0
> com0 at simplebus0: ns16550, no working fifo
> com0: console
> ampintc0 at simplebus0 nirq 160, ncpu 4
> sxirtc0 at simplebus0
> gpio0 at sxipio0: 32 pins
> gpio1 at sxipio0: 32 pins
> gpio2 at sxipio0: 32 pins
> gpio3 at sxipio0: 32 pins
> gpio4 at sxipio0: 32 pins
> gpio5 at sxipio0: 32 pins
> gpio6 at sxipio0: 32 pins
> gpio7 at sxipio1: 32 pins
> agtimer0 at mainbus0: tick rate 24000 KHz
> scsibus0 at sdmmc0: 2 targets, initiator 0
> sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SL16G, 0080> SCSI2 0/direct
> removable
> sd0: 15193MB, 512 bytes/sector, 31116288 sectors
> umass0 at uhub1 port 1 configuration 1 interface 0 "Lexar JD Secure II
> +" rev 2.00/11.00 addr 2
> umass0: using SCSI over Bulk-Only
> scsibus1 at umass0: 2 targets, initiator 0
> sd1 at scsibus1 targ 1 lun 0: <Lexar, JD Secure II +, 1100> SCSI0
> 0/direct removable serial.05dca732012100015339
> sd1: 1912MB, 512 bytes/sector, 3915776 sectors
> vscsi0 at root
> scsibus2 at vscsi0: 256 targets
> softraid0 at root
> scsibus3 at softraid0: 256 targets
> boot device: sd0
> root on sd0a (37e89bdc6451a368.a) swap on sd0b dump on sd0b
> WARNING: preposterous clock chip time
> WARNING: CHECK AND RESET THE DATE!


> U-Boot SPL 2017.09-rc2 (Aug 22 2017 - 00:26:16)
> DRAM: 512 MiB
> Trying to boot from MMC1
>
>
> U-Boot 2017.09-rc2 (Aug 22 2017 - 00:26:16 -0600) Allwinner Technology
>
> CPU:   Allwinner H3 (SUN8I 1680)
> Model: Xunlong Orange Pi One
> DRAM:  512 MiB
> MMC:   SUNXI SD/MMC: 0
> *** Warning - bad CRC, using default environment
>
> In:    serial
> Out:   serial
> Err:   serial
> Net:   phy interface0
> eth0: ethernet@1c30000
> starting USB...
> USB0:   USB EHCI 1.00
> USB1:   USB OHCI 1.0
> scanning bus 0 for devices... 2 USB Device(s) found
>        scanning usb for storage devices... 1 Storage Device(s) found
> Hit any key to stop autoboot:  0 switch to partitions #0, OK
> mmc0 is current device
> Scanning mmc 0:1...
> reading /sun8i-h3-orangepi-one.dtb
> 14504 bytes read in 28 ms (505.9 KiB/s) Found EFI removable media
> binary efi/boot/bootarm.efi reading efi/boot/bootarm.efi
> 67356 bytes read in 35 ms (1.8 MiB/s)
> ## Starting EFI application at 42000000 ...
> Scanning disks on usb...
> Scanning disks on mmc...
> MMC Device 1 not found
> MMC Device 2 not found
> MMC Device 3 not found
> Found 5 disks
> >> OpenBSD/armv7 BOOTARM 1.0
> boot>
> booting sd0a:/bsd: 3886716+164372+498568
> [281602+90+516256+242888]=0x558128
>
> OpenBSD/armv7 booting ...
> arg0 0xc0858128 arg1 0x0 arg2 0x48000000 Allocating page tables
> freestart = 0x40859000, free_pages = 128935 (0x0001f7a7) IRQ stack:
> p0x40887000 v0xc0887000 ABT stack: p0x40888000 v0xc0888000 UND stack:
> p0x40889000 v0xc0889000 SVC stack: p0x4088a000 v0xc088a000 Creating L1
> page table at 0x4085c000 Mapping kernel Constructing L2 page tables
> undefined page pmap [ using 1041292 bytes of bsd ELF symbol table ]
> board type: 0 Copyright (c) 1982, 1986, 1989, 1991, 1993
>         The Regents of the University of California.  All rights reserved.
> Copyright (c) 1995-2017 OpenBSD. All rights reserved.  
> https://www.OpenBSD.org
>
> OpenBSD 6.2-beta (GENERIC) #43: Tue Aug 22 11:20:56 MDT 2017
>     [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
> real mem  = 536870912 (512MB)
> avail mem = 517414912 (493MB)
> mainbus0 at root: Xunlong Orange Pi One
> cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> cortex0 at mainbus0
> sxiccmu0 at mainbus0
> psci0 at mainbus0
> simplebus0 at mainbus0: "soc"
> sxiccmu1 at simplebus0
> sxipio0 at simplebus0: 94 pins
> sxipio1 at simplebus0: 12 pins
> sximmc0 at simplebus0
> sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
> ehci0 at simplebus0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev
> 2.00/1.00 addr 1
> ehci1 at simplebus0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev
> 2.00/1.00 addr 1
> sxidog0 at simplebus0
> com0 at simplebus0: ns16550, no working fifo
> com0: console
> ampintc0 at simplebus0 nirq 160, ncpu 4
> sxirtc0 at simplebus0
> gpio0 at sxipio0: 32 pins
> gpio1 at sxipio0: 32 pins
> gpio2 at sxipio0: 32 pins
> gpio3 at sxipio0: 32 pins
> gpio4 at sxipio0: 32 pins
> gpio5 at sxipio0: 32 pins
> gpio6 at sxipio0: 32 pins
> gpio7 at sxipio1: 32 pins
> agtimer0 at mainbus0: tick rate 24000 KHz
> scsibus0 at sdmmc0: 2 targets, initiator 0
> sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SL16G, 0080> SCSI2 0/direct
> removable
> sd0: 15193MB, 512 bytes/sector, 31116288 sectors
> umass0 at uhub1 port 1 configuration 1 interface 0 "Lexar JD Secure II
> +" rev 2.00/11.00 addr 2
> umass0: using SCSI over Bulk-Only
> scsibus1 at umass0: 2 targets, initiator 0
> sd1 at scsibus1 targ 1 lun 0: <Lexar, JD Secure II +, 1100> SCSI0
> 0/direct removable serial.05dca732012100015339
> sd1: 1912MB, 512 bytes/sector, 3915776 sectors
> vscsi0 at root
> scsibus2 at vscsi0: 256 targets
> softraid0 at root
> scsibus3 at softraid0: 256 targets
> boot device: sd0
> root on sd0a (37e89bdc6451a368.a) swap on sd0b dump on sd0b
> WARNING: preposterous clock chip time
> WARNING: CHECK AND RESET THE DATE!
> Automatic boot in progress: starting file system checks.
> /dev/sd0a (37e89bdc6451a368.a): file system is clean; not checking
> /dev/sd0l (37e89bdc6451a368.l): file system is clean; not checking
> /dev/sd0d (37e89bdc6451a368.d): file system is clean; not checking
> /dev/sd0f (37e89bdc6451a368.f): file system is clean; not checking
> /dev/sd0g (37e89bdc6451a368.g): file system is clean; not checking
> /dev/sd0h (37e89bdc6451a368.h): file system is clean; not checking
> /dev/sd0k (37e89bdc6451a368.k): file system is clean; not checking
> /dev/sd0j (37e89bdc6451a368.j): file system is clean; not checking
> /dev/sd0e (37e89bdc6451a368.e): file system is clean; not checking
> setting tty flags pf enabled starting network reordering libraries:
> done.
> starting early daemons: syslogd pflogd ntpd.
> starting RPC daemons:.
> savecore: no core dump
> checking quotas: done.
> clearing /tmp
> In rc.securelevel, setting gpio.
> PD14
> gpioctl: GPIOPINSET: Operation not supported by device
> kern.securelevel: 0 -> 1
> creating runtime link editor directory cache.
> preserving editor files.
> starting network daemons: sshd smtpd sndiod.
> starting local daemons: cron.
> Thu Aug 24 03:08:27 PDT 2017
>
> OpenBSD/armv7 (openbsdtestdtb.graf.lan) (console)
>
> login:

> U-Boot SPL 2017.07 (Aug 15 2017 - 07:39:48)
> DRAM: 512 MiB
> Trying to boot from MMC1
>
>
> U-Boot 2017.07 (Aug 15 2017 - 07:39:48 -0600) Allwinner Technology
>
> CPU:   Allwinner H3 (SUN8I 1680)
> Model: Xunlong Orange Pi One
> DRAM:  512 MiB
> MMC:   SUNXI SD/MMC: 0
> *** Warning - bad CRC, using default environment
>
> In:    serial
> Out:   serial
> Err:   serial
> Net:   phy interface0
> eth0: ethernet@1c30000
> starting USB...
> USB0:   USB EHCI 1.00
> USB1:   USB OHCI 1.0
> scanning bus 0 for devices... 1 USB Device(s) found
>        scanning usb for storage devices... 0 Storage Device(s) found
> Hit any key to stop autoboot:  0
>
>
> THE FOLLOWING WORKS AND TURNS ON AND OFF THE RED STATUS LIGHT ON THE
> BOARD
>
> => gpio set PA15
> gpio: pin PA15 (gpio 15) value is 1
> => gpio clear PA15
> gpio: pin PA15 (gpio 15) value is 0
> => gpio set PA15
> gpio: pin PA15 (gpio 15) value is 1
> => gpio status -a PA15
> Bank PA:
> PA15: output: 1 [ ]
>
>
>
> => boot
> switch to partitions #0, OK
> mmc0 is current device
> Scanning mmc 0:1...
> reading /sun8i-h3-orangepi-one.dtb
> 14436 bytes read in 25 ms (563.5 KiB/s) Found EFI removable media
> binary efi/boot/bootarm.efi reading efi/boot/bootarm.efi
> 65448 bytes read in 39 ms (1.6 MiB/s)
> ## Starting EFI application at 42000000 ...
> Scanning disks on usb...
> Scanning disks on mmc...
> MMC Device 1 not found
> MMC Device 2 not found
> MMC Device 3 not found
> Found 5 disks
> >> OpenBSD/armv7 BOOTARM 0.9
> boot>
> booting sd0a:/bsd: 3887120+167224+496676
> [281343+90+515936+242597]=0x558184
>
> OpenBSD/armv7 booting ...
> arg0 0xc0858184 arg1 0x0 arg2 0x48000000 Allocating page tables
> freestart = 0x40859000, free_pages = 128935 (0x0001f7a7) IRQ stack:
> p0x40887000 v0xc0887000 ABT stack: p0x40888000 v0xc0888000 UND stack:
> p0x40889000 v0xc0889000 SVC stack: p0x4088a000 v0xc088a000 Creating L1
> page table at 0x4085c000 Mapping kernel Constructing L2 page tables
> undefined page pmap [ using 1040424 bytes of bsd ELF symbol table ]
> board type: 0 Copyright (c) 1982, 1986, 1989, 1991, 1993
>         The Regents of the University of California.  All rights reserved.
> Copyright (c) 1995-2017 OpenBSD. All rights reserved.  
> https://www.OpenBSD.org
>
> OpenBSD 6.1-current (GENERIC) #36: Wed Aug 16 00:34:41 MDT 2017
>     [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
> real mem  = 536870912 (512MB)
> avail mem = 517414912 (493MB)
> mainbus0 at root: Xunlong Orange Pi One
> cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> cortex0 at mainbus0
> sxiccmu0 at mainbus0
> psci0 at mainbus0
> simplebus0 at mainbus0: "soc"
> sxiccmu1 at simplebus0
> sxipio0 at simplebus0: 94 pins
> sxipio1 at simplebus0: 12 pins
> sximmc0 at simplebus0
> sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
> ehci0 at simplebus0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev
> 2.00/1.00 addr 1
> ehci1 at simplebus0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev
> 2.00/1.00 addr 1
> sxidog0 at simplebus0
> com0 at simplebus0: ns16550, no working fifo
> com0: console
> ampintc0 at simplebus0 nirq 160, ncpu 4
> sxirtc0 at simplebus0
> gpio0 at sxipio0: 32 pins
> gpio1 at sxipio0: 32 pins
> gpio2 at sxipio0: 32 pins
> gpio3 at sxipio0: 32 pins
> gpio4 at sxipio0: 32 pins
> gpio5 at sxipio0: 32 pins
> gpio6 at sxipio0: 32 pins
> gpio7 at sxipio1: 32 pins
> agtimer0 at mainbus0: tick rate 24000 KHz
> scsibus0 at sdmmc0: 2 targets, initiator 0
> sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SL16G, 0080> SCSI2 0/direct
> removable
> sd0: 15193MB, 512 bytes/sector, 31116288 sectors
> vscsi0 at root
> scsibus1 at vscsi0: 256 targets
> softraid0 at root
> scsibus2 at softraid0: 256 targets
> boot device: sd0
> root on sd0a (da77471dbf10221d.a) swap on sd0b dump on sd0b
> WARNING: preposterous clock chip time
> WARNING: CHECK AND RESET THE DATE!
> Automatic boot in progress: starting file system checks.
> /dev/sd0a (da77471dbf10221d.a): file system is clean; not checking
> /dev/sd0l (da77471dbf10221d.l): file system is clean; not checking
> /dev/sd0d (da77471dbf10221d.d): file system is clean; not checking
> /dev/sd0f (da77471dbf10221d.f): file system is clean; not checking
> /dev/sd0g (da77471dbf10221d.g): file system is clean; not checking
> /dev/sd0h (da77471dbf10221d.h): file system is clean; not checking
> /dev/sd0k (da77471dbf10221d.k): file system is clean; not checking
> /dev/sd0j (da77471dbf10221d.j): file system is clean; not checking
> /dev/sd0e (da77471dbf10221d.e): file system is clean; not checking
> setting tty flags pf enabled starting network reordering libraries:
> done.
> starting early daemons: syslogd pflogd ntpd.
> starting RPC daemons:.
> savecore: no core dump
> checking quotas: done.
> clearing /tmp
>
> SETTING UP THE GPIO PINS
> I AM PRETTY SURE MY SYNTAX IS CORRECT BUT AM PUZZLED BY THE INVALID
> ARGUMENT RESPONSE TO UNSET
>
> In rc.securelevel, setting gpio.
> PA15
> gpioctl: GPIOPINUNSET: Invalid argument
> gpioctl: GPIOPINSET: Operation not supported by device
> PD14
> gpioctl: GPIOPINSET: Operation not supported by device
>
>
>
> kern.securelevel: 0 -> 1
> creating runtime link editor directory cache.
> preserving editor files.
> starting network daemons: sshd smtpd sndiod.
> starting local daemons: cron.
> Tue Aug 22 11:30:38 PDT 2017
>
> OpenBSD/armv7 (orangepibsd.graf.lan) (console)
>
> login: sysadmin
> Password:
> Last login: Tue Aug 22 11:23:47 on console OpenBSD 6.1-current
> (GENERIC) #36: Wed Aug 16 00:34:41 MDT 2017
>
> Welcome to OpenBSD: The proactively secure Unix-like operating system.
>
> Please use the sendbug(1) utility to report bugs in the system.
> Before reporting a bug, please try to reproduce it with the latest
> version of the code.  With bug reports, please try to ensure that
> enough information to reproduce the problem is enclosed, and if a
> known fix for it exists, include that as well.
>
> You have new mail.
> $ su
> Password:
> # gpioctl gpio0
> /dev/gpio0: 0 pins
> # gpioctl
> usage: gpioctl [-q] device pin [0 | 1 | 2 | on | off | toggle]
>        gpioctl [-q] device pin set [flags] [name]
>        gpioctl [-q] device pin unset
>        gpioctl [-q] device attach device offset mask [flag]
>        gpioctl [-q] device detach device
>
>
> RC.SECURELEVEL
>
> # more /etc/rc.securelevel
>
>   echo "In rc.securelevel, setting gpio."
>   #
>   # PA15 is status led defined in dtb
>   echo "PA15"
>   /usr/sbin/gpioctl /dev/gpio0 15 unset
>   /usr/sbin/gpioctl /dev/gpio0 15 set out status_led
>   #
>   # PD14 is on pin 12 of the header, not defined in dtb
>   echo "PD14"
>   /usr/sbin/gpioctl /dev/gpio3 14 set out hdr_pin_12
>
>
>
> # /usr/sbin/gpioctl /dev/gpio0 15 unset
> gpioctl: GPIOPINUNSET: Operation not permitted # /usr/sbin/gpioctl
> /dev/gpio0 15 set out status_led
> gpioctl: GPIOPINSET: Operation not permitted # man gpioctl
> GPIOCTL(8)                  System Manager's Manual
GPIOCTL(8)

>
> NAME
>      gpioctl - control GPIO devices
>
> SYNOPSIS
>      gpioctl [-q] device pin [0 | 1 | 2 | on | off | toggle]
>      gpioctl [-q] device pin set [flags] [name]
>      gpioctl [-q] device pin unset
>      gpioctl [-q] device attach device offset mask [flag]
>      gpioctl [-q] device detach device
>
> DESCRIPTION
>      The gpioctl program allows manipulation of GPIO (General Purpose
>      Input/Output) device pins.  Such devices can be either part of the
>      chipset or embedded CPU, or a separate chip.  The usual way of using
GPIO
>      is to connect some simple devices such as LEDs and 1-wire thermal
sensors
>      to its pins.
>
>      Each GPIO device has an associated device file in the /dev directory.
>      device can be specified with or without the /dev prefix.  For
example,
>      /dev/gpio0 or gpio0.
>
>      GPIO pins can be either "read" or "written" with the values of
logical 0
>      or 1.  If only a pin number is specified on the command line, the pin
>      state will be read from the GPIO controller and displayed.  To write
to a
>      pin, a value must be specified after the pin number.  Values can be
>      either 0 or 1.  A value of 2 has a special meaning: it "toggles" the
pin,
>      i.e. changes its state to the opposite.  Instead of the numerical
values,
>      the word on, off, or toggle can be used.
>
>      Only pins that have been configured at securelevel 0, typically
during
>      system startup, are accessible once the securelevel has been raised.
>      Pins can be given symbolic names for easier use.  Besides using
>      individual pins, device drivers that use GPIO pins can be attached to
a
>      gpio(4) device using the gpioctl command.
>
>      The following configuration flags are supported by the GPIO
framework.

>      Note that not all the flags can be supported by the particular GPIO
>      controller.
>
>            in      input direction
>            out     output direction
>            inout   bi-directional
>            od      open-drain output
>            pp      push-pull output
>            tri     tri-state (output disabled)
>            pu      internal pull-up enabled
>            pd      internal pull-down enabled
>            iin     invert input
>            iout    invert output
>
>      When attaching an I2C device, if the flag argument is set to 0x01,
the
>      order of the SDA and SCL signals is reversed (see gpioiic(4)).
>
>      When executed with only the gpio(4) device name as argument, gpioctl
>      reads information about the GPIO device and displays it.  At
securelevel

>      0 the number of physically available pins is displayed, at higher
>      securelevels the number of configured (set) pins is displayed.
>
>      The options are as follows:
>
>      -q      Operate quietly i.e. nothing is printed to stdout.
>
> FILES
>      /dev/gpiou  GPIO device unit u file.
>
> EXAMPLES
>      Configure pin 20 to have push-pull output:
>
>            # gpioctl gpio0 20 set out pp
>
>      Write logical 1 to pin 20:
>
>            # gpioctl gpio0 20 1
>
>      Attach a onewire(4) bus on a gpioow(4) device on pin 4:
>
>            # gpioctl gpio0 attach gpioow 4 0x01
>
>      Detach the gpioow0 device:
>
>            # gpioctl gpio0 detach gpioow0
>
>      Configure pin 5 as output and name it error_led:
>
>            # gpioctl gpio0 5 set out error_led
>
>      Toggle the error_led:
>
>            # gpioctl gpio0 error_led 2
>
> SEE ALSO
>      gpio(4)
>
> HISTORY
>      The gpioctl command first appeared in OpenBSD 3.6.
>
> AUTHORS
>      The gpioctl program was written by Alexander Yurchenko
>      <[hidden email]>.  Device attachment was added by Marc Balmer
>      <[hidden email]>.
>
> OpenBSD 6.1                   September 11, 2015                   OpenBSD
6.1
> #
> #
> #


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Re: looking for help on gpio setup on orange pi one

Mark Kettenis
> From: "Stephen Graf" <[hidden email]>
> Date: Sat, 26 Aug 2017 11:58:58 -0700
>
> Thank you again for your suggestions. I tried to follow your example but it
> did not work out as expected.
> For some reason the gpioctl set command is not working at secure level 0 and
> without that it is impossible to do anything with the device later.

You should run the diff that Artturi send in an early mail.  That
produces output like:

> A0 mux 5<gmac>- skipping
> A1 mux 2<emac>- skipping
> A2 mux 5<gmac>- skipping
> A3 mux 2<emac>- skipping
> A4 mux 5<gmac>- skipping
> A5 mux 2<emac>- skipping
> A6 mux 5<gmac>- skipping
> A7 mux 2<emac>- skipping
> A8 mux 5<gmac>- skipping
> A9 mux 2<emac>- skipping
> A10 mux 5<gmac>- skipping
> A11 mux 2<emac>- skipping
> A12 mux 5<gmac>- skipping
> A13 mux 2<emac>- skipping
> A14 mux 5<gmac>- skipping
> A15 mux 2<emac>- skipping
> A16 mux 5<gmac>- skipping
> A17 mux 2<emac>- skipping
> B0 mux 2<i2c0>- skipping
> B1 mux 1<gpio_out>- adding
> B2 mux 0<gpio_in>- adding
> B3 mux 4<spdif>- skipping
> B4 mux 2<ir0>- skipping
> B5 mux 1<gpio_out>- adding
> B6 mux 0<gpio_in>- adding
> B7 mux 0<gpio_in>- adding
> B8 mux 1<gpio_out>- adding
> B9 mux 0<gpio_in>- adding
> B10 mux 0<gpio_in>- adding
> B11 mux 0<gpio_in>- adding
> B12 mux 0<gpio_in>- adding
> B13 mux 0<gpio_in>- adding
> B14 mux 0<gpio_in>- adding
> B15 mux 0<gpio_in>- adding
> B16 mux 0<gpio_in>- adding
> B17 mux 0<gpio_in>- adding
> B18 mux 0<gpio_in>- adding
> B19 mux 0<gpio_in>- adding
> B20 mux 0<gpio_in>- adding
> B21 mux 0<gpio_in>- adding
> B22 mux 0<gpio_in>- adding
> B23 mux 4<invalid>- skipping
> C0 mux 0<gpio_in>- adding
> C1 mux 0<gpio_in>- adding
> C2 mux 0<gpio_in>- adding
> C3 mux 0<gpio_in>- adding
> C4 mux 0<gpio_in>- adding
> C5 mux 0<gpio_in>- adding
> C6 mux 0<gpio_in>- adding
> C7 mux 0<gpio_in>- adding
> C8 mux 0<gpio_in>- adding
> C9 mux 0<gpio_in>- adding
> C10 mux 0<gpio_in>- adding
> C11 mux 0<gpio_in>- adding
> C12 mux 0<gpio_in>- adding
> C13 mux 0<gpio_in>- adding
> C14 mux 0<gpio_in>- adding
> C15 mux 0<gpio_in>- adding
> C16 mux 0<gpio_in>- adding
> C17 mux 0<gpio_in>- adding
> C18 mux 0<gpio_in>- adding
> C19 mux 0<gpio_in>- adding
> C20 mux 0<gpio_in>- adding
> C21 mux 0<gpio_in>- adding
> C22 mux 0<gpio_in>- adding
> C23 mux 0<gpio_in>- adding
> C24 mux 0<gpio_in>- adding
> D0 mux 0<gpio_in>- adding
> D1 mux 0<gpio_in>- adding
> D2 mux 0<gpio_in>- adding
> D3 mux 0<gpio_in>- adding
> D4 mux 0<gpio_in>- adding
> D5 mux 0<gpio_in>- adding
> D6 mux 0<gpio_in>- adding
> D7 mux 0<gpio_in>- adding
> D8 mux 0<gpio_in>- adding
> D9 mux 0<gpio_in>- adding
> D10 mux 0<gpio_in>- adding
> D11 mux 0<gpio_in>- adding
> D12 mux 0<gpio_in>- adding
> D13 mux 0<gpio_in>- adding
> D14 mux 0<gpio_in>- adding
> D15 mux 0<gpio_in>- adding
> D16 mux 0<gpio_in>- adding
> D17 mux 0<gpio_in>- adding
> D18 mux 0<gpio_in>- adding
> D19 mux 0<gpio_in>- adding
> D20 mux 0<gpio_in>- adding
> D21 mux 0<gpio_in>- adding
> D22 mux 0<gpio_in>- adding
> D23 mux 0<gpio_in>- adding
> D24 mux 0<gpio_in>- adding
> D25 mux 0<gpio_in>- adding
> D26 mux 0<gpio_in>- adding
> D27 mux 0<gpio_in>- adding
> E0 mux 0<gpio_in>- adding
> E1 mux 0<gpio_in>- adding
> E2 mux 0<gpio_in>- adding
> E3 mux 0<gpio_in>- adding
> E4 mux 0<gpio_in>- adding
> E5 mux 0<gpio_in>- adding
> E6 mux 0<gpio_in>- adding
> E7 mux 0<gpio_in>- adding
> E8 mux 0<gpio_in>- adding
> E9 mux 0<gpio_in>- adding
> E10 mux 0<gpio_in>- adding
> E11 mux 0<gpio_in>- adding
> F0 mux 2<mmc0>- skipping
> F1 mux 1<gpio_out>- adding
> F2 mux 0<gpio_in>- adding
> F3 mux 4<jtag>- skipping
> F4 mux 2<mmc0>- skipping
> F5 mux 1<gpio_out>- adding
> G0 mux 0<gpio_in>- adding
> G1 mux 0<gpio_in>- adding
> G2 mux 0<gpio_in>- adding
> G3 mux 0<gpio_in>- adding
> G4 mux 0<gpio_in>- adding
> G5 mux 0<gpio_in>- adding
> G6 mux 0<gpio_in>- adding
> G7 mux 0<gpio_in>- adding
> G8 mux 0<gpio_in>- adding
> G9 mux 0<gpio_in>- adding
> G10 mux 0<gpio_in>- adding
> G11 mux 0<gpio_in>- adding
> H0 mux 0<gpio_in>- adding
> H1 mux 0<gpio_in>- adding
> H2 mux 0<gpio_in>- adding
> H3 mux 0<gpio_in>- adding
> H4 mux 0<gpio_in>- adding
> H5 mux 0<gpio_in>- adding
> H6 mux 0<gpio_in>- adding
> H7 mux 0<gpio_in>- adding
> H8 mux 0<gpio_in>- adding
> H9 mux 0<gpio_in>- adding
> H10 mux 0<gpio_in>- adding
> H11 mux 0<gpio_in>- adding
> H12 mux 0<gpio_in>- adding
> H13 mux 0<gpio_in>- adding
> H14 mux 0<gpio_in>- adding
> H15 mux 0<gpio_in>- adding
> H16 mux 0<gpio_in>- adding
> H17 mux 0<gpio_in>- adding
> H18 mux 0<gpio_in>- adding
> H19 mux 0<gpio_in>- adding
> H20 mux 0<gpio_in>- adding
> H21 mux 0<gpio_in>- adding
> H22 mux 0<gpio_in>- adding
> H23 mux 0<gpio_in>- adding
> H24 mux 0<gpio_in>- adding
> H25 mux 0<gpio_in>- adding
> H26 mux 0<gpio_in>- adding
> H27 mux 0<gpio_in>- adding
> I0 mux 0<gpio_in>- adding
> I1 mux 0<gpio_in>- adding
> I2 mux 0<gpio_in>- adding
> I3 mux 0<gpio_in>- adding
> I4 mux 0<gpio_in>- adding
> I5 mux 0<gpio_in>- adding
> I6 mux 0<gpio_in>- adding
> I7 mux 0<gpio_in>- adding
> I8 mux 0<gpio_in>- adding
> I9 mux 0<gpio_in>- adding
> I10 mux 0<gpio_in>- adding
> I11 mux 0<gpio_in>- adding
> I12 mux 0<gpio_in>- adding
> I13 mux 0<gpio_in>- adding
> I14 mux 0<gpio_in>- adding
> I15 mux 0<gpio_in>- adding
> I16 mux 0<gpio_in>- adding
> I17 mux 0<gpio_in>- adding
> I18 mux 0<gpio_in>- adding
> I19 mux 0<gpio_in>- adding
> I20 mux 0<gpio_in>- adding
> I21 mux 0<gpio_in>- adding

which allows us to see how the pins are configured and whether they're
made available.

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Re: looking for help on gpio setup on orange pi one

Artturi Alm
On Sat, Aug 26, 2017 at 09:29:31PM +0200, Mark Kettenis wrote:

> > From: "Stephen Graf" <[hidden email]>
> > Date: Sat, 26 Aug 2017 11:58:58 -0700
> >
> > Thank you again for your suggestions. I tried to follow your example but it
> > did not work out as expected.
> > For some reason the gpioctl set command is not working at secure level 0 and
> > without that it is impossible to do anything with the device later.
>
> You should run the diff that Artturi send in an early mail.  That
> produces output like:
>

i'm almost overtired atm., but after comparing datasheets i decided to
take a quick look at sxipio again, and stumbled upon these shifts.

sxipio_config_pin:
337         mux = (config & GPIO_CONFIG_OUTPUT) ? 1 : 0;
338         off = (pin & 0x7) << 2;
339         SXICMS4(sc, SXIPIO_CFG(port, pin), 0x7 << off, mux << off);

sxipio_attach_gpio:
460                 /* Get pin configuration. */
461                 reg = SXIREAD4(sc, SXIPIO_CFG(port, pin));
462                 cfg = (reg >> (pin & 0x7)) & 0x7;

1:1?
-Artturi


> > A0 mux 5<gmac>- skipping
> > A1 mux 2<emac>- skipping
> > A2 mux 5<gmac>- skipping
> > A3 mux 2<emac>- skipping
> > A4 mux 5<gmac>- skipping
> > A5 mux 2<emac>- skipping
> > A6 mux 5<gmac>- skipping
> > A7 mux 2<emac>- skipping
> > A8 mux 5<gmac>- skipping
> > A9 mux 2<emac>- skipping
> > A10 mux 5<gmac>- skipping
> > A11 mux 2<emac>- skipping
> > A12 mux 5<gmac>- skipping
> > A13 mux 2<emac>- skipping
> > A14 mux 5<gmac>- skipping
> > A15 mux 2<emac>- skipping
> > A16 mux 5<gmac>- skipping
> > A17 mux 2<emac>- skipping
> > B0 mux 2<i2c0>- skipping
> > B1 mux 1<gpio_out>- adding
> > B2 mux 0<gpio_in>- adding
> > B3 mux 4<spdif>- skipping
> > B4 mux 2<ir0>- skipping
> > B5 mux 1<gpio_out>- adding
> > B6 mux 0<gpio_in>- adding
> > B7 mux 0<gpio_in>- adding
> > B8 mux 1<gpio_out>- adding
> > B9 mux 0<gpio_in>- adding
> > B10 mux 0<gpio_in>- adding
> > B11 mux 0<gpio_in>- adding
> > B12 mux 0<gpio_in>- adding
> > B13 mux 0<gpio_in>- adding
> > B14 mux 0<gpio_in>- adding
> > B15 mux 0<gpio_in>- adding
> > B16 mux 0<gpio_in>- adding
> > B17 mux 0<gpio_in>- adding
> > B18 mux 0<gpio_in>- adding
> > B19 mux 0<gpio_in>- adding
> > B20 mux 0<gpio_in>- adding
> > B21 mux 0<gpio_in>- adding
> > B22 mux 0<gpio_in>- adding
> > B23 mux 4<invalid>- skipping
> > C0 mux 0<gpio_in>- adding
> > C1 mux 0<gpio_in>- adding
> > C2 mux 0<gpio_in>- adding
> > C3 mux 0<gpio_in>- adding
> > C4 mux 0<gpio_in>- adding
> > C5 mux 0<gpio_in>- adding
> > C6 mux 0<gpio_in>- adding
> > C7 mux 0<gpio_in>- adding
> > C8 mux 0<gpio_in>- adding
> > C9 mux 0<gpio_in>- adding
> > C10 mux 0<gpio_in>- adding
> > C11 mux 0<gpio_in>- adding
> > C12 mux 0<gpio_in>- adding
> > C13 mux 0<gpio_in>- adding
> > C14 mux 0<gpio_in>- adding
> > C15 mux 0<gpio_in>- adding
> > C16 mux 0<gpio_in>- adding
> > C17 mux 0<gpio_in>- adding
> > C18 mux 0<gpio_in>- adding
> > C19 mux 0<gpio_in>- adding
> > C20 mux 0<gpio_in>- adding
> > C21 mux 0<gpio_in>- adding
> > C22 mux 0<gpio_in>- adding
> > C23 mux 0<gpio_in>- adding
> > C24 mux 0<gpio_in>- adding
> > D0 mux 0<gpio_in>- adding
> > D1 mux 0<gpio_in>- adding
> > D2 mux 0<gpio_in>- adding
> > D3 mux 0<gpio_in>- adding
> > D4 mux 0<gpio_in>- adding
> > D5 mux 0<gpio_in>- adding
> > D6 mux 0<gpio_in>- adding
> > D7 mux 0<gpio_in>- adding
> > D8 mux 0<gpio_in>- adding
> > D9 mux 0<gpio_in>- adding
> > D10 mux 0<gpio_in>- adding
> > D11 mux 0<gpio_in>- adding
> > D12 mux 0<gpio_in>- adding
> > D13 mux 0<gpio_in>- adding
> > D14 mux 0<gpio_in>- adding
> > D15 mux 0<gpio_in>- adding
> > D16 mux 0<gpio_in>- adding
> > D17 mux 0<gpio_in>- adding
> > D18 mux 0<gpio_in>- adding
> > D19 mux 0<gpio_in>- adding
> > D20 mux 0<gpio_in>- adding
> > D21 mux 0<gpio_in>- adding
> > D22 mux 0<gpio_in>- adding
> > D23 mux 0<gpio_in>- adding
> > D24 mux 0<gpio_in>- adding
> > D25 mux 0<gpio_in>- adding
> > D26 mux 0<gpio_in>- adding
> > D27 mux 0<gpio_in>- adding
> > E0 mux 0<gpio_in>- adding
> > E1 mux 0<gpio_in>- adding
> > E2 mux 0<gpio_in>- adding
> > E3 mux 0<gpio_in>- adding
> > E4 mux 0<gpio_in>- adding
> > E5 mux 0<gpio_in>- adding
> > E6 mux 0<gpio_in>- adding
> > E7 mux 0<gpio_in>- adding
> > E8 mux 0<gpio_in>- adding
> > E9 mux 0<gpio_in>- adding
> > E10 mux 0<gpio_in>- adding
> > E11 mux 0<gpio_in>- adding
> > F0 mux 2<mmc0>- skipping
> > F1 mux 1<gpio_out>- adding
> > F2 mux 0<gpio_in>- adding
> > F3 mux 4<jtag>- skipping
> > F4 mux 2<mmc0>- skipping
> > F5 mux 1<gpio_out>- adding
> > G0 mux 0<gpio_in>- adding
> > G1 mux 0<gpio_in>- adding
> > G2 mux 0<gpio_in>- adding
> > G3 mux 0<gpio_in>- adding
> > G4 mux 0<gpio_in>- adding
> > G5 mux 0<gpio_in>- adding
> > G6 mux 0<gpio_in>- adding
> > G7 mux 0<gpio_in>- adding
> > G8 mux 0<gpio_in>- adding
> > G9 mux 0<gpio_in>- adding
> > G10 mux 0<gpio_in>- adding
> > G11 mux 0<gpio_in>- adding
> > H0 mux 0<gpio_in>- adding
> > H1 mux 0<gpio_in>- adding
> > H2 mux 0<gpio_in>- adding
> > H3 mux 0<gpio_in>- adding
> > H4 mux 0<gpio_in>- adding
> > H5 mux 0<gpio_in>- adding
> > H6 mux 0<gpio_in>- adding
> > H7 mux 0<gpio_in>- adding
> > H8 mux 0<gpio_in>- adding
> > H9 mux 0<gpio_in>- adding
> > H10 mux 0<gpio_in>- adding
> > H11 mux 0<gpio_in>- adding
> > H12 mux 0<gpio_in>- adding
> > H13 mux 0<gpio_in>- adding
> > H14 mux 0<gpio_in>- adding
> > H15 mux 0<gpio_in>- adding
> > H16 mux 0<gpio_in>- adding
> > H17 mux 0<gpio_in>- adding
> > H18 mux 0<gpio_in>- adding
> > H19 mux 0<gpio_in>- adding
> > H20 mux 0<gpio_in>- adding
> > H21 mux 0<gpio_in>- adding
> > H22 mux 0<gpio_in>- adding
> > H23 mux 0<gpio_in>- adding
> > H24 mux 0<gpio_in>- adding
> > H25 mux 0<gpio_in>- adding
> > H26 mux 0<gpio_in>- adding
> > H27 mux 0<gpio_in>- adding
> > I0 mux 0<gpio_in>- adding
> > I1 mux 0<gpio_in>- adding
> > I2 mux 0<gpio_in>- adding
> > I3 mux 0<gpio_in>- adding
> > I4 mux 0<gpio_in>- adding
> > I5 mux 0<gpio_in>- adding
> > I6 mux 0<gpio_in>- adding
> > I7 mux 0<gpio_in>- adding
> > I8 mux 0<gpio_in>- adding
> > I9 mux 0<gpio_in>- adding
> > I10 mux 0<gpio_in>- adding
> > I11 mux 0<gpio_in>- adding
> > I12 mux 0<gpio_in>- adding
> > I13 mux 0<gpio_in>- adding
> > I14 mux 0<gpio_in>- adding
> > I15 mux 0<gpio_in>- adding
> > I16 mux 0<gpio_in>- adding
> > I17 mux 0<gpio_in>- adding
> > I18 mux 0<gpio_in>- adding
> > I19 mux 0<gpio_in>- adding
> > I20 mux 0<gpio_in>- adding
> > I21 mux 0<gpio_in>- adding
>
> which allows us to see how the pins are configured and whether they're
> made available.

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Re: looking for help on gpio setup on orange pi one

Artturi Alm
On Mon, Aug 28, 2017 at 09:32:04AM +0300, Artturi Alm wrote:

> On Sat, Aug 26, 2017 at 09:29:31PM +0200, Mark Kettenis wrote:
> > > From: "Stephen Graf" <[hidden email]>
> > > Date: Sat, 26 Aug 2017 11:58:58 -0700
> > >
> > > Thank you again for your suggestions. I tried to follow your example but it
> > > did not work out as expected.
> > > For some reason the gpioctl set command is not working at secure level 0 and
> > > without that it is impossible to do anything with the device later.
> >
> > You should run the diff that Artturi send in an early mail.  That
> > produces output like:
> >
>
> i'm almost overtired atm., but after comparing datasheets i decided to
> take a quick look at sxipio again, and stumbled upon these shifts.
>
> sxipio_config_pin:
> 337         mux = (config & GPIO_CONFIG_OUTPUT) ? 1 : 0;
> 338         off = (pin & 0x7) << 2;
> 339         SXICMS4(sc, SXIPIO_CFG(port, pin), 0x7 << off, mux << off);
>
> sxipio_attach_gpio:
> 460                 /* Get pin configuration. */
> 461                 reg = SXIREAD4(sc, SXIPIO_CFG(port, pin));
> 462                 cfg = (reg >> (pin & 0x7)) & 0x7;
>
> 1:1?
> -Artturi
>

So, i was thinking something like this (untested):

diff --git a/sys/dev/fdt/sxipio.c b/sys/dev/fdt/sxipio.c
index 643226ecd19..9de710ffd5c 100644
--- a/sys/dev/fdt/sxipio.c
+++ b/sys/dev/fdt/sxipio.c
@@ -446,7 +446,7 @@ sxipio_attach_gpio(struct device *parent)
  uint32_t reg;
  int port, pin;
  int cfg, state;
- int i;
+ int i, off;
 
  for (i = 0; i < sc->sc_npins; i++) {
  /* Skip pins that have no gpio function. */
@@ -459,7 +459,8 @@ sxipio_attach_gpio(struct device *parent)
 
  /* Get pin configuration. */
  reg = SXIREAD4(sc, SXIPIO_CFG(port, pin));
- cfg = (reg >> (pin & 0x7)) & 0x7;
+ off = (pin & 0x7) << 2;
+ cfg = (reg >> off) & 0x7;
 
  /* Skip pins that have been assigned other functions. */
  if (cfg != SXIPIO_GPIO_IN && cfg != SXIPIO_GPIO_OUT)


just figured how the output below does ie. miss some supposed to be i2c-pins.

-Artturi

>
> > > A0 mux 5<gmac>- skipping
> > > A1 mux 2<emac>- skipping
> > > A2 mux 5<gmac>- skipping
> > > A3 mux 2<emac>- skipping
> > > A4 mux 5<gmac>- skipping
> > > A5 mux 2<emac>- skipping
> > > A6 mux 5<gmac>- skipping
> > > A7 mux 2<emac>- skipping
> > > A8 mux 5<gmac>- skipping
> > > A9 mux 2<emac>- skipping
> > > A10 mux 5<gmac>- skipping
> > > A11 mux 2<emac>- skipping
> > > A12 mux 5<gmac>- skipping
> > > A13 mux 2<emac>- skipping
> > > A14 mux 5<gmac>- skipping
> > > A15 mux 2<emac>- skipping
> > > A16 mux 5<gmac>- skipping
> > > A17 mux 2<emac>- skipping
> > > B0 mux 2<i2c0>- skipping
> > > B1 mux 1<gpio_out>- adding
> > > B2 mux 0<gpio_in>- adding
> > > B3 mux 4<spdif>- skipping
> > > B4 mux 2<ir0>- skipping
> > > B5 mux 1<gpio_out>- adding
> > > B6 mux 0<gpio_in>- adding
> > > B7 mux 0<gpio_in>- adding
> > > B8 mux 1<gpio_out>- adding
> > > B9 mux 0<gpio_in>- adding
> > > B10 mux 0<gpio_in>- adding
> > > B11 mux 0<gpio_in>- adding
> > > B12 mux 0<gpio_in>- adding
> > > B13 mux 0<gpio_in>- adding
> > > B14 mux 0<gpio_in>- adding
> > > B15 mux 0<gpio_in>- adding
> > > B16 mux 0<gpio_in>- adding
> > > B17 mux 0<gpio_in>- adding
> > > B18 mux 0<gpio_in>- adding
> > > B19 mux 0<gpio_in>- adding
> > > B20 mux 0<gpio_in>- adding
> > > B21 mux 0<gpio_in>- adding
> > > B22 mux 0<gpio_in>- adding
> > > B23 mux 4<invalid>- skipping
> > > C0 mux 0<gpio_in>- adding
> > > C1 mux 0<gpio_in>- adding
> > > C2 mux 0<gpio_in>- adding
> > > C3 mux 0<gpio_in>- adding
> > > C4 mux 0<gpio_in>- adding
> > > C5 mux 0<gpio_in>- adding
> > > C6 mux 0<gpio_in>- adding
> > > C7 mux 0<gpio_in>- adding
> > > C8 mux 0<gpio_in>- adding
> > > C9 mux 0<gpio_in>- adding
> > > C10 mux 0<gpio_in>- adding
> > > C11 mux 0<gpio_in>- adding
> > > C12 mux 0<gpio_in>- adding
> > > C13 mux 0<gpio_in>- adding
> > > C14 mux 0<gpio_in>- adding
> > > C15 mux 0<gpio_in>- adding
> > > C16 mux 0<gpio_in>- adding
> > > C17 mux 0<gpio_in>- adding
> > > C18 mux 0<gpio_in>- adding
> > > C19 mux 0<gpio_in>- adding
> > > C20 mux 0<gpio_in>- adding
> > > C21 mux 0<gpio_in>- adding
> > > C22 mux 0<gpio_in>- adding
> > > C23 mux 0<gpio_in>- adding
> > > C24 mux 0<gpio_in>- adding
> > > D0 mux 0<gpio_in>- adding
> > > D1 mux 0<gpio_in>- adding
> > > D2 mux 0<gpio_in>- adding
> > > D3 mux 0<gpio_in>- adding
> > > D4 mux 0<gpio_in>- adding
> > > D5 mux 0<gpio_in>- adding
> > > D6 mux 0<gpio_in>- adding
> > > D7 mux 0<gpio_in>- adding
> > > D8 mux 0<gpio_in>- adding
> > > D9 mux 0<gpio_in>- adding
> > > D10 mux 0<gpio_in>- adding
> > > D11 mux 0<gpio_in>- adding
> > > D12 mux 0<gpio_in>- adding
> > > D13 mux 0<gpio_in>- adding
> > > D14 mux 0<gpio_in>- adding
> > > D15 mux 0<gpio_in>- adding
> > > D16 mux 0<gpio_in>- adding
> > > D17 mux 0<gpio_in>- adding
> > > D18 mux 0<gpio_in>- adding
> > > D19 mux 0<gpio_in>- adding
> > > D20 mux 0<gpio_in>- adding
> > > D21 mux 0<gpio_in>- adding
> > > D22 mux 0<gpio_in>- adding
> > > D23 mux 0<gpio_in>- adding
> > > D24 mux 0<gpio_in>- adding
> > > D25 mux 0<gpio_in>- adding
> > > D26 mux 0<gpio_in>- adding
> > > D27 mux 0<gpio_in>- adding
> > > E0 mux 0<gpio_in>- adding
> > > E1 mux 0<gpio_in>- adding
> > > E2 mux 0<gpio_in>- adding
> > > E3 mux 0<gpio_in>- adding
> > > E4 mux 0<gpio_in>- adding
> > > E5 mux 0<gpio_in>- adding
> > > E6 mux 0<gpio_in>- adding
> > > E7 mux 0<gpio_in>- adding
> > > E8 mux 0<gpio_in>- adding
> > > E9 mux 0<gpio_in>- adding
> > > E10 mux 0<gpio_in>- adding
> > > E11 mux 0<gpio_in>- adding
> > > F0 mux 2<mmc0>- skipping
> > > F1 mux 1<gpio_out>- adding
> > > F2 mux 0<gpio_in>- adding
> > > F3 mux 4<jtag>- skipping
> > > F4 mux 2<mmc0>- skipping
> > > F5 mux 1<gpio_out>- adding
> > > G0 mux 0<gpio_in>- adding
> > > G1 mux 0<gpio_in>- adding
> > > G2 mux 0<gpio_in>- adding
> > > G3 mux 0<gpio_in>- adding
> > > G4 mux 0<gpio_in>- adding
> > > G5 mux 0<gpio_in>- adding
> > > G6 mux 0<gpio_in>- adding
> > > G7 mux 0<gpio_in>- adding
> > > G8 mux 0<gpio_in>- adding
> > > G9 mux 0<gpio_in>- adding
> > > G10 mux 0<gpio_in>- adding
> > > G11 mux 0<gpio_in>- adding
> > > H0 mux 0<gpio_in>- adding
> > > H1 mux 0<gpio_in>- adding
> > > H2 mux 0<gpio_in>- adding
> > > H3 mux 0<gpio_in>- adding
> > > H4 mux 0<gpio_in>- adding
> > > H5 mux 0<gpio_in>- adding
> > > H6 mux 0<gpio_in>- adding
> > > H7 mux 0<gpio_in>- adding
> > > H8 mux 0<gpio_in>- adding
> > > H9 mux 0<gpio_in>- adding
> > > H10 mux 0<gpio_in>- adding
> > > H11 mux 0<gpio_in>- adding
> > > H12 mux 0<gpio_in>- adding
> > > H13 mux 0<gpio_in>- adding
> > > H14 mux 0<gpio_in>- adding
> > > H15 mux 0<gpio_in>- adding
> > > H16 mux 0<gpio_in>- adding
> > > H17 mux 0<gpio_in>- adding
> > > H18 mux 0<gpio_in>- adding
> > > H19 mux 0<gpio_in>- adding
> > > H20 mux 0<gpio_in>- adding
> > > H21 mux 0<gpio_in>- adding
> > > H22 mux 0<gpio_in>- adding
> > > H23 mux 0<gpio_in>- adding
> > > H24 mux 0<gpio_in>- adding
> > > H25 mux 0<gpio_in>- adding
> > > H26 mux 0<gpio_in>- adding
> > > H27 mux 0<gpio_in>- adding
> > > I0 mux 0<gpio_in>- adding
> > > I1 mux 0<gpio_in>- adding
> > > I2 mux 0<gpio_in>- adding
> > > I3 mux 0<gpio_in>- adding
> > > I4 mux 0<gpio_in>- adding
> > > I5 mux 0<gpio_in>- adding
> > > I6 mux 0<gpio_in>- adding
> > > I7 mux 0<gpio_in>- adding
> > > I8 mux 0<gpio_in>- adding
> > > I9 mux 0<gpio_in>- adding
> > > I10 mux 0<gpio_in>- adding
> > > I11 mux 0<gpio_in>- adding
> > > I12 mux 0<gpio_in>- adding
> > > I13 mux 0<gpio_in>- adding
> > > I14 mux 0<gpio_in>- adding
> > > I15 mux 0<gpio_in>- adding
> > > I16 mux 0<gpio_in>- adding
> > > I17 mux 0<gpio_in>- adding
> > > I18 mux 0<gpio_in>- adding
> > > I19 mux 0<gpio_in>- adding
> > > I20 mux 0<gpio_in>- adding
> > > I21 mux 0<gpio_in>- adding
> >
> > which allows us to see how the pins are configured and whether they're
> > made available.

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Re: looking for help on gpio setup on orange pi one

Stephen Graf
In reply to this post by Artturi Alm
I tied your suggested change with the following results.
Not yet what I am thinking is correct.


U-Boot SPL 2017.09-rc2 (Aug 22 2017 - 00:26:16)
DRAM: 512 MiB
Trying to boot from MMC1


U-Boot 2017.09-rc2 (Aug 22 2017 - 00:26:16 -0600) Allwinner Technology

CPU:   Allwinner H3 (SUN8I 1680)
Model: Xunlong Orange Pi One
DRAM:  512 MiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   phy interface0
eth0: ethernet@1c30000
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
scanning bus 0 for devices... 2 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
reading /sun8i-h3-orangepi-one.dtb
14504 bytes read in 25 ms (566.4 KiB/s)
Found EFI removable media binary efi/boot/bootarm.efi
reading efi/boot/bootarm.efi
67356 bytes read in 36 ms (1.8 MiB/s)
## Starting EFI application at 42000000 ...
Scanning disks on usb...
Scanning disks on mmc...
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Found 5 disks
>> OpenBSD/armv7 BOOTARM 1.0
boot>
booting sd0a:/bsd: 3905464+165912+498860 [281342+90+518560+243869]=0x561424

OpenBSD/armv7 booting ...
arg0 0xc0861424 arg1 0x0 arg2 0x48000000
Allocating page tables
freestart = 0x40862000, free_pages = 128926 (0x0001f79e)
IRQ stack: p0x40890000 v0xc0890000
ABT stack: p0x40891000 v0xc0891000
UND stack: p0x40892000 v0xc0892000
SVC stack: p0x40893000 v0xc0893000
Creating L1 page table at 0x40864000
Mapping kernel
Constructing L2 page tables
undefined page pmap [ using 1044320 bytes of bsd ELF symbol table ]
board type: 0
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2017 OpenBSD. All rights reserved.
https://www.OpenBSD.org

OpenBSD 6.2-beta (GENERIC) #3: Mon Aug 28 10:18:41 PDT 2017
    [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
real mem  = 536870912 (512MB)
avail mem = 517378048 (493MB)
mainbus0 at root: Xunlong Orange Pi One
cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
cortex0 at mainbus0
sxiccmu0 at mainbus0
psci0 at mainbus0
simplebus0 at mainbus0: "soc"
sxiccmu1 at simplebus0
sxipio0 at simplebus0: 94 pins
sxipio1 at simplebus0: 12 pins
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
ehci0 at simplebus0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev
2.00/1.00 addr 1
ehci1 at simplebus0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev
2.00/1.00 addr 1
sxidog0 at simplebus0
com0 at simplebus0: ns16550, no working fifo
com0: console
ampintc0 at simplebus0 nirq 160, ncpu 4
sxirtc0 at simplebus0
A0 mux 7<invalid>- skipping
A1 mux 7<invalid>- skipping
A2 mux 7<invalid>- skipping
A3 mux 7<invalid>- skipping
A4 mux 2<uart0>- skipping
A5 mux 2<uart0>- skipping
A6 mux 7<invalid>- skipping
A7 mux 7<invalid>- skipping
A8 mux 7<invalid>- skipping
A9 mux 7<invalid>- skipping
A10 mux 7<invalid>- skipping
A11 mux 7<invalid>- skipping
A12 mux 7<invalid>- skipping
A13 mux 7<invalid>- skipping
A14 mux 7<invalid>- skipping
A15 mux 7<invalid>- skipping
A16 mux 7<invalid>- skipping
A17 mux 7<invalid>- skipping
A18 mux 7<invalid>- skipping
A19 mux 7<invalid>- skipping
A20 mux 7<invalid>- skipping
A21 mux 7<invalid>- skipping
C0 mux 7<invalid>- skipping
C1 mux 7<invalid>- skipping
C2 mux 7<invalid>- skipping
C3 mux 7<invalid>- skipping
C4 mux 7<invalid>- skipping
C5 mux 7<invalid>- skipping
C6 mux 7<invalid>- skipping
C7 mux 7<invalid>- skipping
C8 mux 7<invalid>- skipping
C9 mux 7<invalid>- skipping
C10 mux 7<invalid>- skipping
C11 mux 7<invalid>- skipping
C12 mux 7<invalid>- skipping
C13 mux 7<invalid>- skipping
C14 mux 7<invalid>- skipping
C15 mux 7<invalid>- skipping
C16 mux 7<invalid>- skipping
D0 mux 7<invalid>- skipping
D1 mux 7<invalid>- skipping
D2 mux 7<invalid>- skipping
D3 mux 7<invalid>- skipping
D4 mux 7<invalid>- skipping
D5 mux 7<invalid>- skipping
D6 mux 7<invalid>- skipping
D7 mux 7<invalid>- skipping
D8 mux 7<invalid>- skipping
D9 mux 7<invalid>- skipping
D10 mux 7<invalid>- skipping
D11 mux 7<invalid>- skipping
D12 mux 7<invalid>- skipping
D13 mux 7<invalid>- skipping
D14 mux 7<invalid>- skipping
D15 mux 7<invalid>- skipping
D16 mux 7<invalid>- skipping
D17 mux 7<invalid>- skipping
E0 mux 7<invalid>- skipping
E1 mux 7<invalid>- skipping
E2 mux 7<invalid>- skipping
E3 mux 7<invalid>- skipping
E4 mux 7<invalid>- skipping
E5 mux 7<invalid>- skipping
E6 mux 7<invalid>- skipping
E7 mux 7<invalid>- skipping
E8 mux 7<invalid>- skipping
E9 mux 7<invalid>- skipping
E10 mux 7<invalid>- skipping
E11 mux 7<invalid>- skipping
E12 mux 7<invalid>- skipping
E13 mux 7<invalid>- skipping
E14 mux 7<invalid>- skipping
E15 mux 7<invalid>- skipping
F0 mux 2<mmc0>- skipping
F1 mux 2<mmc0>- skipping
F2 mux 2<mmc0>- skipping
F3 mux 2<mmc0>- skipping
F4 mux 2<mmc0>- skipping
F5 mux 2<mmc0>- skipping
F6 mux 0<gpio_in>- adding
G0 mux 7<invalid>- skipping
G1 mux 7<invalid>- skipping
G2 mux 7<invalid>- skipping
G3 mux 7<invalid>- skipping
G4 mux 7<invalid>- skipping
G5 mux 7<invalid>- skipping
G6 mux 7<invalid>- skipping
G7 mux 7<invalid>- skipping
G8 mux 7<invalid>- skipping
G9 mux 7<invalid>- skipping
G10 mux 7<invalid>- skipping
G11 mux 7<invalid>- skipping
G12 mux 7<invalid>- skipping
G13 mux 7<invalid>- skipping
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
A0 mux 7<invalid>- skipping
A1 mux 7<invalid>- skipping
A2 mux 7<invalid>- skipping
A3 mux 7<invalid>- skipping
A4 mux 7<invalid>- skipping
A5 mux 7<invalid>- skipping
A6 mux 7<invalid>- skipping
A7 mux 7<invalid>- skipping
A8 mux 7<invalid>- skipping
A9 mux 7<invalid>- skipping
A10 mux 7<invalid>- skipping
A11 mux 7<invalid>- skipping
gpio7 at sxipio1: 32 pins
agtimer0 at mainbus0: tick rate 24000 KHz
scsibus0 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SL16G, 0080> SCSI2 0/direct removable
sd0: 15193MB, 512 bytes/sector, 31116288 sectors
run0 at uhub1 port 1 configuration 1 interface 0 "Ralink 802.11 n WLAN" rev
2.00/1.01 addr 2
run0: MAC/BBP RT3070 (rev 0x0201), RF RT3020 (MIMO 1T1R), address
00:1f:cf:52:86:52
vscsi0 at root
scsibus1 at vscsi0: 256 targets
softraid0 at root
scsibus2 at softraid0: 256 targets
boot device: sd0
root on sd0a (e50fea1f8609b974.a) swap on sd0b dump on sd0b
Automatic boot in progress: starting file system checks.
/dev/sd0a (e50fea1f8609b974.a): file system is clean; not checking
/dev/sd0l (e50fea1f8609b974.l): file system is clean; not checking
/dev/sd0d (e50fea1f8609b974.d): file system is clean; not checking
/dev/sd0f (e50fea1f8609b974.f): file system is clean; not checking
/dev/sd0g (e50fea1f8609b974.g): file system is clean; not checking
/dev/sd0h (e50fea1f8609b974.h): file system is clean; not checking
/dev/sd0k (e50fea1f8609b974.k): file system is clean; not checking
/dev/sd0j (e50fea1f8609b974.j): file system is clean; not checking
/dev/sd0e (e50fea1f8609b974.e): file system is clean; not checking
setting tty flags
pf enabled
starting network
DHCPREQUEST on run0 to 255.255.255.255
DHCPACK from 192.168.1.253 (cc:5d:4e:ad:f4:0f)
bound to 192.168.1.6 -- renewal in 43200 seconds.
reordering libraries: done.
starting early daemons: syslogd pflogd ntpd.
starting RPC daemons:.
savecore: no core dump
checking quotas: done.
clearing /tmp
kern.securelevel: 0 -> 1
creating runtime link editor directory cache.
preserving editor files.
starting network daemons: sshd smtpd sndiod.
starting local daemons: cron.
Mon Aug 28 10:26:12 PDT 2017

OpenBSD/armv7 (openbsdop1.graf.lan) (console)

login:

-----Original Message-----
From: [hidden email] [mailto:[hidden email]] On Behalf Of
Artturi Alm
Sent: Monday, August 28, 2017 7:09 AM
To: Mark Kettenis <[hidden email]>
Cc: [hidden email]
Subject: Re: looking for help on gpio setup on orange pi one

On Mon, Aug 28, 2017 at 09:32:04AM +0300, Artturi Alm wrote:
> On Sat, Aug 26, 2017 at 09:29:31PM +0200, Mark Kettenis wrote:
> > > From: "Stephen Graf" <[hidden email]>
> > > Date: Sat, 26 Aug 2017 11:58:58 -0700
> > >
> > > Thank you again for your suggestions. I tried to follow your
> > > example but it did not work out as expected.
> > > For some reason the gpioctl set command is not working at secure
> > > level 0 and without that it is impossible to do anything with the
device later.

> >
> > You should run the diff that Artturi send in an early mail.  That
> > produces output like:
> >
>
> i'm almost overtired atm., but after comparing datasheets i decided to
> take a quick look at sxipio again, and stumbled upon these shifts.
>
> sxipio_config_pin:
> 337         mux = (config & GPIO_CONFIG_OUTPUT) ? 1 : 0;
> 338         off = (pin & 0x7) << 2;
> 339         SXICMS4(sc, SXIPIO_CFG(port, pin), 0x7 << off, mux << off);
>
> sxipio_attach_gpio:
> 460                 /* Get pin configuration. */
> 461                 reg = SXIREAD4(sc, SXIPIO_CFG(port, pin));
> 462                 cfg = (reg >> (pin & 0x7)) & 0x7;
>
> 1:1?
> -Artturi
>

So, i was thinking something like this (untested):

diff --git a/sys/dev/fdt/sxipio.c b/sys/dev/fdt/sxipio.c index
643226ecd19..9de710ffd5c 100644
--- a/sys/dev/fdt/sxipio.c
+++ b/sys/dev/fdt/sxipio.c
@@ -446,7 +446,7 @@ sxipio_attach_gpio(struct device *parent)
  uint32_t reg;
  int port, pin;
  int cfg, state;
- int i;
+ int i, off;
 
  for (i = 0; i < sc->sc_npins; i++) {
  /* Skip pins that have no gpio function. */ @@ -459,7 +459,8
@@ sxipio_attach_gpio(struct device *parent)
 
  /* Get pin configuration. */
  reg = SXIREAD4(sc, SXIPIO_CFG(port, pin));
- cfg = (reg >> (pin & 0x7)) & 0x7;
+ off = (pin & 0x7) << 2;
+ cfg = (reg >> off) & 0x7;
 
  /* Skip pins that have been assigned other functions. */
  if (cfg != SXIPIO_GPIO_IN && cfg != SXIPIO_GPIO_OUT)


just figured how the output below does ie. miss some supposed to be
i2c-pins.

-Artturi

>
> > > A0 mux 5<gmac>- skipping
> > > A1 mux 2<emac>- skipping
> > > A2 mux 5<gmac>- skipping
> > > A3 mux 2<emac>- skipping
> > > A4 mux 5<gmac>- skipping
> > > A5 mux 2<emac>- skipping
> > > A6 mux 5<gmac>- skipping
> > > A7 mux 2<emac>- skipping
> > > A8 mux 5<gmac>- skipping
> > > A9 mux 2<emac>- skipping
> > > A10 mux 5<gmac>- skipping
> > > A11 mux 2<emac>- skipping
> > > A12 mux 5<gmac>- skipping
> > > A13 mux 2<emac>- skipping
> > > A14 mux 5<gmac>- skipping
> > > A15 mux 2<emac>- skipping
> > > A16 mux 5<gmac>- skipping
> > > A17 mux 2<emac>- skipping
> > > B0 mux 2<i2c0>- skipping
> > > B1 mux 1<gpio_out>- adding
> > > B2 mux 0<gpio_in>- adding
> > > B3 mux 4<spdif>- skipping
> > > B4 mux 2<ir0>- skipping
> > > B5 mux 1<gpio_out>- adding
> > > B6 mux 0<gpio_in>- adding
> > > B7 mux 0<gpio_in>- adding
> > > B8 mux 1<gpio_out>- adding
> > > B9 mux 0<gpio_in>- adding
> > > B10 mux 0<gpio_in>- adding
> > > B11 mux 0<gpio_in>- adding
> > > B12 mux 0<gpio_in>- adding
> > > B13 mux 0<gpio_in>- adding
> > > B14 mux 0<gpio_in>- adding
> > > B15 mux 0<gpio_in>- adding
> > > B16 mux 0<gpio_in>- adding
> > > B17 mux 0<gpio_in>- adding
> > > B18 mux 0<gpio_in>- adding
> > > B19 mux 0<gpio_in>- adding
> > > B20 mux 0<gpio_in>- adding
> > > B21 mux 0<gpio_in>- adding
> > > B22 mux 0<gpio_in>- adding
> > > B23 mux 4<invalid>- skipping
> > > C0 mux 0<gpio_in>- adding
> > > C1 mux 0<gpio_in>- adding
> > > C2 mux 0<gpio_in>- adding
> > > C3 mux 0<gpio_in>- adding
> > > C4 mux 0<gpio_in>- adding
> > > C5 mux 0<gpio_in>- adding
> > > C6 mux 0<gpio_in>- adding
> > > C7 mux 0<gpio_in>- adding
> > > C8 mux 0<gpio_in>- adding
> > > C9 mux 0<gpio_in>- adding
> > > C10 mux 0<gpio_in>- adding
> > > C11 mux 0<gpio_in>- adding
> > > C12 mux 0<gpio_in>- adding
> > > C13 mux 0<gpio_in>- adding
> > > C14 mux 0<gpio_in>- adding
> > > C15 mux 0<gpio_in>- adding
> > > C16 mux 0<gpio_in>- adding
> > > C17 mux 0<gpio_in>- adding
> > > C18 mux 0<gpio_in>- adding
> > > C19 mux 0<gpio_in>- adding
> > > C20 mux 0<gpio_in>- adding
> > > C21 mux 0<gpio_in>- adding
> > > C22 mux 0<gpio_in>- adding
> > > C23 mux 0<gpio_in>- adding
> > > C24 mux 0<gpio_in>- adding
> > > D0 mux 0<gpio_in>- adding
> > > D1 mux 0<gpio_in>- adding
> > > D2 mux 0<gpio_in>- adding
> > > D3 mux 0<gpio_in>- adding
> > > D4 mux 0<gpio_in>- adding
> > > D5 mux 0<gpio_in>- adding
> > > D6 mux 0<gpio_in>- adding
> > > D7 mux 0<gpio_in>- adding
> > > D8 mux 0<gpio_in>- adding
> > > D9 mux 0<gpio_in>- adding
> > > D10 mux 0<gpio_in>- adding
> > > D11 mux 0<gpio_in>- adding
> > > D12 mux 0<gpio_in>- adding
> > > D13 mux 0<gpio_in>- adding
> > > D14 mux 0<gpio_in>- adding
> > > D15 mux 0<gpio_in>- adding
> > > D16 mux 0<gpio_in>- adding
> > > D17 mux 0<gpio_in>- adding
> > > D18 mux 0<gpio_in>- adding
> > > D19 mux 0<gpio_in>- adding
> > > D20 mux 0<gpio_in>- adding
> > > D21 mux 0<gpio_in>- adding
> > > D22 mux 0<gpio_in>- adding
> > > D23 mux 0<gpio_in>- adding
> > > D24 mux 0<gpio_in>- adding
> > > D25 mux 0<gpio_in>- adding
> > > D26 mux 0<gpio_in>- adding
> > > D27 mux 0<gpio_in>- adding
> > > E0 mux 0<gpio_in>- adding
> > > E1 mux 0<gpio_in>- adding
> > > E2 mux 0<gpio_in>- adding
> > > E3 mux 0<gpio_in>- adding
> > > E4 mux 0<gpio_in>- adding
> > > E5 mux 0<gpio_in>- adding
> > > E6 mux 0<gpio_in>- adding
> > > E7 mux 0<gpio_in>- adding
> > > E8 mux 0<gpio_in>- adding
> > > E9 mux 0<gpio_in>- adding
> > > E10 mux 0<gpio_in>- adding
> > > E11 mux 0<gpio_in>- adding
> > > F0 mux 2<mmc0>- skipping
> > > F1 mux 1<gpio_out>- adding
> > > F2 mux 0<gpio_in>- adding
> > > F3 mux 4<jtag>- skipping
> > > F4 mux 2<mmc0>- skipping
> > > F5 mux 1<gpio_out>- adding
> > > G0 mux 0<gpio_in>- adding
> > > G1 mux 0<gpio_in>- adding
> > > G2 mux 0<gpio_in>- adding
> > > G3 mux 0<gpio_in>- adding
> > > G4 mux 0<gpio_in>- adding
> > > G5 mux 0<gpio_in>- adding
> > > G6 mux 0<gpio_in>- adding
> > > G7 mux 0<gpio_in>- adding
> > > G8 mux 0<gpio_in>- adding
> > > G9 mux 0<gpio_in>- adding
> > > G10 mux 0<gpio_in>- adding
> > > G11 mux 0<gpio_in>- adding
> > > H0 mux 0<gpio_in>- adding
> > > H1 mux 0<gpio_in>- adding
> > > H2 mux 0<gpio_in>- adding
> > > H3 mux 0<gpio_in>- adding
> > > H4 mux 0<gpio_in>- adding
> > > H5 mux 0<gpio_in>- adding
> > > H6 mux 0<gpio_in>- adding
> > > H7 mux 0<gpio_in>- adding
> > > H8 mux 0<gpio_in>- adding
> > > H9 mux 0<gpio_in>- adding
> > > H10 mux 0<gpio_in>- adding
> > > H11 mux 0<gpio_in>- adding
> > > H12 mux 0<gpio_in>- adding
> > > H13 mux 0<gpio_in>- adding
> > > H14 mux 0<gpio_in>- adding
> > > H15 mux 0<gpio_in>- adding
> > > H16 mux 0<gpio_in>- adding
> > > H17 mux 0<gpio_in>- adding
> > > H18 mux 0<gpio_in>- adding
> > > H19 mux 0<gpio_in>- adding
> > > H20 mux 0<gpio_in>- adding
> > > H21 mux 0<gpio_in>- adding
> > > H22 mux 0<gpio_in>- adding
> > > H23 mux 0<gpio_in>- adding
> > > H24 mux 0<gpio_in>- adding
> > > H25 mux 0<gpio_in>- adding
> > > H26 mux 0<gpio_in>- adding
> > > H27 mux 0<gpio_in>- adding
> > > I0 mux 0<gpio_in>- adding
> > > I1 mux 0<gpio_in>- adding
> > > I2 mux 0<gpio_in>- adding
> > > I3 mux 0<gpio_in>- adding
> > > I4 mux 0<gpio_in>- adding
> > > I5 mux 0<gpio_in>- adding
> > > I6 mux 0<gpio_in>- adding
> > > I7 mux 0<gpio_in>- adding
> > > I8 mux 0<gpio_in>- adding
> > > I9 mux 0<gpio_in>- adding
> > > I10 mux 0<gpio_in>- adding
> > > I11 mux 0<gpio_in>- adding
> > > I12 mux 0<gpio_in>- adding
> > > I13 mux 0<gpio_in>- adding
> > > I14 mux 0<gpio_in>- adding
> > > I15 mux 0<gpio_in>- adding
> > > I16 mux 0<gpio_in>- adding
> > > I17 mux 0<gpio_in>- adding
> > > I18 mux 0<gpio_in>- adding
> > > I19 mux 0<gpio_in>- adding
> > > I20 mux 0<gpio_in>- adding
> > > I21 mux 0<gpio_in>- adding
> >
> > which allows us to see how the pins are configured and whether
> > they're made available.


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Re: looking for help on gpio setup on orange pi one

Mark Kettenis
> From: "Stephen Graf" <[hidden email]>
> Date: Mon, 28 Aug 2017 10:30:51 -0700
>
> I tied your suggested change with the following results.
> Not yet what I am thinking is correct.

> sxirtc0 at simplebus0
> A0 mux 7<invalid>- skipping
> A1 mux 7<invalid>- skipping
> A2 mux 7<invalid>- skipping
> A3 mux 7<invalid>- skipping
> A4 mux 2<uart0>- skipping
> A5 mux 2<uart0>- skipping
> A6 mux 7<invalid>- skipping
> A7 mux 7<invalid>- skipping
> A8 mux 7<invalid>- skipping
> A9 mux 7<invalid>- skipping
> A10 mux 7<invalid>- skipping
> A11 mux 7<invalid>- skipping
> A12 mux 7<invalid>- skipping
> A13 mux 7<invalid>- skipping
> A14 mux 7<invalid>- skipping
> A15 mux 7<invalid>- skipping
> A16 mux 7<invalid>- skipping
> A17 mux 7<invalid>- skipping
> A18 mux 7<invalid>- skipping
> A19 mux 7<invalid>- skipping
> A20 mux 7<invalid>- skipping
> A21 mux 7<invalid>- skipping
> C0 mux 7<invalid>- skipping
> C1 mux 7<invalid>- skipping
> C2 mux 7<invalid>- skipping
> C3 mux 7<invalid>- skipping
> C4 mux 7<invalid>- skipping
> C5 mux 7<invalid>- skipping
> C6 mux 7<invalid>- skipping
> C7 mux 7<invalid>- skipping
> C8 mux 7<invalid>- skipping
> C9 mux 7<invalid>- skipping
> C10 mux 7<invalid>- skipping
> C11 mux 7<invalid>- skipping
> C12 mux 7<invalid>- skipping
> C13 mux 7<invalid>- skipping
> C14 mux 7<invalid>- skipping
> C15 mux 7<invalid>- skipping
> C16 mux 7<invalid>- skipping
> D0 mux 7<invalid>- skipping
> D1 mux 7<invalid>- skipping
> D2 mux 7<invalid>- skipping
> D3 mux 7<invalid>- skipping
> D4 mux 7<invalid>- skipping
> D5 mux 7<invalid>- skipping
> D6 mux 7<invalid>- skipping
> D7 mux 7<invalid>- skipping
> D8 mux 7<invalid>- skipping
> D9 mux 7<invalid>- skipping
> D10 mux 7<invalid>- skipping
> D11 mux 7<invalid>- skipping
> D12 mux 7<invalid>- skipping
> D13 mux 7<invalid>- skipping
> D14 mux 7<invalid>- skipping
> D15 mux 7<invalid>- skipping
> D16 mux 7<invalid>- skipping
> D17 mux 7<invalid>- skipping
> E0 mux 7<invalid>- skipping
> E1 mux 7<invalid>- skipping
> E2 mux 7<invalid>- skipping
> E3 mux 7<invalid>- skipping
> E4 mux 7<invalid>- skipping
> E5 mux 7<invalid>- skipping
> E6 mux 7<invalid>- skipping
> E7 mux 7<invalid>- skipping
> E8 mux 7<invalid>- skipping
> E9 mux 7<invalid>- skipping
> E10 mux 7<invalid>- skipping
> E11 mux 7<invalid>- skipping
> E12 mux 7<invalid>- skipping
> E13 mux 7<invalid>- skipping
> E14 mux 7<invalid>- skipping
> E15 mux 7<invalid>- skipping
> F0 mux 2<mmc0>- skipping
> F1 mux 2<mmc0>- skipping
> F2 mux 2<mmc0>- skipping
> F3 mux 2<mmc0>- skipping
> F4 mux 2<mmc0>- skipping
> F5 mux 2<mmc0>- skipping
> F6 mux 0<gpio_in>- adding
> G0 mux 7<invalid>- skipping
> G1 mux 7<invalid>- skipping
> G2 mux 7<invalid>- skipping
> G3 mux 7<invalid>- skipping
> G4 mux 7<invalid>- skipping
> G5 mux 7<invalid>- skipping
> G6 mux 7<invalid>- skipping
> G7 mux 7<invalid>- skipping
> G8 mux 7<invalid>- skipping
> G9 mux 7<invalid>- skipping
> G10 mux 7<invalid>- skipping
> G11 mux 7<invalid>- skipping
> G12 mux 7<invalid>- skipping
> G13 mux 7<invalid>- skipping
> gpio0 at sxipio0: 32 pins
> gpio1 at sxipio0: 32 pins
> gpio2 at sxipio0: 32 pins
> gpio3 at sxipio0: 32 pins
> gpio4 at sxipio0: 32 pins
> gpio5 at sxipio0: 32 pins
> gpio6 at sxipio0: 32 pins
> A0 mux 7<invalid>- skipping
> A1 mux 7<invalid>- skipping
> A2 mux 7<invalid>- skipping
> A3 mux 7<invalid>- skipping
> A4 mux 7<invalid>- skipping
> A5 mux 7<invalid>- skipping
> A6 mux 7<invalid>- skipping
> A7 mux 7<invalid>- skipping
> A8 mux 7<invalid>- skipping
> A9 mux 7<invalid>- skipping
> A10 mux 7<invalid>- skipping
> A11 mux 7<invalid>- skipping
> gpio7 at sxipio1: 32 pins

Actually this starts to make sense.  If you look at page 316 and
further of the H3 data sheet:

  http://linux-sunxi.org/images/4/4b/Allwinner_H3_Datasheet_V1.2.pdf

you'll see that the pins most pins come up in state 7 "IO disable".  I
think we can allow configurtion of pins thet are left in this state
without too much risk.

I don't have much time to look into this right now myself.  But please
remind me in the 2nd half of september if nothing happens before then.