enhanced mode for Intel SATA

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enhanced mode for Intel SATA

Jonathan Gray
Here is a diff that is an updated version of expanded version... of
a diff from Ulrik Holmin.
 
To be able to use the maximum number of IDE/SATA disks on an ICH
system we have to make some channels native as there isn't enough
legacy I/O space/interrupts to go around.
 
In addition to the ICH datasheets Intel has specific
Programmer Reference Manual documents for ICH5 and ICH6 SATA
that go into some more detail.

While this still has the ICH6M case statement left in, ICH6M
is not currently wired up to use this chip map function.

I'd like to hear some testing reports from people on this.
 
Index: pciide.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/pciide.c,v
retrieving revision 1.230
diff -u -p -r1.230 pciide.c
--- pciide.c 28 Mar 2006 12:56:44 -0000 1.230
+++ pciide.c 29 Mar 2006 12:53:04 -0000
@@ -2159,6 +2159,7 @@ piixsata_chip_map(struct pciide_softc *s
  pcireg_t interface = PCI_INTERFACE(pa->pa_class);
  int channel;
  bus_size_t cmdsize, ctlsize;
+ u_int8_t reg;
 
  if (pciide_chipen(sc, pa) == 0)
  return;
@@ -2188,6 +2189,53 @@ piixsata_chip_map(struct pciide_softc *s
  sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
     WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA;
  sc->sc_wdcdev.set_modes = sata_setup_channel;
+
+ /*
+ * Put the SATA portion of controllers that don't operate in combined
+ * mode into native PCI modes so the maximum number of devices can be
+ * used.  Intel calls this "enhanced mode"
+ */
+ switch(sc->sc_pp->ide_product) {
+ /* ICH 5 */
+ case PCI_PRODUCT_INTEL_82801EB_SATA:
+ case PCI_PRODUCT_INTEL_82801ER_SATA:
+ case PCI_PRODUCT_INTEL_6300ESB_SATA:
+ case PCI_PRODUCT_INTEL_6300ESB_SATA2:
+ reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP);
+ if ((reg & ICH5_SATA_MAP_COMBINED) == 0) {
+ reg = pciide_pci_read(pa->pa_pc, pa->pa_tag,
+    ICH5_SATA_PI);
+ reg |= ICH5_SATA_PI_PRI_NATIVE |
+    ICH5_SATA_PI_SEC_NATIVE;
+ pciide_pci_write(pa->pa_pc, pa->pa_tag,
+    ICH5_SATA_PI, reg);
+ interface |= PCIIDE_INTERFACE_PCI(0) |
+    PCIIDE_INTERFACE_PCI(1);
+ }
+ break;
+ /* ICH 6 */
+ case PCI_PRODUCT_INTEL_82801FB_SATA:
+ case PCI_PRODUCT_INTEL_82801FR_SATA:
+ case PCI_PRODUCT_INTEL_82801FBM_SATA:
+ /* ICH 7 */
+ case PCI_PRODUCT_INTEL_82801GB_SATA_1:
+ case PCI_PRODUCT_INTEL_82801GB_SATA_3:
+ case PCI_PRODUCT_INTEL_82801GBM_SATA:
+ reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP) &
+    ICH6_SATA_MAP_CMB_MASK;
+ if (reg != ICH6_SATA_MAP_CMB_PRI &&
+    reg != ICH6_SATA_MAP_CMB_SEC) {
+ reg = pciide_pci_read(pa->pa_pc, pa->pa_tag,
+    ICH5_SATA_PI);
+ reg |= ICH5_SATA_PI_PRI_NATIVE |
+    ICH5_SATA_PI_SEC_NATIVE;
+ pciide_pci_write(pa->pa_pc, pa->pa_tag,
+    ICH5_SATA_PI, reg);
+ interface |= PCIIDE_INTERFACE_PCI(0) |
+    PCIIDE_INTERFACE_PCI(1);
+ }
+ break;
+ }
 
  for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
  cp = &sc->pciide_channels[channel];
Index: pciide_piix_reg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/pciide_piix_reg.h,v
retrieving revision 1.9
diff -u -p -r1.9 pciide_piix_reg.h
--- pciide_piix_reg.h 24 Sep 2004 07:38:38 -0000 1.9
+++ pciide_piix_reg.h 29 Mar 2006 12:53:04 -0000
@@ -128,11 +128,24 @@ static int8_t piix4_sct_udma[] = {0x00,
  */
 #define ICH5_SATA_MAP 0x90 /* Address Map Register */
 #define ICH5_SATA_MAP_MV_MASK 0x07 /* Map Value mask */
+#define ICH5_SATA_MAP_COMBINED 0x04 /* Combined mode */
+
+#define ICH5_SATA_PI 0x09 /* Program Interface register */
+#define ICH5_SATA_PI_PRI_NATIVE 0x01 /* Put Pri IDE channel in native mode */
+#define ICH5_SATA_PI_SEC_NATIVE 0x04 /* Put Sec IDE channel in native mode */
 
 #define ICH_SATA_PCS 0x92 /* Port Control and Status Register */
 #define ICH_SATA_PCS_P0E 0x01 /* Port 0 enabled */
 #define ICH_SATA_PCS_P1E 0x02 /* Port 1 enabled */
 #define ICH_SATA_PCS_P0P 0x10 /* Port 0 present */
 #define ICH_SATA_PCS_P1P 0x20 /* Port 1 present */
+
+/*
+ * ICH6/ICH7 SATA registers definitions
+ */
+#define ICH6_SATA_MAP_CMB_MASK 0x03 /* Combined mode bits */
+#define ICH6_SATA_MAP_CMB_PRI 0x01 /* Combined mode, IDE Primary */
+#define ICH6_SATA_MAP_CMB_SEC 0x02 /* Combined mode, IDE Secondary */
+
 
 #endif /* !_DEV_PCI_PCIIDE_PIIX_REG_H_ */