armv7: OpenBSD-current on Lichee Pi Zero (Allwinner V3s)

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armv7: OpenBSD-current on Lichee Pi Zero (Allwinner V3s)

SASANO Takayoshi
Hello,

Recently I bought Lichee Pi Zero board, it has Allwinner V3s.

I tried to run OpenBSD-current, some devices are recognized and
others are not recognized. Both bsd.rd and bsd didn't work
when attaching microSD/ramdisk.

I attach the log of bsd, built from recent source tree on pcDuino.
What can I do to debug?

----
CUIсSPL 2019.01 (Jan 27 2019 - 18:58:44 +0900)
DRAM: 64 MiB
Trying to boot from MMC1


U-Boot 2019.01 (Jan 27 2019 - 18:58:44 +0900) Allwinner Technology

CPU:   Allwinner V3s (SUN8I 1681)
Model: Lichee Pi Zero
DRAM:  64 MiB
MMC:   SUNXI SD/MMC: 0
Loading Environment from FAT... *** Warning - bad CRC, using default environment

In:    serial@01c28000
Out:   serial@01c28000
Err:   serial@01c28000
Net:   No ethernet found.
starting USB...
No controllers found
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
6610 bytes read in 3 ms (2.1 MiB/s)
Found EFI removable media binary efi/boot/bootarm.efi
Scanning disks on usb...
Disk usb0 not ready
Disk usb1 not ready
Disk usb2 not ready
Disk usb3 not ready
Scanning disks on mmc...
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Found 3 disks
89060 bytes read in 8 ms (10.6 MiB/s)
## Starting EFI application at 41000000 ...
>> OpenBSD/armv7 BOOTARM 1.1
boot> boot
cannot open sd0a:/etc/random.seed: No such file or directory
booting sd0a:/bsd: 4538696+682524+235396+561676 [300312+107+312800+276796]=0x698044

OpenBSD/armv7 booting ...
arg0 0xc0998044 arg1 0x0 arg2 0x42d49000
Allocating page tables
IRQ stack: p0x409c7000 v0xc09c7000
ABT stack: p0x409c8000 v0xc09c8000
UND stack: p0x409c9000 v0xc09c9000
SVC stack: p0x409ca000 v0xc09ca000
Creating L1 page table at 0x4099c000
Mapping kernel
Constructing L2 page tables
undefined page type 0x2 pa 0x40000000 va 0x40000000 pages 0x2000 attr 0x8
type 0x7 pa 0x42000000 va 0x40000000 pages 0x5e6 attr 0x8
type 0x2 pa 0x425e6000 va 0x425e6000 pages 0x74d attr 0x8
type 0x1 pa 0x42d33000 va 0x42d33000 pages 0x16 attr 0x8
type 0x6 pa 0x42d49000 va 0x42d49000 pages 0xa attr 0x8000000000000008
type 0x0 pa 0x42d53000 va 0x42d51000 pages 0x2 attr 0x8
type 0x6 pa 0x42d55000 va 0x42d55000 pages 0x1 attr 0x8000000000000008
type 0x0 pa 0x42d56000 va 0x42d51000 pages 0x1 attr 0x8
type 0x6 pa 0x42d57000 va 0x42d57000 pages 0x1 attr 0x8000000000000008
type 0x0 pa 0x42d58000 va 0x42d58000 pages 0x2 attr 0x8
type 0x2 pa 0x42d5a000 va 0x42d5a000 pages 0x1223 attr 0x8
type 0x5 pa 0x43f7d000 va 0x43f7d000 pages 0x1 attr 0x8000000000000008
type 0x2 pa 0x43f7e000 va 0x42d5a000 pages 0x82 attr 0x8
pmap [ using 890548 bytes of bsd ELF symbol table ]
board type: 0
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2019 OpenBSD. All rights reserved.  https://www.OpenBSD.org

OpenBSD 6.4-current (GENERIC) #5: Thu Jan 31 23:24:00 JST 2019
    [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
real mem  = 39739392 (37MB)
avail mem = 28778496 (27MB)
mainbus0 at root: Lichee Pi Zero
cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
cortex0 at mainbus0
psci0 at mainbus0: PSCI 0.0
agtimer0 at mainbus0: tick rate 24000 KHz
simplebus0 at mainbus0: "soc"
ampintc0 at simplebus0 nirq 160, ncpu 1: "interrupt-controller"
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
"usb" at simplebus0 not configured
"phy" at simplebus0 not configured
"clock" at simplebus0 not configured
sxirtc0 at simplebus0
"pinctrl" at simplebus0 not configured
"timer" at simplebus0 not configured
sxidog0 at simplebus0
com0 at simplebus0: ns16550, no working fifo
com0: console
"interrupt-controller" at simplebus0 not configured
vscsi0 at root
scsibus0 at vscsi0: 256 targets
softraid0 at root
scsibus1 at softraid0: 256 targets
bootfile: sd0a:/bsd
boot device: lookup sd0a:/bsd failed.
root device: <--- hang at here

--
SASANO Takayoshi (JG1UAA) <[hidden email]>

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Re: armv7: OpenBSD-current on Lichee Pi Zero (Allwinner V3s)

Jonathan Gray-11
On Thu, Jan 31, 2019 at 11:50:25PM +0900, SASANO Takayoshi wrote:

> Hello,
>
> Recently I bought Lichee Pi Zero board, it has Allwinner V3s.
>
> I tried to run OpenBSD-current, some devices are recognized and
> others are not recognized. Both bsd.rd and bsd didn't work
> when attaching microSD/ramdisk.
>
> I attach the log of bsd, built from recent source tree on pcDuino.
> What can I do to debug?

There is no support for v3s in sxiccmu(4) and sxipio(4).
There is no driver for mentor usb otg "allwinner,sun8i-h3-musb"

>
> ----
> CUI??SPL 2019.01 (Jan 27 2019 - 18:58:44 +0900)
> DRAM: 64 MiB
> Trying to boot from MMC1
>
>
> U-Boot 2019.01 (Jan 27 2019 - 18:58:44 +0900) Allwinner Technology
>
> CPU:   Allwinner V3s (SUN8I 1681)
> Model: Lichee Pi Zero
> DRAM:  64 MiB
> MMC:   SUNXI SD/MMC: 0
> Loading Environment from FAT... *** Warning - bad CRC, using default environment
>
> In:    serial@01c28000
> Out:   serial@01c28000
> Err:   serial@01c28000
> Net:   No ethernet found.
> starting USB...
> No controllers found
> Hit any key to stop autoboot:  0
> switch to partitions #0, OK
> mmc0 is current device
> Scanning mmc 0:1...
> 6610 bytes read in 3 ms (2.1 MiB/s)
> Found EFI removable media binary efi/boot/bootarm.efi
> Scanning disks on usb...
> Disk usb0 not ready
> Disk usb1 not ready
> Disk usb2 not ready
> Disk usb3 not ready
> Scanning disks on mmc...
> MMC Device 1 not found
> MMC Device 2 not found
> MMC Device 3 not found
> Found 3 disks
> 89060 bytes read in 8 ms (10.6 MiB/s)
> ## Starting EFI application at 41000000 ...
> >> OpenBSD/armv7 BOOTARM 1.1
> boot> boot
> cannot open sd0a:/etc/random.seed: No such file or directory
> booting sd0a:/bsd: 4538696+682524+235396+561676 [300312+107+312800+276796]=0x698044
>
> OpenBSD/armv7 booting ...
> arg0 0xc0998044 arg1 0x0 arg2 0x42d49000
> Allocating page tables
> IRQ stack: p0x409c7000 v0xc09c7000
> ABT stack: p0x409c8000 v0xc09c8000
> UND stack: p0x409c9000 v0xc09c9000
> SVC stack: p0x409ca000 v0xc09ca000
> Creating L1 page table at 0x4099c000
> Mapping kernel
> Constructing L2 page tables
> undefined page type 0x2 pa 0x40000000 va 0x40000000 pages 0x2000 attr 0x8
> type 0x7 pa 0x42000000 va 0x40000000 pages 0x5e6 attr 0x8
> type 0x2 pa 0x425e6000 va 0x425e6000 pages 0x74d attr 0x8
> type 0x1 pa 0x42d33000 va 0x42d33000 pages 0x16 attr 0x8
> type 0x6 pa 0x42d49000 va 0x42d49000 pages 0xa attr 0x8000000000000008
> type 0x0 pa 0x42d53000 va 0x42d51000 pages 0x2 attr 0x8
> type 0x6 pa 0x42d55000 va 0x42d55000 pages 0x1 attr 0x8000000000000008
> type 0x0 pa 0x42d56000 va 0x42d51000 pages 0x1 attr 0x8
> type 0x6 pa 0x42d57000 va 0x42d57000 pages 0x1 attr 0x8000000000000008
> type 0x0 pa 0x42d58000 va 0x42d58000 pages 0x2 attr 0x8
> type 0x2 pa 0x42d5a000 va 0x42d5a000 pages 0x1223 attr 0x8
> type 0x5 pa 0x43f7d000 va 0x43f7d000 pages 0x1 attr 0x8000000000000008
> type 0x2 pa 0x43f7e000 va 0x42d5a000 pages 0x82 attr 0x8
> pmap [ using 890548 bytes of bsd ELF symbol table ]
> board type: 0
> Copyright (c) 1982, 1986, 1989, 1991, 1993
>         The Regents of the University of California.  All rights reserved.
> Copyright (c) 1995-2019 OpenBSD. All rights reserved.  https://www.OpenBSD.org
>
> OpenBSD 6.4-current (GENERIC) #5: Thu Jan 31 23:24:00 JST 2019
>     [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
> real mem  = 39739392 (37MB)
> avail mem = 28778496 (27MB)
> mainbus0 at root: Lichee Pi Zero
> cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> cortex0 at mainbus0
> psci0 at mainbus0: PSCI 0.0
> agtimer0 at mainbus0: tick rate 24000 KHz
> simplebus0 at mainbus0: "soc"
> ampintc0 at simplebus0 nirq 160, ncpu 1: "interrupt-controller"
> sximmc0 at simplebus0
> sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
> "usb" at simplebus0 not configured
> "phy" at simplebus0 not configured
> "clock" at simplebus0 not configured
> sxirtc0 at simplebus0
> "pinctrl" at simplebus0 not configured
> "timer" at simplebus0 not configured
> sxidog0 at simplebus0
> com0 at simplebus0: ns16550, no working fifo
> com0: console
> "interrupt-controller" at simplebus0 not configured
> vscsi0 at root
> scsibus0 at vscsi0: 256 targets
> softraid0 at root
> scsibus1 at softraid0: 256 targets
> bootfile: sd0a:/bsd
> boot device: lookup sd0a:/bsd failed.
> root device: <--- hang at here
>
> --
> SASANO Takayoshi (JG1UAA) <[hidden email]>
>

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[wip] armv7: Lichee Pi Zero (Allwinner V3s) support

SASANO Takayoshi
Hi,

> There is no support for v3s in sxiccmu(4) and sxipio(4).
> There is no driver for mentor usb otg "allwinner,sun8i-h3-musb"

I added v3s support code to sxiccmu(4) and sxipio(4),
but hangs up at attaching root device.

In dmesg, no sd0 is shown after sdmmc0 so something wrong with SD card
handling I think.

Here is kernel boot message.

>> OpenBSD/armv7 BOOTARM 1.1
boot>
cannot open sd0a:/etc/random.seed: No such file or directory
booting sd0a:/bsd: 4524864+682536+243280+565156 [298192+120+312640+276802]=0x696424

OpenBSD/armv7 booting ...
arg0 0xc0996424 arg1 0x0 arg2 0x42d49000
Allocating page tables
IRQ stack: p0x409c5000 v0xc09c5000
ABT stack: p0x409c6000 v0xc09c6000
UND stack: p0x409c7000 v0xc09c7000
SVC stack: p0x409c8000 v0xc09c8000
Creating L1 page table at 0x40998000
Mapping kernel
Constructing L2 page tables
undefined page type 0x2 pa 0x40000000 va 0x40000000 pages 0x2000 attr 0x8
type 0x7 pa 0x42000000 va 0x40000000 pages 0x5f8 attr 0x8
type 0x2 pa 0x425f8000 va 0x425f8000 pages 0x73b attr 0x8
type 0x1 pa 0x42d33000 va 0x42d33000 pages 0x16 attr 0x8
type 0x6 pa 0x42d49000 va 0x42d49000 pages 0xa attr 0x8000000000000008
type 0x0 pa 0x42d53000 va 0x42d51000 pages 0x2 attr 0x8
type 0x6 pa 0x42d55000 va 0x42d55000 pages 0x1 attr 0x8000000000000008
type 0x0 pa 0x42d56000 va 0x42d51000 pages 0x1 attr 0x8
type 0x6 pa 0x42d57000 va 0x42d57000 pages 0x1 attr 0x8000000000000008
type 0x0 pa 0x42d58000 va 0x42d58000 pages 0x2 attr 0x8
type 0x2 pa 0x42d5a000 va 0x42d5a000 pages 0x1223 attr 0x8
type 0x5 pa 0x43f7d000 va 0x43f7d000 pages 0x1 attr 0x8000000000000008
type 0x2 pa 0x43f7e000 va 0x42d5a000 pages 0x82 attr 0x8
pmap [ using 888368 bytes of bsd ELF symbol table ]
board type: 0
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2019 OpenBSD. All rights reserved.  https://www.OpenBSD.org

OpenBSD 6.4-current (GENERIC) #1: Mon Feb  4 22:53:06 JST 2019
    [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
real mem  = 39813120 (37MB)
avail mem = 28860416 (27MB)
warning: no entropy supplied by boot loader
mainbus0 at root: Lichee Pi Zero
cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
cortex0 at mainbus0
psci0 at mainbus0: PSCI 0.0
sxiccmu0 at mainbus0
agtimer0 at mainbus0: tick rate 24000 KHz
simplebus0 at mainbus0: "soc"
sxiccmu1 at simplebus0
sxipio0 at simplebus0: 52 pins
ampintc0 at simplebus0 nirq 160, ncpu 1: "interrupt-controller"
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
"usb" at simplebus0 not configured
"phy" at simplebus0 not configured
"clock" at simplebus0 not configured
sxirtc0 at simplebus0
"pinctrl" at simplebus0 not configured
"timer" at simplebus0 not configured
sxidog0 at simplebus0
com0 at simplebus0: ns16550, no working fifo
com0: console
"interrupt-controller" at simplebus0 not configured
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
vscsi0 at root
scsibus0 at vscsi0: 256 targets
softraid0 at root
scsibus1 at softraid0: 256 targets
bootfile: sd0a:/bsd
boot device: lookup sd0a:/bsd failed.
root device: <-- (hang at here)

And I attach the diff.
How do I determine clock index of sxiccmu_clocks.h?

--
SASANO Takayoshi (JG1UAA) <[hidden email]>

Index: sxiccmu.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
retrieving revision 1.21
diff -u -r1.21 sxiccmu.c
--- sxiccmu.c 3 Aug 2018 21:28:28 -0000 1.21
+++ sxiccmu.c 4 Feb 2019 13:47:35 -0000
@@ -103,6 +103,8 @@
 uint32_t sxiccmu_h3_r_get_frequency(struct sxiccmu_softc *, uint32_t);
 uint32_t sxiccmu_r40_get_frequency(struct sxiccmu_softc *, uint32_t);
 int sxiccmu_r40_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
+int sxiccmu_v3s_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
+uint32_t sxiccmu_v3s_get_frequency(struct sxiccmu_softc *, uint32_t);
 uint32_t sxiccmu_nop_get_frequency(struct sxiccmu_softc *, uint32_t);
 int sxiccmu_nop_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
 
@@ -122,6 +124,7 @@
     OF_is_compatible(node, "allwinner,sun8i-a23") ||
     OF_is_compatible(node, "allwinner,sun8i-a33") ||
     OF_is_compatible(node, "allwinner,sun8i-h3") ||
+    OF_is_compatible(node, "allwinner,sun8i-v3s") ||
     OF_is_compatible(node, "allwinner,sun9i-a80") ||
     OF_is_compatible(node, "allwinner,sun50i-a64") ||
     OF_is_compatible(node, "allwinner,sun50i-h5"));
@@ -135,6 +138,7 @@
     OF_is_compatible(node, "allwinner,sun8i-h3-ccu") ||
     OF_is_compatible(node, "allwinner,sun8i-h3-r-ccu") ||
     OF_is_compatible(node, "allwinner,sun8i-r40-ccu") ||
+    OF_is_compatible(node, "allwinner,sun8i-v3s-ccu") ||
     OF_is_compatible(node, "allwinner,sun9i-a80-ccu") ||
     OF_is_compatible(node, "allwinner,sun9i-a80-usb-clks") ||
     OF_is_compatible(node, "allwinner,sun9i-a80-mmc-config-clk") ||
@@ -211,6 +215,14 @@
  sc->sc_nresets = nitems(sun8i_r40_resets);
  sc->sc_get_frequency = sxiccmu_r40_get_frequency;
  sc->sc_set_frequency = sxiccmu_r40_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun8i-v3s-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun8i_v3s_gates;
+ sc->sc_ngates = nitems(sun8i_v3s_gates);
+ sc->sc_resets = sun8i_v3s_resets;
+ sc->sc_nresets = nitems(sun8i_v3s_resets);
+ sc->sc_get_frequency = sxiccmu_v3s_get_frequency;
+ sc->sc_set_frequency = sxiccmu_v3s_set_frequency;
  } else if (OF_is_compatible(node, "allwinner,sun9i-a80-ccu")) {
  KASSERT(faa->fa_nreg > 0);
  sc->sc_gates = sun9i_a80_gates;
@@ -1233,6 +1245,65 @@
 }
 
 uint32_t
+sxiccmu_v3s_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+ uint32_t parent;
+ uint32_t reg, div;
+
+ switch (idx) {
+ case V3S_CLK_LOSC:
+ return clock_get_frequency(sc->sc_node, "losc");
+ case V3S_CLK_HOSC:
+ return clock_get_frequency(sc->sc_node, "hosc");
+ case V3S_CLK_PLL_PERIPH0:
+ /* Not hardcoded, but recommended. */
+ return 600000000;
+ case V3S_CLK_APB2:
+ /* XXX Controlled by a MUX. */
+ return 24000000;
+ case V3S_CLK_AHB1:
+ reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
+ div = CCU_AHB1_CLK_DIV_RATIO(reg);
+ switch (reg & CCU_AHB1_CLK_SRC_SEL) {
+ case CCU_AHB1_CLK_SRC_SEL_LOSC:
+ parent = V3S_CLK_LOSC;
+ break;
+ case CCU_AHB1_CLK_SRC_SEL_OSC24M:
+ parent = V3S_CLK_HOSC;
+ break;
+ case CCU_AHB1_CLK_SRC_SEL_AXI:
+ parent = V3S_CLK_AXI;
+ break;
+ case CCU_AHB1_CLK_SRC_SEL_PERIPH0:
+ parent = V3S_CLK_PLL_PERIPH0;
+ div *= CCU_AHB1_PRE_DIV(reg);
+ break;
+ default:
+ return 0;
+ }
+ return sxiccmu_ccu_get_frequency(sc, &parent) / div;
+ case V3S_CLK_AHB2:
+ reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
+ switch (reg & CCU_AHB2_CLK_CFG) {
+ case 0:
+ parent = V3S_CLK_AHB1;
+ div = 1;
+ break;
+ case 1:
+ parent = V3S_CLK_PLL_PERIPH0;
+ div = 2;
+ break;
+ default:
+ return 0;
+ }
+ return sxiccmu_ccu_get_frequency(sc, &parent) / div;
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return 0;
+}
+
+uint32_t
 sxiccmu_nop_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
 {
  printf("%s: 0x%08x\n", __func__, idx);
@@ -1414,6 +1485,28 @@
  bus_space_subregion(sc->sc_iot, sc->sc_ioh,
     sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
  parent = R40_CLK_PLL_PERIPH0_2X;
+ parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
+ return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return -1;
+}
+
+int
+sxiccmu_v3s_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
+{
+ struct sxiccmu_clock clock;
+ uint32_t parent, parent_freq;
+
+ switch (idx) {
+ case V3S_CLK_MMC0:
+ case V3S_CLK_MMC1:
+ case V3S_CLK_MMC2:
+ clock.sc_iot = sc->sc_iot;
+ bus_space_subregion(sc->sc_iot, sc->sc_ioh,
+    sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
+ parent = V3S_CLK_PLL_PERIPH0;
  parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
  return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
  }
Index: sxiccmu_clocks.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
retrieving revision 1.23
diff -u -r1.23 sxiccmu_clocks.h
--- sxiccmu_clocks.h 15 Jan 2019 16:07:42 -0000 1.23
+++ sxiccmu_clocks.h 4 Feb 2019 13:47:35 -0000
@@ -473,6 +473,58 @@
  [R40_CLK_USB_PHY2]  = { 0x00cc, 10 },
 };
 
+/* V3s */
+
+#define V3S_CLK_PLL_PERIPH0 5 // XXX
+#define V3S_CLK_AXI 6 // XXX
+#define V3S_CLK_AHB1 7 // XXX
+#define V3S_CLK_AHB2 8 // XXX
+#define V3S_CLK_APB2 9 // XXX
+
+#define V3S_CLK_BUS_MMC0 22
+#define V3S_CLK_BUS_MMC1 23
+#define V3S_CLK_BUS_MMC2 24
+#define V3S_CLK_BUS_EMAC 26
+#define V3S_CLK_BUS_EHCI0 30
+#define V3S_CLK_BUS_OHCI0 31
+#define V3S_CLK_BUS_PIO 37
+#define V3S_CLK_BUS_I2C0 38
+#define V3S_CLK_BUS_I2C1 39
+#define V3S_CLK_BUS_UART0 40
+#define V3S_CLK_BUS_UART1 41
+#define V3S_CLK_BUS_UART2 42
+#define V3S_CLK_BUS_EPHY 43
+
+#define V3S_CLK_MMC0 45
+#define V3S_CLK_MMC1 48
+#define V3S_CLK_MMC2 51
+#define V3S_CLK_USB_PHY0 56
+#define V3S_CLK_USB_OHCI0 57
+
+#define V3S_CLK_LOSC 254
+#define V3S_CLK_HOSC 253
+
+struct sxiccmu_ccu_bit sun8i_v3s_gates[] = {
+ [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 },
+ [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 },
+ [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 },
+ [V3S_CLK_BUS_MMC2] = { 0x0060, 10 },
+ [V3S_CLK_BUS_MMC1] = { 0x0060, 9 },
+ [V3S_CLK_BUS_MMC0] = { 0x0060, 8 },
+ [V3S_CLK_BUS_PIO] = { 0x0068, 5 },
+ [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_EPHY] = { 0x0070, 0 },
+ [V3S_CLK_MMC0] = { 0x0088, 31 },
+ [V3S_CLK_MMC1] = { 0x008c, 31 },
+ [V3S_CLK_MMC2] = { 0x0090, 31 },
+ [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 },
+ [V3S_CLK_USB_PHY0] = { 0x00cc, 8 },
+};
+
 /*
  * Reset Signals
  */
@@ -726,4 +778,37 @@
  [R40_RST_BUS_UART5] = { 0x02d8, 21 },
  [R40_RST_BUS_UART6] = { 0x02d8, 22 },
  [R40_RST_BUS_UART7] = { 0x02d8, 23 },
+};
+
+/* V3s */
+
+#define V3S_RST_USB_PHY0 0
+
+#define V3S_RST_BUS_MMC0 7
+#define V3S_RST_BUS_MMC1 8
+#define V3S_RST_BUS_MMC2 9
+#define V3S_RST_BUS_EMAC 12
+#define V3S_RST_BUS_EHCI0 18
+#define V3S_RST_BUS_OHCI0 22
+#define V3S_RST_BUS_EPHY 39
+#define V3S_RST_BUS_I2C0 46
+#define V3S_RST_BUS_I2C1 47
+#define V3S_RST_BUS_UART0 49
+#define V3S_RST_BUS_UART1 50
+#define V3S_RST_BUS_UART2 51
+
+struct sxiccmu_ccu_bit sun8i_v3s_resets[] = {
+ [V3S_RST_USB_PHY0] = { 0x00cc, 0 },
+ [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 },
+ [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 },
+ [V3S_RST_BUS_EMAC] = { 0x02c0, 17 },
+ [V3S_RST_BUS_MMC2] = { 0x02c0, 10 },
+ [V3S_RST_BUS_MMC1] = { 0x02c0, 9 },
+ [V3S_RST_BUS_MMC0] = { 0x02c0, 8 },
+ [V3S_RST_BUS_EPHY] = { 0x02c8, 2 },
+ [V3S_RST_BUS_UART2] = { 0x02d8, 18 },
+ [V3S_RST_BUS_UART1] = { 0x02d8, 17 },
+ [V3S_RST_BUS_UART0] = { 0x02d8, 16 },
+ [V3S_RST_BUS_I2C1] = { 0x02d8, 1 },
+ [V3S_RST_BUS_I2C0] = { 0x02d8, 0 },
 };
Index: sxipio.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio.c,v
retrieving revision 1.9
diff -u -r1.9 sxipio.c
--- sxipio.c 28 Dec 2017 18:05:09 -0000 1.9
+++ sxipio.c 4 Feb 2019 13:47:35 -0000
@@ -154,6 +154,10 @@
  sun8i_h3_r_pins, nitems(sun8i_h3_r_pins)
  },
  {
+ "allwinner,sun8i-v3s-pinctrl",
+ sun8i_v3s_pins, nitems(sun8i_v3s_pins)
+ },
+ {
  "allwinner,sun9i-a80-pinctrl",
  sun9i_a80_pins, nitems(sun9i_a80_pins)
  },
Index: sxipio_pins.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio_pins.h,v
retrieving revision 1.5
diff -u -r1.5 sxipio_pins.h
--- sxipio_pins.h 28 Dec 2017 18:05:09 -0000 1.5
+++ sxipio_pins.h 4 Feb 2019 13:47:36 -0000
@@ -6485,6 +6485,323 @@
  } },
 };
 
+struct sxipio_pin sun8i_v3s_pins[] = {
+ { SXIPIO_PIN(B, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(B, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(B, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(B, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(B, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "pwm0", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(B, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "pwm1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(B, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(B, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(B, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c1", 2 },
+ { "uart0", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(B, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c1", 2 },
+ { "uart0", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc2", 2 },
+ { "spi0", 3 },
+ } },
+ { SXIPIO_PIN(C, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc2", 2 },
+ { "spi0", 3 },
+ } },
+ { SXIPIO_PIN(C, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc2", 2 },
+ { "spi0", 3 },
+ } },
+ { SXIPIO_PIN(C, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc2", 2 },
+ { "spi0", 3 },
+ } },
+ { SXIPIO_PIN(E, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 16), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 17), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 18), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 19), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "lcd0", 3 },
+ } },
+ { SXIPIO_PIN(E, 20), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "mcsi", 3 },
+ } },
+ { SXIPIO_PIN(E, 21), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "i2c1", 3 },
+ { "uart1", 4 },
+ } },
+ { SXIPIO_PIN(E, 22), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "i2c1", 3 },
+ { "uart1", 4 },
+ } },
+ { SXIPIO_PIN(E, 23), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 3 },
+ { "uart1", 4 },
+ } },
+ { SXIPIO_PIN(E, 24), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 3 },
+ { "uart1", 4 },
+ } },
+ { SXIPIO_PIN(F, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ } },
+ { SXIPIO_PIN(F, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ } },
+ { SXIPIO_PIN(F, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "uart0", 3 },
+ } },
+ { SXIPIO_PIN(F, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ } },
+ { SXIPIO_PIN(F, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "uart0", 3 },
+ } },
+ { SXIPIO_PIN(F, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ } },
+ { SXIPIO_PIN(F, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ } },
+ { SXIPIO_PIN(G, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+};
+
 struct sxipio_pin sun9i_a80_pins[] = {
  { SXIPIO_PIN(A, 0), {
  { "gpio_in", 0 },

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Re: [wip] armv7: Lichee Pi Zero (Allwinner V3s) support

Mark Kettenis
> Date: Tue, 05 Feb 2019 00:41:01 +0900
> From: SASANO Takayoshi <[hidden email]>
>
> Hi,
>
> > There is no support for v3s in sxiccmu(4) and sxipio(4).
> > There is no driver for mentor usb otg "allwinner,sun8i-h3-musb"
>
> I added v3s support code to sxiccmu(4) and sxipio(4),
> but hangs up at attaching root device.

I have some code that generates the tables used by sxipio(4).  I've
updated that code and committed the sxipio(4) changes.

I have one request for a change in the sxiccmu(4) code.  See the
comment below.  Can you make that change and send an updated diff?

Thanks,

Mark


> Index: sxiccmu.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
> retrieving revision 1.21
> diff -u -r1.21 sxiccmu.c
> --- sxiccmu.c 3 Aug 2018 21:28:28 -0000 1.21
> +++ sxiccmu.c 4 Feb 2019 13:47:35 -0000
> @@ -103,6 +103,8 @@
>  uint32_t sxiccmu_h3_r_get_frequency(struct sxiccmu_softc *, uint32_t);
>  uint32_t sxiccmu_r40_get_frequency(struct sxiccmu_softc *, uint32_t);
>  int sxiccmu_r40_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
> +int sxiccmu_v3s_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
> +uint32_t sxiccmu_v3s_get_frequency(struct sxiccmu_softc *, uint32_t);
>  uint32_t sxiccmu_nop_get_frequency(struct sxiccmu_softc *, uint32_t);
>  int sxiccmu_nop_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
>  
> @@ -122,6 +124,7 @@
>      OF_is_compatible(node, "allwinner,sun8i-a23") ||
>      OF_is_compatible(node, "allwinner,sun8i-a33") ||
>      OF_is_compatible(node, "allwinner,sun8i-h3") ||
> +    OF_is_compatible(node, "allwinner,sun8i-v3s") ||
>      OF_is_compatible(node, "allwinner,sun9i-a80") ||
>      OF_is_compatible(node, "allwinner,sun50i-a64") ||
>      OF_is_compatible(node, "allwinner,sun50i-h5"));
> @@ -135,6 +138,7 @@
>      OF_is_compatible(node, "allwinner,sun8i-h3-ccu") ||
>      OF_is_compatible(node, "allwinner,sun8i-h3-r-ccu") ||
>      OF_is_compatible(node, "allwinner,sun8i-r40-ccu") ||
> +    OF_is_compatible(node, "allwinner,sun8i-v3s-ccu") ||
>      OF_is_compatible(node, "allwinner,sun9i-a80-ccu") ||
>      OF_is_compatible(node, "allwinner,sun9i-a80-usb-clks") ||
>      OF_is_compatible(node, "allwinner,sun9i-a80-mmc-config-clk") ||
> @@ -211,6 +215,14 @@
>   sc->sc_nresets = nitems(sun8i_r40_resets);
>   sc->sc_get_frequency = sxiccmu_r40_get_frequency;
>   sc->sc_set_frequency = sxiccmu_r40_set_frequency;
> + } else if (OF_is_compatible(node, "allwinner,sun8i-v3s-ccu")) {
> + KASSERT(faa->fa_nreg > 0);
> + sc->sc_gates = sun8i_v3s_gates;
> + sc->sc_ngates = nitems(sun8i_v3s_gates);
> + sc->sc_resets = sun8i_v3s_resets;
> + sc->sc_nresets = nitems(sun8i_v3s_resets);
> + sc->sc_get_frequency = sxiccmu_v3s_get_frequency;
> + sc->sc_set_frequency = sxiccmu_v3s_set_frequency;
>   } else if (OF_is_compatible(node, "allwinner,sun9i-a80-ccu")) {
>   KASSERT(faa->fa_nreg > 0);
>   sc->sc_gates = sun9i_a80_gates;
> @@ -1233,6 +1245,65 @@
>  }
>  
>  uint32_t
> +sxiccmu_v3s_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
> +{
> + uint32_t parent;
> + uint32_t reg, div;
> +
> + switch (idx) {
> + case V3S_CLK_LOSC:
> + return clock_get_frequency(sc->sc_node, "losc");
> + case V3S_CLK_HOSC:
> + return clock_get_frequency(sc->sc_node, "hosc");
> + case V3S_CLK_PLL_PERIPH0:
> + /* Not hardcoded, but recommended. */
> + return 600000000;
> + case V3S_CLK_APB2:
> + /* XXX Controlled by a MUX. */
> + return 24000000;
> + case V3S_CLK_AHB1:
> + reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
> + div = CCU_AHB1_CLK_DIV_RATIO(reg);
> + switch (reg & CCU_AHB1_CLK_SRC_SEL) {
> + case CCU_AHB1_CLK_SRC_SEL_LOSC:
> + parent = V3S_CLK_LOSC;
> + break;
> + case CCU_AHB1_CLK_SRC_SEL_OSC24M:
> + parent = V3S_CLK_HOSC;
> + break;
> + case CCU_AHB1_CLK_SRC_SEL_AXI:
> + parent = V3S_CLK_AXI;
> + break;
> + case CCU_AHB1_CLK_SRC_SEL_PERIPH0:
> + parent = V3S_CLK_PLL_PERIPH0;
> + div *= CCU_AHB1_PRE_DIV(reg);
> + break;
> + default:
> + return 0;
> + }
> + return sxiccmu_ccu_get_frequency(sc, &parent) / div;
> + case V3S_CLK_AHB2:
> + reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
> + switch (reg & CCU_AHB2_CLK_CFG) {
> + case 0:
> + parent = V3S_CLK_AHB1;
> + div = 1;
> + break;
> + case 1:
> + parent = V3S_CLK_PLL_PERIPH0;
> + div = 2;
> + break;
> + default:
> + return 0;
> + }
> + return sxiccmu_ccu_get_frequency(sc, &parent) / div;
> + }
> +
> + printf("%s: 0x%08x\n", __func__, idx);
> + return 0;
> +}
> +
> +uint32_t
>  sxiccmu_nop_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
>  {
>   printf("%s: 0x%08x\n", __func__, idx);
> @@ -1414,6 +1485,28 @@
>   bus_space_subregion(sc->sc_iot, sc->sc_ioh,
>      sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
>   parent = R40_CLK_PLL_PERIPH0_2X;
> + parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
> + return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
> + }
> +
> + printf("%s: 0x%08x\n", __func__, idx);
> + return -1;
> +}
> +
> +int
> +sxiccmu_v3s_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
> +{
> + struct sxiccmu_clock clock;
> + uint32_t parent, parent_freq;
> +
> + switch (idx) {
> + case V3S_CLK_MMC0:
> + case V3S_CLK_MMC1:
> + case V3S_CLK_MMC2:
> + clock.sc_iot = sc->sc_iot;
> + bus_space_subregion(sc->sc_iot, sc->sc_ioh,
> +    sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
> + parent = V3S_CLK_PLL_PERIPH0;
>   parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
>   return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
>   }
> Index: sxiccmu_clocks.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
> retrieving revision 1.23
> diff -u -r1.23 sxiccmu_clocks.h
> --- sxiccmu_clocks.h 15 Jan 2019 16:07:42 -0000 1.23
> +++ sxiccmu_clocks.h 4 Feb 2019 13:47:35 -0000
> @@ -473,6 +473,58 @@
>   [R40_CLK_USB_PHY2]  = { 0x00cc, 10 },
>  };
>  
> +/* V3s */
> +
> +#define V3S_CLK_PLL_PERIPH0 5 // XXX
> +#define V3S_CLK_AXI 6 // XXX
> +#define V3S_CLK_AHB1 7 // XXX
> +#define V3S_CLK_AHB2 8 // XXX
> +#define V3S_CLK_APB2 9 // XXX

Probably best to use the same numbers as the Linux kernel uses, in
case these get exported for use in device trees.

V3S_CLK_PLL_PERIPH0 -> 9
V3S_CLK_AXI -> 15
V3S_CLK_AHB1 -> 16
V3S_CLK_APB2 -> 18
V3S_CLK_AHB2 -> 19

> +
> +#define V3S_CLK_BUS_MMC0 22
> +#define V3S_CLK_BUS_MMC1 23
> +#define V3S_CLK_BUS_MMC2 24
> +#define V3S_CLK_BUS_EMAC 26
> +#define V3S_CLK_BUS_EHCI0 30
> +#define V3S_CLK_BUS_OHCI0 31
> +#define V3S_CLK_BUS_PIO 37
> +#define V3S_CLK_BUS_I2C0 38
> +#define V3S_CLK_BUS_I2C1 39
> +#define V3S_CLK_BUS_UART0 40
> +#define V3S_CLK_BUS_UART1 41
> +#define V3S_CLK_BUS_UART2 42
> +#define V3S_CLK_BUS_EPHY 43
> +
> +#define V3S_CLK_MMC0 45
> +#define V3S_CLK_MMC1 48
> +#define V3S_CLK_MMC2 51
> +#define V3S_CLK_USB_PHY0 56
> +#define V3S_CLK_USB_OHCI0 57
> +
> +#define V3S_CLK_LOSC 254
> +#define V3S_CLK_HOSC 253
> +
> +struct sxiccmu_ccu_bit sun8i_v3s_gates[] = {
> + [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 },
> + [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 },
> + [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 },
> + [V3S_CLK_BUS_MMC2] = { 0x0060, 10 },
> + [V3S_CLK_BUS_MMC1] = { 0x0060, 9 },
> + [V3S_CLK_BUS_MMC0] = { 0x0060, 8 },
> + [V3S_CLK_BUS_PIO] = { 0x0068, 5 },
> + [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_EPHY] = { 0x0070, 0 },
> + [V3S_CLK_MMC0] = { 0x0088, 31 },
> + [V3S_CLK_MMC1] = { 0x008c, 31 },
> + [V3S_CLK_MMC2] = { 0x0090, 31 },
> + [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 },
> + [V3S_CLK_USB_PHY0] = { 0x00cc, 8 },
> +};
> +
>  /*
>   * Reset Signals
>   */
> @@ -726,4 +778,37 @@
>   [R40_RST_BUS_UART5] = { 0x02d8, 21 },
>   [R40_RST_BUS_UART6] = { 0x02d8, 22 },
>   [R40_RST_BUS_UART7] = { 0x02d8, 23 },
> +};
> +
> +/* V3s */
> +
> +#define V3S_RST_USB_PHY0 0
> +
> +#define V3S_RST_BUS_MMC0 7
> +#define V3S_RST_BUS_MMC1 8
> +#define V3S_RST_BUS_MMC2 9
> +#define V3S_RST_BUS_EMAC 12
> +#define V3S_RST_BUS_EHCI0 18
> +#define V3S_RST_BUS_OHCI0 22
> +#define V3S_RST_BUS_EPHY 39
> +#define V3S_RST_BUS_I2C0 46
> +#define V3S_RST_BUS_I2C1 47
> +#define V3S_RST_BUS_UART0 49
> +#define V3S_RST_BUS_UART1 50
> +#define V3S_RST_BUS_UART2 51
> +
> +struct sxiccmu_ccu_bit sun8i_v3s_resets[] = {
> + [V3S_RST_USB_PHY0] = { 0x00cc, 0 },
> + [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 },
> + [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 },
> + [V3S_RST_BUS_EMAC] = { 0x02c0, 17 },
> + [V3S_RST_BUS_MMC2] = { 0x02c0, 10 },
> + [V3S_RST_BUS_MMC1] = { 0x02c0, 9 },
> + [V3S_RST_BUS_MMC0] = { 0x02c0, 8 },
> + [V3S_RST_BUS_EPHY] = { 0x02c8, 2 },
> + [V3S_RST_BUS_UART2] = { 0x02d8, 18 },
> + [V3S_RST_BUS_UART1] = { 0x02d8, 17 },
> + [V3S_RST_BUS_UART0] = { 0x02d8, 16 },
> + [V3S_RST_BUS_I2C1] = { 0x02d8, 1 },
> + [V3S_RST_BUS_I2C0] = { 0x02d8, 0 },
>  };

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Re: [wip] armv7: Lichee Pi Zero (Allwinner V3s) support

SASANO Takayoshi
Hello,

> I have one request for a change in the sxiccmu(4) code.  See the
> comment below.  Can you make that change and send an updated diff?

Here is the new diff. the definitions of V3S_CLK_PLL_PERIPH0,
V3S_CLK_AXI, V3S_CLK_AHB1, V3S_CLK_APB2 and V3S_CLK_AHB2 are updated.

regards,

--
SASANO Takayoshi (JG1UAA) <[hidden email]>

Index: sxiccmu.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
retrieving revision 1.21
diff -u -p -u -r1.21 sxiccmu.c
--- sxiccmu.c 3 Aug 2018 21:28:28 -0000 1.21
+++ sxiccmu.c 11 Feb 2019 08:02:32 -0000
@@ -103,6 +103,8 @@ int sxiccmu_h3_set_frequency(struct sxic
 uint32_t sxiccmu_h3_r_get_frequency(struct sxiccmu_softc *, uint32_t);
 uint32_t sxiccmu_r40_get_frequency(struct sxiccmu_softc *, uint32_t);
 int sxiccmu_r40_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
+int sxiccmu_v3s_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
+uint32_t sxiccmu_v3s_get_frequency(struct sxiccmu_softc *, uint32_t);
 uint32_t sxiccmu_nop_get_frequency(struct sxiccmu_softc *, uint32_t);
 int sxiccmu_nop_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
 
@@ -122,6 +124,7 @@ sxiccmu_match(struct device *parent, voi
     OF_is_compatible(node, "allwinner,sun8i-a23") ||
     OF_is_compatible(node, "allwinner,sun8i-a33") ||
     OF_is_compatible(node, "allwinner,sun8i-h3") ||
+    OF_is_compatible(node, "allwinner,sun8i-v3s") ||
     OF_is_compatible(node, "allwinner,sun9i-a80") ||
     OF_is_compatible(node, "allwinner,sun50i-a64") ||
     OF_is_compatible(node, "allwinner,sun50i-h5"));
@@ -135,6 +138,7 @@ sxiccmu_match(struct device *parent, voi
     OF_is_compatible(node, "allwinner,sun8i-h3-ccu") ||
     OF_is_compatible(node, "allwinner,sun8i-h3-r-ccu") ||
     OF_is_compatible(node, "allwinner,sun8i-r40-ccu") ||
+    OF_is_compatible(node, "allwinner,sun8i-v3s-ccu") ||
     OF_is_compatible(node, "allwinner,sun9i-a80-ccu") ||
     OF_is_compatible(node, "allwinner,sun9i-a80-usb-clks") ||
     OF_is_compatible(node, "allwinner,sun9i-a80-mmc-config-clk") ||
@@ -211,6 +215,14 @@ sxiccmu_attach(struct device *parent, st
  sc->sc_nresets = nitems(sun8i_r40_resets);
  sc->sc_get_frequency = sxiccmu_r40_get_frequency;
  sc->sc_set_frequency = sxiccmu_r40_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun8i-v3s-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun8i_v3s_gates;
+ sc->sc_ngates = nitems(sun8i_v3s_gates);
+ sc->sc_resets = sun8i_v3s_resets;
+ sc->sc_nresets = nitems(sun8i_v3s_resets);
+ sc->sc_get_frequency = sxiccmu_v3s_get_frequency;
+ sc->sc_set_frequency = sxiccmu_v3s_set_frequency;
  } else if (OF_is_compatible(node, "allwinner,sun9i-a80-ccu")) {
  KASSERT(faa->fa_nreg > 0);
  sc->sc_gates = sun9i_a80_gates;
@@ -1233,6 +1245,65 @@ sxiccmu_r40_get_frequency(struct sxiccmu
 }
 
 uint32_t
+sxiccmu_v3s_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+ uint32_t parent;
+ uint32_t reg, div;
+
+ switch (idx) {
+ case V3S_CLK_LOSC:
+ return clock_get_frequency(sc->sc_node, "losc");
+ case V3S_CLK_HOSC:
+ return clock_get_frequency(sc->sc_node, "hosc");
+ case V3S_CLK_PLL_PERIPH0:
+ /* Not hardcoded, but recommended. */
+ return 600000000;
+ case V3S_CLK_APB2:
+ /* XXX Controlled by a MUX. */
+ return 24000000;
+ case V3S_CLK_AHB1:
+ reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
+ div = CCU_AHB1_CLK_DIV_RATIO(reg);
+ switch (reg & CCU_AHB1_CLK_SRC_SEL) {
+ case CCU_AHB1_CLK_SRC_SEL_LOSC:
+ parent = V3S_CLK_LOSC;
+ break;
+ case CCU_AHB1_CLK_SRC_SEL_OSC24M:
+ parent = V3S_CLK_HOSC;
+ break;
+ case CCU_AHB1_CLK_SRC_SEL_AXI:
+ parent = V3S_CLK_AXI;
+ break;
+ case CCU_AHB1_CLK_SRC_SEL_PERIPH0:
+ parent = V3S_CLK_PLL_PERIPH0;
+ div *= CCU_AHB1_PRE_DIV(reg);
+ break;
+ default:
+ return 0;
+ }
+ return sxiccmu_ccu_get_frequency(sc, &parent) / div;
+ case V3S_CLK_AHB2:
+ reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
+ switch (reg & CCU_AHB2_CLK_CFG) {
+ case 0:
+ parent = V3S_CLK_AHB1;
+ div = 1;
+ break;
+ case 1:
+ parent = V3S_CLK_PLL_PERIPH0;
+ div = 2;
+ break;
+ default:
+ return 0;
+ }
+ return sxiccmu_ccu_get_frequency(sc, &parent) / div;
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return 0;
+}
+
+uint32_t
 sxiccmu_nop_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
 {
  printf("%s: 0x%08x\n", __func__, idx);
@@ -1414,6 +1485,28 @@ sxiccmu_r40_set_frequency(struct sxiccmu
  bus_space_subregion(sc->sc_iot, sc->sc_ioh,
     sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
  parent = R40_CLK_PLL_PERIPH0_2X;
+ parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
+ return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return -1;
+}
+
+int
+sxiccmu_v3s_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
+{
+ struct sxiccmu_clock clock;
+ uint32_t parent, parent_freq;
+
+ switch (idx) {
+ case V3S_CLK_MMC0:
+ case V3S_CLK_MMC1:
+ case V3S_CLK_MMC2:
+ clock.sc_iot = sc->sc_iot;
+ bus_space_subregion(sc->sc_iot, sc->sc_ioh,
+    sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
+ parent = V3S_CLK_PLL_PERIPH0;
  parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
  return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
  }
Index: sxiccmu_clocks.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
retrieving revision 1.23
diff -u -p -u -r1.23 sxiccmu_clocks.h
--- sxiccmu_clocks.h 15 Jan 2019 16:07:42 -0000 1.23
+++ sxiccmu_clocks.h 11 Feb 2019 08:02:36 -0000
@@ -473,6 +473,58 @@ struct sxiccmu_ccu_bit sun8i_r40_gates[]
  [R40_CLK_USB_PHY2]  = { 0x00cc, 10 },
 };
 
+/* V3s */
+
+#define V3S_CLK_PLL_PERIPH0 9
+#define V3S_CLK_AXI 15
+#define V3S_CLK_AHB1 16
+#define V3S_CLK_APB2 18
+#define V3S_CLK_AHB2 19
+
+#define V3S_CLK_BUS_MMC0 22
+#define V3S_CLK_BUS_MMC1 23
+#define V3S_CLK_BUS_MMC2 24
+#define V3S_CLK_BUS_EMAC 26
+#define V3S_CLK_BUS_EHCI0 30
+#define V3S_CLK_BUS_OHCI0 31
+#define V3S_CLK_BUS_PIO 37
+#define V3S_CLK_BUS_I2C0 38
+#define V3S_CLK_BUS_I2C1 39
+#define V3S_CLK_BUS_UART0 40
+#define V3S_CLK_BUS_UART1 41
+#define V3S_CLK_BUS_UART2 42
+#define V3S_CLK_BUS_EPHY 43
+
+#define V3S_CLK_MMC0 45
+#define V3S_CLK_MMC1 48
+#define V3S_CLK_MMC2 51
+#define V3S_CLK_USB_PHY0 56
+#define V3S_CLK_USB_OHCI0 57
+
+#define V3S_CLK_LOSC 254
+#define V3S_CLK_HOSC 253
+
+struct sxiccmu_ccu_bit sun8i_v3s_gates[] = {
+ [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 },
+ [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 },
+ [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 },
+ [V3S_CLK_BUS_MMC2] = { 0x0060, 10 },
+ [V3S_CLK_BUS_MMC1] = { 0x0060, 9 },
+ [V3S_CLK_BUS_MMC0] = { 0x0060, 8 },
+ [V3S_CLK_BUS_PIO] = { 0x0068, 5 },
+ [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 },
+ [V3S_CLK_BUS_EPHY] = { 0x0070, 0 },
+ [V3S_CLK_MMC0] = { 0x0088, 31 },
+ [V3S_CLK_MMC1] = { 0x008c, 31 },
+ [V3S_CLK_MMC2] = { 0x0090, 31 },
+ [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 },
+ [V3S_CLK_USB_PHY0] = { 0x00cc, 8 },
+};
+
 /*
  * Reset Signals
  */
@@ -726,4 +778,37 @@ struct sxiccmu_ccu_bit sun8i_r40_resets[
  [R40_RST_BUS_UART5] = { 0x02d8, 21 },
  [R40_RST_BUS_UART6] = { 0x02d8, 22 },
  [R40_RST_BUS_UART7] = { 0x02d8, 23 },
+};
+
+/* V3s */
+
+#define V3S_RST_USB_PHY0 0
+
+#define V3S_RST_BUS_MMC0 7
+#define V3S_RST_BUS_MMC1 8
+#define V3S_RST_BUS_MMC2 9
+#define V3S_RST_BUS_EMAC 12
+#define V3S_RST_BUS_EHCI0 18
+#define V3S_RST_BUS_OHCI0 22
+#define V3S_RST_BUS_EPHY 39
+#define V3S_RST_BUS_I2C0 46
+#define V3S_RST_BUS_I2C1 47
+#define V3S_RST_BUS_UART0 49
+#define V3S_RST_BUS_UART1 50
+#define V3S_RST_BUS_UART2 51
+
+struct sxiccmu_ccu_bit sun8i_v3s_resets[] = {
+ [V3S_RST_USB_PHY0] = { 0x00cc, 0 },
+ [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 },
+ [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 },
+ [V3S_RST_BUS_EMAC] = { 0x02c0, 17 },
+ [V3S_RST_BUS_MMC2] = { 0x02c0, 10 },
+ [V3S_RST_BUS_MMC1] = { 0x02c0, 9 },
+ [V3S_RST_BUS_MMC0] = { 0x02c0, 8 },
+ [V3S_RST_BUS_EPHY] = { 0x02c8, 2 },
+ [V3S_RST_BUS_UART2] = { 0x02d8, 18 },
+ [V3S_RST_BUS_UART1] = { 0x02d8, 17 },
+ [V3S_RST_BUS_UART0] = { 0x02d8, 16 },
+ [V3S_RST_BUS_I2C1] = { 0x02d8, 1 },
+ [V3S_RST_BUS_I2C0] = { 0x02d8, 0 },
 };

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Re: [wip] armv7: Lichee Pi Zero (Allwinner V3s) support

Mark Kettenis
> Date: Tue, 12 Feb 2019 06:56:10 +0900
> From: SASANO Takayoshi <[hidden email]>
>
> Hello,
>
> > I have one request for a change in the sxiccmu(4) code.  See the
> > comment below.  Can you make that change and send an updated diff?
>
> Here is the new diff. the definitions of V3S_CLK_PLL_PERIPH0,
> V3S_CLK_AXI, V3S_CLK_AHB1, V3S_CLK_APB2 and V3S_CLK_AHB2 are updated.
>
> regards,

Thanks.  I committed this with a small tweak putting the function
prototypes in consistent order.

Does this mean that OpenBSD is functional on the Lichee Pi Zero now?
If so, I'll add it to the armv7 web page.

> --
> SASANO Takayoshi (JG1UAA) <[hidden email]>
>
> Index: sxiccmu.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
> retrieving revision 1.21
> diff -u -p -u -r1.21 sxiccmu.c
> --- sxiccmu.c 3 Aug 2018 21:28:28 -0000 1.21
> +++ sxiccmu.c 11 Feb 2019 08:02:32 -0000
> @@ -103,6 +103,8 @@ int sxiccmu_h3_set_frequency(struct sxic
>  uint32_t sxiccmu_h3_r_get_frequency(struct sxiccmu_softc *, uint32_t);
>  uint32_t sxiccmu_r40_get_frequency(struct sxiccmu_softc *, uint32_t);
>  int sxiccmu_r40_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
> +int sxiccmu_v3s_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
> +uint32_t sxiccmu_v3s_get_frequency(struct sxiccmu_softc *, uint32_t);
>  uint32_t sxiccmu_nop_get_frequency(struct sxiccmu_softc *, uint32_t);
>  int sxiccmu_nop_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
>  
> @@ -122,6 +124,7 @@ sxiccmu_match(struct device *parent, voi
>      OF_is_compatible(node, "allwinner,sun8i-a23") ||
>      OF_is_compatible(node, "allwinner,sun8i-a33") ||
>      OF_is_compatible(node, "allwinner,sun8i-h3") ||
> +    OF_is_compatible(node, "allwinner,sun8i-v3s") ||
>      OF_is_compatible(node, "allwinner,sun9i-a80") ||
>      OF_is_compatible(node, "allwinner,sun50i-a64") ||
>      OF_is_compatible(node, "allwinner,sun50i-h5"));
> @@ -135,6 +138,7 @@ sxiccmu_match(struct device *parent, voi
>      OF_is_compatible(node, "allwinner,sun8i-h3-ccu") ||
>      OF_is_compatible(node, "allwinner,sun8i-h3-r-ccu") ||
>      OF_is_compatible(node, "allwinner,sun8i-r40-ccu") ||
> +    OF_is_compatible(node, "allwinner,sun8i-v3s-ccu") ||
>      OF_is_compatible(node, "allwinner,sun9i-a80-ccu") ||
>      OF_is_compatible(node, "allwinner,sun9i-a80-usb-clks") ||
>      OF_is_compatible(node, "allwinner,sun9i-a80-mmc-config-clk") ||
> @@ -211,6 +215,14 @@ sxiccmu_attach(struct device *parent, st
>   sc->sc_nresets = nitems(sun8i_r40_resets);
>   sc->sc_get_frequency = sxiccmu_r40_get_frequency;
>   sc->sc_set_frequency = sxiccmu_r40_set_frequency;
> + } else if (OF_is_compatible(node, "allwinner,sun8i-v3s-ccu")) {
> + KASSERT(faa->fa_nreg > 0);
> + sc->sc_gates = sun8i_v3s_gates;
> + sc->sc_ngates = nitems(sun8i_v3s_gates);
> + sc->sc_resets = sun8i_v3s_resets;
> + sc->sc_nresets = nitems(sun8i_v3s_resets);
> + sc->sc_get_frequency = sxiccmu_v3s_get_frequency;
> + sc->sc_set_frequency = sxiccmu_v3s_set_frequency;
>   } else if (OF_is_compatible(node, "allwinner,sun9i-a80-ccu")) {
>   KASSERT(faa->fa_nreg > 0);
>   sc->sc_gates = sun9i_a80_gates;
> @@ -1233,6 +1245,65 @@ sxiccmu_r40_get_frequency(struct sxiccmu
>  }
>  
>  uint32_t
> +sxiccmu_v3s_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
> +{
> + uint32_t parent;
> + uint32_t reg, div;
> +
> + switch (idx) {
> + case V3S_CLK_LOSC:
> + return clock_get_frequency(sc->sc_node, "losc");
> + case V3S_CLK_HOSC:
> + return clock_get_frequency(sc->sc_node, "hosc");
> + case V3S_CLK_PLL_PERIPH0:
> + /* Not hardcoded, but recommended. */
> + return 600000000;
> + case V3S_CLK_APB2:
> + /* XXX Controlled by a MUX. */
> + return 24000000;
> + case V3S_CLK_AHB1:
> + reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
> + div = CCU_AHB1_CLK_DIV_RATIO(reg);
> + switch (reg & CCU_AHB1_CLK_SRC_SEL) {
> + case CCU_AHB1_CLK_SRC_SEL_LOSC:
> + parent = V3S_CLK_LOSC;
> + break;
> + case CCU_AHB1_CLK_SRC_SEL_OSC24M:
> + parent = V3S_CLK_HOSC;
> + break;
> + case CCU_AHB1_CLK_SRC_SEL_AXI:
> + parent = V3S_CLK_AXI;
> + break;
> + case CCU_AHB1_CLK_SRC_SEL_PERIPH0:
> + parent = V3S_CLK_PLL_PERIPH0;
> + div *= CCU_AHB1_PRE_DIV(reg);
> + break;
> + default:
> + return 0;
> + }
> + return sxiccmu_ccu_get_frequency(sc, &parent) / div;
> + case V3S_CLK_AHB2:
> + reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
> + switch (reg & CCU_AHB2_CLK_CFG) {
> + case 0:
> + parent = V3S_CLK_AHB1;
> + div = 1;
> + break;
> + case 1:
> + parent = V3S_CLK_PLL_PERIPH0;
> + div = 2;
> + break;
> + default:
> + return 0;
> + }
> + return sxiccmu_ccu_get_frequency(sc, &parent) / div;
> + }
> +
> + printf("%s: 0x%08x\n", __func__, idx);
> + return 0;
> +}
> +
> +uint32_t
>  sxiccmu_nop_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
>  {
>   printf("%s: 0x%08x\n", __func__, idx);
> @@ -1414,6 +1485,28 @@ sxiccmu_r40_set_frequency(struct sxiccmu
>   bus_space_subregion(sc->sc_iot, sc->sc_ioh,
>      sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
>   parent = R40_CLK_PLL_PERIPH0_2X;
> + parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
> + return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
> + }
> +
> + printf("%s: 0x%08x\n", __func__, idx);
> + return -1;
> +}
> +
> +int
> +sxiccmu_v3s_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
> +{
> + struct sxiccmu_clock clock;
> + uint32_t parent, parent_freq;
> +
> + switch (idx) {
> + case V3S_CLK_MMC0:
> + case V3S_CLK_MMC1:
> + case V3S_CLK_MMC2:
> + clock.sc_iot = sc->sc_iot;
> + bus_space_subregion(sc->sc_iot, sc->sc_ioh,
> +    sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
> + parent = V3S_CLK_PLL_PERIPH0;
>   parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
>   return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
>   }
> Index: sxiccmu_clocks.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
> retrieving revision 1.23
> diff -u -p -u -r1.23 sxiccmu_clocks.h
> --- sxiccmu_clocks.h 15 Jan 2019 16:07:42 -0000 1.23
> +++ sxiccmu_clocks.h 11 Feb 2019 08:02:36 -0000
> @@ -473,6 +473,58 @@ struct sxiccmu_ccu_bit sun8i_r40_gates[]
>   [R40_CLK_USB_PHY2]  = { 0x00cc, 10 },
>  };
>  
> +/* V3s */
> +
> +#define V3S_CLK_PLL_PERIPH0 9
> +#define V3S_CLK_AXI 15
> +#define V3S_CLK_AHB1 16
> +#define V3S_CLK_APB2 18
> +#define V3S_CLK_AHB2 19
> +
> +#define V3S_CLK_BUS_MMC0 22
> +#define V3S_CLK_BUS_MMC1 23
> +#define V3S_CLK_BUS_MMC2 24
> +#define V3S_CLK_BUS_EMAC 26
> +#define V3S_CLK_BUS_EHCI0 30
> +#define V3S_CLK_BUS_OHCI0 31
> +#define V3S_CLK_BUS_PIO 37
> +#define V3S_CLK_BUS_I2C0 38
> +#define V3S_CLK_BUS_I2C1 39
> +#define V3S_CLK_BUS_UART0 40
> +#define V3S_CLK_BUS_UART1 41
> +#define V3S_CLK_BUS_UART2 42
> +#define V3S_CLK_BUS_EPHY 43
> +
> +#define V3S_CLK_MMC0 45
> +#define V3S_CLK_MMC1 48
> +#define V3S_CLK_MMC2 51
> +#define V3S_CLK_USB_PHY0 56
> +#define V3S_CLK_USB_OHCI0 57
> +
> +#define V3S_CLK_LOSC 254
> +#define V3S_CLK_HOSC 253
> +
> +struct sxiccmu_ccu_bit sun8i_v3s_gates[] = {
> + [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 },
> + [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 },
> + [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 },
> + [V3S_CLK_BUS_MMC2] = { 0x0060, 10 },
> + [V3S_CLK_BUS_MMC1] = { 0x0060, 9 },
> + [V3S_CLK_BUS_MMC0] = { 0x0060, 8 },
> + [V3S_CLK_BUS_PIO] = { 0x0068, 5 },
> + [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 },
> + [V3S_CLK_BUS_EPHY] = { 0x0070, 0 },
> + [V3S_CLK_MMC0] = { 0x0088, 31 },
> + [V3S_CLK_MMC1] = { 0x008c, 31 },
> + [V3S_CLK_MMC2] = { 0x0090, 31 },
> + [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 },
> + [V3S_CLK_USB_PHY0] = { 0x00cc, 8 },
> +};
> +
>  /*
>   * Reset Signals
>   */
> @@ -726,4 +778,37 @@ struct sxiccmu_ccu_bit sun8i_r40_resets[
>   [R40_RST_BUS_UART5] = { 0x02d8, 21 },
>   [R40_RST_BUS_UART6] = { 0x02d8, 22 },
>   [R40_RST_BUS_UART7] = { 0x02d8, 23 },
> +};
> +
> +/* V3s */
> +
> +#define V3S_RST_USB_PHY0 0
> +
> +#define V3S_RST_BUS_MMC0 7
> +#define V3S_RST_BUS_MMC1 8
> +#define V3S_RST_BUS_MMC2 9
> +#define V3S_RST_BUS_EMAC 12
> +#define V3S_RST_BUS_EHCI0 18
> +#define V3S_RST_BUS_OHCI0 22
> +#define V3S_RST_BUS_EPHY 39
> +#define V3S_RST_BUS_I2C0 46
> +#define V3S_RST_BUS_I2C1 47
> +#define V3S_RST_BUS_UART0 49
> +#define V3S_RST_BUS_UART1 50
> +#define V3S_RST_BUS_UART2 51
> +
> +struct sxiccmu_ccu_bit sun8i_v3s_resets[] = {
> + [V3S_RST_USB_PHY0] = { 0x00cc, 0 },
> + [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 },
> + [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 },
> + [V3S_RST_BUS_EMAC] = { 0x02c0, 17 },
> + [V3S_RST_BUS_MMC2] = { 0x02c0, 10 },
> + [V3S_RST_BUS_MMC1] = { 0x02c0, 9 },
> + [V3S_RST_BUS_MMC0] = { 0x02c0, 8 },
> + [V3S_RST_BUS_EPHY] = { 0x02c8, 2 },
> + [V3S_RST_BUS_UART2] = { 0x02d8, 18 },
> + [V3S_RST_BUS_UART1] = { 0x02d8, 17 },
> + [V3S_RST_BUS_UART0] = { 0x02d8, 16 },
> + [V3S_RST_BUS_I2C1] = { 0x02d8, 1 },
> + [V3S_RST_BUS_I2C0] = { 0x02d8, 0 },
>  };
>

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Re: [wip] armv7: Lichee Pi Zero (Allwinner V3s) support

SASANO Takayoshi
hello,

> Does this mean that OpenBSD is functional on the Lichee Pi Zero now?
> If so, I'll add it to the armv7 web page.

Not yet. We need to support both Ethernet and USB, but they are not
supported even Linux mainline. There is no official device tree
that enabled these devices.

I tried to test USB and Ethernet, there are some troubles.

USB: OHCI/EHCI can be enabled easily, but attached USB device is
not recognized. (USB port is shared by OTG and host controller,
port multiplexer issue?)

Ethernet: need to modify dwxe(4). But it got MAC address but failed to
reset MAC and could not find PHY. (clock/reset and device-tree issue?)

Here is a boot log (syscon is enabled by my dtb),
available memory is too less due to U-boot address (@0x42e00000).

Regards,

----
U-Boot SPL 2019.01 (Feb 13 2019 - 16:34:25 +0900)
DRAM: 64 MiB
Trying to boot from MMC1


U-Boot 2019.01 (Feb 13 2019 - 16:34:25 +0900) Allwinner Technology

CPU:   Allwinner V3s (SUN8I 1681)
Model: Lichee Pi Zero
DRAM:  64 MiB
MMC:   SUNXI SD/MMC: 0
Loading Environment from FAT... *** Warning - bad CRC, using default environment

In:    serial@01c28000
Out:   serial@01c28000
Err:   serial@01c28000
Net:   No ethernet found.
starting USB...
No controllers found
Hit any key to stop autoboot:  0
=> bdinfo
arch_number = 0x00000000
boot_params = 0x40000100
DRAM bank   = 0x00000000
-> start    = 0x40000000
-> size     = 0x04000000
baudrate    = 115200 bps
TLB addr    = 0x43ff0000
relocaddr   = 0x43f7d000
reloc off   = 0x0117d000
irq_sp      = 0x43d5a210
sp start    = 0x43d5a200
Early malloc usage: 11c / 400
fdt_blob    = 0x43d5a220
=> boot
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
7345 bytes read in 10 ms (716.8 KiB/s)
Found EFI removable media binary efi/boot/bootarm.efi
Scanning disks on usb...
Disk usb0 not ready
Disk usb1 not ready
Disk usb2 not ready
Disk usb3 not ready
Scanning disks on mmc...
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Found 3 disks
86916 bytes read in 7 ms (11.8 MiB/s)
## Starting EFI application at 41000000 ...
>> OpenBSD/armv7 BOOTARM 1.1
boot>
sd0: getdisklabel: no disk label
booting sd0a:/bsd: sd0: getdisklabel: no disk label
4533064+683860+243412+563460 [298008+120+312672+276843]=0x697d98

OpenBSD/armv7 booting ...
arg0 0xc0997d98 arg1 0x0 arg2 0x42d49000
Allocating page tables
IRQ stack: p0x409c6000 v0xc09c6000
ABT stack: p0x409c7000 v0xc09c7000
UND stack: p0x409c8000 v0xc09c8000
SVC stack: p0x409c9000 v0xc09c9000
Creating L1 page table at 0x40998000
Mapping kernel
Constructing L2 page tables
undefined page type 0x2 pa 0x40000000 va 0x40000000 pages 0x2000 attr 0x8
type 0x7 pa 0x42000000 va 0x40000000 pages 0x5e9 attr 0x8
type 0x2 pa 0x425e9000 va 0x425e9000 pages 0x74a attr 0x8
type 0x1 pa 0x42d33000 va 0x42d33000 pages 0x16 attr 0x8
type 0x6 pa 0x42d49000 va 0x42d49000 pages 0xa attr 0x8000000000000008
type 0x0 pa 0x42d53000 va 0x42d51000 pages 0x2 attr 0x8
type 0x6 pa 0x42d55000 va 0x42d55000 pages 0x1 attr 0x8000000000000008
type 0x0 pa 0x42d56000 va 0x42d51000 pages 0x1 attr 0x8
type 0x6 pa 0x42d57000 va 0x42d57000 pages 0x1 attr 0x8000000000000008
type 0x0 pa 0x42d58000 va 0x42d58000 pages 0x2 attr 0x8
type 0x2 pa 0x42d5a000 va 0x42d5a000 pages 0x1223 attr 0x8
type 0x5 pa 0x43f7d000 va 0x43f7d000 pages 0x1 attr 0x8000000000000008
type 0x2 pa 0x43f7e000 va 0x42d5a000 pages 0x82 attr 0x8
pmap [ using 888256 bytes of bsd ELF symbol table ]
board type: 0
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.
Copyright (c) 1995-2019 OpenBSD. All rights reserved.  https://www.OpenBSD.org

OpenBSD 6.4-current (GENERIC) #4: Wed Feb 13 19:41:19 JST 2019
    [hidden email]:/usr/src/sys/arch/armv7/compile/GENERIC
real mem  = 39751680 (37MB)
avail mem = 28794880 (27MB)
mainbus0 at root: Lichee Pi Zero
cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
cortex0 at mainbus0
psci0 at mainbus0: PSCI 0.0
sxiccmu0 at mainbus0
agtimer0 at mainbus0: tick rate 24000 KHz
simplebus0 at mainbus0: "soc"
syscon0 at simplebus0: "syscon"
sxiccmu1 at simplebus0
sxipio0 at simplebus0: 52 pins
ampintc0 at simplebus0 nirq 160, ncpu 1: "interrupt-controller"
"syscon" at simplebus0 not configured
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
"usb" at simplebus0 not configured
"phy" at simplebus0 not configured
"clock" at simplebus0 not configured
sxirtc0 at simplebus0
"pinctrl" at simplebus0 not configured
"timer" at simplebus0 not configured
sxidog0 at simplebus0
com0 at simplebus0: ns16550, no working fifo
com0: console
"ethernet" at simplebus0 not configured
"interrupt-controller" at simplebus0 not configured
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
scsibus0 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SS08G, 0080> SCSI2 0/direct removable
sd0: 7580MB, 512 bytes/sector, 15523840 sectors
vscsi0 at root
scsibus1 at vscsi0: 256 targets
softraid0 at root
scsibus2 at softraid0: 256 targets
bootfile: sd0a:/bsd
boot device: sd0
root on sd0a (25bd418bf7d14629.a) swap on sd0b dump on sd0b
WARNING: preposterous clock chip time
WARNING: CHECK AND RESET THE DATE!
Automatic boot in progress: starting file system checks.
/dev/sd0a (25bd418bf7d14629.a): file system is clean; not checking
pf enabled
starting network
starting early daemons: syslogd pflogd ntpd.
starting RPC daemons:.
savecore: no core dump
checking quotas: done.
clearing /tmp
kern.securelevel: 0 -> 1
creating runtime link editor directory cache.
preserving editor files.
starting network daemons: sshd smtpd sndiod.
starting local daemons: cron.
Wed Feb 13 20:33:58 JST 2019

OpenBSD/armv7 (lpizero.uaa.org.uk) (console)

login:

--
SASANO Takayoshi (JG1UAA) <[hidden email]>