apollo lake gpio

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apollo lake gpio

James Hastings
Index: share/man/man4/Makefile
===================================================================
RCS file: /cvs/src/share/man/man4/Makefile,v
retrieving revision 1.713
diff -u -p -u -r1.713 Makefile
--- share/man/man4/Makefile 7 Jun 2019 16:06:59 -0000 1.713
+++ share/man/man4/Makefile 17 Jun 2019 16:18:15 -0000
@@ -10,7 +10,7 @@ MAN= aac.4 abcrtc.4 ac97.4 acphy.4 acrtc
  admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 alc.4 ale.4 agp.4 \
  ahc.4 ahci.4 ahd.4 aibs.4 aic.4 \
  akbd.4 alipm.4 amas.4 amdiic.4 amdpm.4 ami.4 amphy.4 \
- ams.4 an.4 andl.4 aps.4 arc.4 arcofi.4 \
+ ams.4 an.4 andl.4 aplgpio.4 aps.4 arc.4 arcofi.4 \
  asbtm.4 asmc.4 ast.4 atapiscsi.4 atphy.4 ath.4 athn.4 atu.4 atw.4 \
  auacer.4 audio.4 aue.4 auglx.4 auich.4 auixp.4 autri.4 auvia.4 \
  axe.4 axen.4 axppmic.4 azalia.4 \
Index: share/man/man4/acpi.4
===================================================================
RCS file: /cvs/src/share/man/man4/acpi.4,v
retrieving revision 1.57
diff -u -p -u -r1.57 acpi.4
--- share/man/man4/acpi.4 23 Apr 2019 20:23:36 -0000 1.57
+++ share/man/man4/acpi.4 17 Jun 2019 16:18:15 -0000
@@ -90,6 +90,8 @@ ACPI video
 ACPI video output
 .It Xr aibs 4
 ASUSTeK AI Booster ACPI ATK0110 temperature, voltage, and fan sensor
+.It Xr aplgpio 4
+Intel Apollo Lake GPIO controller
 .It Xr bytgpio 4
 Intel Bay Trail GPIO controller
 .It Xr ccp 4
Index: share/man/man4/aplgpio.4
===================================================================
RCS file: share/man/man4/aplgpio.4
diff -N share/man/man4/aplgpio.4
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ share/man/man4/aplgpio.4 17 Jun 2019 16:18:15 -0000
@@ -0,0 +1,50 @@
+.\" $OpenBSD$
+.\"
+.\" Copyright (c) 2019 James Hastings
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate$
+.Dt APLGPIO 4
+.Os
+.Sh NAME
+.Nm aplgpio
+.Nd Intel Apollo Lake GPIO controller
+.Sh SYNOPSIS
+.Cd "aplgpio* at acpi?"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for the GPIO controllers found on Intel's Apollo
+Lake SoC.
+It does not provide direct device driver entry points but makes its
+functions available to
+.Xr acpi 4 .
+.Sh SEE ALSO
+.Xr acpi 4 ,
+.Xr intro 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 6.6 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver was written by
+.An James Hastings
+based on the
+.Xr bytgpio 4
+driver by
+.An Mark Kettenis Aq Mt [hidden email] .
Index: sys/arch/amd64/conf/GENERIC
===================================================================
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.473
diff -u -p -u -r1.473 GENERIC
--- sys/arch/amd64/conf/GENERIC 7 Jun 2019 16:06:59 -0000 1.473
+++ sys/arch/amd64/conf/GENERIC 17 Jun 2019 16:18:16 -0000
@@ -61,6 +61,7 @@ acpivideo* at acpi?
 acpivout* at acpivideo?
 acpipwrres* at acpi?
 aibs* at acpi?
+aplgpio* at acpi?
 bytgpio* at acpi?
 chvgpio* at acpi?
 sdhc* at acpi?
Index: sys/arch/amd64/conf/RAMDISK_CD
===================================================================
RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
retrieving revision 1.179
diff -u -p -u -r1.179 RAMDISK_CD
--- sys/arch/amd64/conf/RAMDISK_CD 4 May 2019 17:59:40 -0000 1.179
+++ sys/arch/amd64/conf/RAMDISK_CD 17 Jun 2019 16:18:16 -0000
@@ -42,6 +42,7 @@ acpiec* at acpi?
 acpiprt* at acpi?
 acpimadt0 at acpi?
 #acpitz* at acpi?
+aplgpio* at acpi?
 bytgpio* at acpi?
 sdhc* at acpi?
 acpihve* at acpi?
Index: sys/dev/acpi/aplgpio.c
===================================================================
RCS file: sys/dev/acpi/aplgpio.c
diff -N sys/dev/acpi/aplgpio.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/dev/acpi/aplgpio.c 17 Jun 2019 16:18:16 -0000
@@ -0,0 +1,304 @@
+/* $OpenBSD$ */
+/*
+ * Copyright (c) 2016 Mark Kettenis
+ * Copyright (c) 2019 James Hastings
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/malloc.h>
+#include <sys/systm.h>
+
+#include <dev/acpi/acpireg.h>
+#include <dev/acpi/acpivar.h>
+#include <dev/acpi/acpidev.h>
+#include <dev/acpi/amltypes.h>
+#include <dev/acpi/dsdt.h>
+
+#define APLGPIO_CONF_TXSTATE 0x00000001
+#define APLGPIO_CONF_RXSTATE 0x00000002
+#define APLGPIO_CONF_RXINV 0x00800000
+#define APLGPIO_CONF_RXEV_EDGE 0x02000000
+#define APLGPIO_CONF_RXEV_ZERO 0x04000000
+#define APLGPIO_CONF_RXEV_MASK 0x06000000
+
+#define APLGPIO_IRQ_STS 0x100
+#define APLGPIO_IRQ_EN 0x110
+#define APLGPIO_PAD_CFG0 0x500
+
+struct aplgpio_intrhand {
+ int (*ih_func)(void *);
+ void *ih_arg;
+};
+
+struct aplgpio_softc {
+ struct device sc_dev;
+ struct acpi_softc *sc_acpi;
+ struct aml_node *sc_node;
+
+ bus_space_tag_t sc_memt;
+ bus_space_handle_t sc_memh;
+ bus_addr_t sc_addr;
+ bus_size_t sc_size;
+
+ int sc_irq;
+ int sc_irq_flags;
+ void *sc_ih;
+
+ int sc_npins;
+ struct aplgpio_intrhand *sc_pin_ih;
+
+ struct acpi_gpio sc_gpio;
+};
+
+int aplgpio_match(struct device *, void *, void *);
+void aplgpio_attach(struct device *, struct device *, void *);
+
+struct cfattach aplgpio_ca = {
+ sizeof(struct aplgpio_softc), aplgpio_match, aplgpio_attach
+};
+
+struct cfdriver aplgpio_cd = {
+ NULL, "aplgpio", DV_DULL
+};
+
+const char *aplgpio_hids[] = {
+ "INT3452",
+ NULL
+};
+
+int aplgpio_parse_resources(int, union acpi_resource *, void *);
+int aplgpio_read_pin(void *, int);
+void aplgpio_write_pin(void *, int, int);
+void aplgpio_intr_establish(void *, int, int, int (*)(), void *);
+int aplgpio_intr(void *);
+
+int
+aplgpio_match(struct device *parent, void *match, void *aux)
+{
+ struct acpi_attach_args *aaa = aux;
+ struct cfdata *cf = match;
+
+ return acpi_matchhids(aaa, aplgpio_hids, cf->cf_driver->cd_name);
+}
+
+void
+aplgpio_attach(struct device *parent, struct device *self, void *aux)
+{
+ struct acpi_attach_args *aaa = aux;
+ struct aplgpio_softc *sc = (struct aplgpio_softc *)self;
+ struct aml_value res;
+ int64_t uid;
+ int i;
+
+ sc->sc_acpi = (struct acpi_softc *)parent;
+ sc->sc_node = aaa->aaa_node;
+ printf(": %s", sc->sc_node->name);
+
+ if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, &uid)) {
+ printf(", can't find uid\n");
+ return;
+ }
+
+ printf(" uid %lld", uid);
+
+ switch (uid) {
+ case 1:
+ sc->sc_npins = 78;
+ break;
+ case 2:
+ sc->sc_npins = 77;
+ break;
+ case 3:
+ sc->sc_npins = 47;
+ break;
+ case 4:
+ sc->sc_npins = 43;
+ break;
+ default:
+ printf("\n");
+ return;
+ }
+
+ if (aml_evalname(sc->sc_acpi, sc->sc_node, "_CRS", 0, NULL, &res)) {
+ printf(", can't find registers\n");
+ return;
+ }
+
+ aml_parse_resource(&res, aplgpio_parse_resources, sc);
+ printf(" addr 0x%lx/0x%lx", sc->sc_addr, sc->sc_size);
+ if (sc->sc_addr == 0 || sc->sc_size == 0) {
+ printf("\n");
+ return;
+ }
+ aml_freevalue(&res);
+
+ sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih),
+    M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (sc->sc_pin_ih == NULL) {
+ printf("\n");
+ return;
+ }
+
+ printf(" irq %d", sc->sc_irq);
+
+ sc->sc_memt = aaa->aaa_memt;
+ if (bus_space_map(sc->sc_memt, sc->sc_addr, sc->sc_size, 0,
+    &sc->sc_memh)) {
+ printf(", can't map registers\n");
+ goto free;
+ }
+
+ sc->sc_ih = acpi_intr_establish(sc->sc_irq, sc->sc_irq_flags, IPL_BIO,
+    aplgpio_intr, sc, sc->sc_dev.dv_xname);
+ if (sc->sc_ih == NULL) {
+ printf(", can't establish interrupt\n");
+ goto unmap;
+ }
+
+ sc->sc_gpio.cookie = sc;
+ sc->sc_gpio.read_pin = aplgpio_read_pin;
+ sc->sc_gpio.write_pin = aplgpio_write_pin;
+ sc->sc_gpio.intr_establish = aplgpio_intr_establish;
+ sc->sc_node->gpio = &sc->sc_gpio;
+
+ /* Mask and clear all interrupts. */
+ for (i = 0; i < sc->sc_npins; i++) {
+ if (i % 32 == 0) {
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_IRQ_EN + (i / 32) * 4, 0x00000000);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_IRQ_STS + (i / 32) * 4, 0xffffffff);
+ }
+ }
+
+ printf(", %d pins\n", sc->sc_npins);
+
+ acpi_register_gpio(sc->sc_acpi, sc->sc_node);
+ return;
+
+unmap:
+ bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size);
+free:
+ free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih));
+}
+
+int
+aplgpio_parse_resources(int crsidx, union acpi_resource *crs, void *arg)
+{
+ struct aplgpio_softc *sc = arg;
+ int type = AML_CRSTYPE(crs);
+
+ switch (type) {
+ case LR_MEM32FIXED:
+ sc->sc_addr = crs->lr_m32fixed._bas;
+ sc->sc_size = crs->lr_m32fixed._len;
+ break;
+ case LR_EXTIRQ:
+ sc->sc_irq = crs->lr_extirq.irq[0];
+ sc->sc_irq_flags = crs->lr_extirq.flags;
+ break;
+ default:
+ printf(" type 0x%x\n", type);
+ break;
+ }
+
+ return 0;
+}
+
+int
+aplgpio_read_pin(void *cookie, int pin)
+{
+ struct aplgpio_softc *sc = cookie;
+ uint32_t reg;
+
+ reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_PAD_CFG0 + pin * 8);
+
+ return !!(reg & APLGPIO_CONF_RXSTATE);
+}
+
+void
+aplgpio_write_pin(void *cookie, int pin, int value)
+{
+ struct aplgpio_softc *sc = cookie;
+ uint32_t reg;
+
+ reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_PAD_CFG0 + pin * 8);
+ if (value)
+ reg |= APLGPIO_CONF_TXSTATE;
+ else
+ reg &= ~APLGPIO_CONF_TXSTATE;
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_PAD_CFG0 + pin * 8, reg);
+}
+
+void
+aplgpio_intr_establish(void *cookie, int pin, int flags,
+    int (*func)(void *), void *arg)
+{
+ struct aplgpio_softc *sc = cookie;
+ uint32_t reg;
+
+ KASSERT(pin >= 0 && pin < sc->sc_npins);
+
+ sc->sc_pin_ih[pin].ih_func = func;
+ sc->sc_pin_ih[pin].ih_arg = arg;
+
+ reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_PAD_CFG0 + pin * 8);
+ reg &= ~(APLGPIO_CONF_RXEV_MASK | APLGPIO_CONF_RXINV);
+ if ((flags & LR_GPIO_MODE) == 1)
+ reg |= APLGPIO_CONF_RXEV_EDGE;
+ if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO)
+ reg |= APLGPIO_CONF_RXINV;
+ if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH)
+ reg |= APLGPIO_CONF_RXEV_EDGE | APLGPIO_CONF_RXEV_ZERO;
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_PAD_CFG0 + pin * 8, reg);
+
+ reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_IRQ_EN + (pin / 32) * 4);
+ reg |= (1 << (pin % 32));
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_IRQ_EN + (pin / 32) * 4, reg);
+}
+
+int
+aplgpio_intr(void *arg)
+{
+ struct aplgpio_softc *sc = arg;
+ uint32_t status, enable;
+ int rc = 0;
+ int pin;
+
+ for (pin = 0; pin < sc->sc_npins; pin++) {
+ if (pin % 32 == 0) {
+ status = bus_space_read_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_IRQ_STS + (pin / 32) * 4);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_IRQ_STS + (pin / 32) * 4, status);
+ enable = bus_space_read_4(sc->sc_memt, sc->sc_memh,
+    APLGPIO_IRQ_EN + (pin / 32) * 4);
+ status &= enable;
+ }
+ if (status & (1 << (pin % 32))) {
+ if (sc->sc_pin_ih[pin].ih_func)
+ sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg);
+ rc = 1;
+ }
+ }
+ return rc;
+}
Index: sys/dev/acpi/files.acpi
===================================================================
RCS file: /cvs/src/sys/dev/acpi/files.acpi,v
retrieving revision 1.50
diff -u -p -u -r1.50 files.acpi
--- sys/dev/acpi/files.acpi 23 Apr 2019 18:34:06 -0000 1.50
+++ sys/dev/acpi/files.acpi 17 Jun 2019 16:18:16 -0000
@@ -116,6 +116,11 @@ device aibs
 attach aibs at acpi
 file dev/acpi/atk0110.c aibs
 
+# Intel Apollo Lake GPIO
+device aplgpio
+attach aplgpio at acpi
+file dev/acpi/aplgpio.c aplgpio
+
 # Intel Bay Trail GPIO
 device bytgpio
 attach bytgpio at acpi

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Re: apollo lake gpio

Mark Kettenis
> From: James Hastings <[hidden email]>
> Date: Mon, 17 Jun 2019 13:24:36 -0400 (EDT)

This diff is ok kettenis@

It might take a few days for me to commit this.  If anybody else wants
to do it based on my ok, go ahead.


> Index: share/man/man4/Makefile
> ===================================================================
> RCS file: /cvs/src/share/man/man4/Makefile,v
> retrieving revision 1.713
> diff -u -p -u -r1.713 Makefile
> --- share/man/man4/Makefile 7 Jun 2019 16:06:59 -0000 1.713
> +++ share/man/man4/Makefile 17 Jun 2019 16:18:15 -0000
> @@ -10,7 +10,7 @@ MAN= aac.4 abcrtc.4 ac97.4 acphy.4 acrtc
>   admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 alc.4 ale.4 agp.4 \
>   ahc.4 ahci.4 ahd.4 aibs.4 aic.4 \
>   akbd.4 alipm.4 amas.4 amdiic.4 amdpm.4 ami.4 amphy.4 \
> - ams.4 an.4 andl.4 aps.4 arc.4 arcofi.4 \
> + ams.4 an.4 andl.4 aplgpio.4 aps.4 arc.4 arcofi.4 \
>   asbtm.4 asmc.4 ast.4 atapiscsi.4 atphy.4 ath.4 athn.4 atu.4 atw.4 \
>   auacer.4 audio.4 aue.4 auglx.4 auich.4 auixp.4 autri.4 auvia.4 \
>   axe.4 axen.4 axppmic.4 azalia.4 \
> Index: share/man/man4/acpi.4
> ===================================================================
> RCS file: /cvs/src/share/man/man4/acpi.4,v
> retrieving revision 1.57
> diff -u -p -u -r1.57 acpi.4
> --- share/man/man4/acpi.4 23 Apr 2019 20:23:36 -0000 1.57
> +++ share/man/man4/acpi.4 17 Jun 2019 16:18:15 -0000
> @@ -90,6 +90,8 @@ ACPI video
>  ACPI video output
>  .It Xr aibs 4
>  ASUSTeK AI Booster ACPI ATK0110 temperature, voltage, and fan sensor
> +.It Xr aplgpio 4
> +Intel Apollo Lake GPIO controller
>  .It Xr bytgpio 4
>  Intel Bay Trail GPIO controller
>  .It Xr ccp 4
> Index: share/man/man4/aplgpio.4
> ===================================================================
> RCS file: share/man/man4/aplgpio.4
> diff -N share/man/man4/aplgpio.4
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ share/man/man4/aplgpio.4 17 Jun 2019 16:18:15 -0000
> @@ -0,0 +1,50 @@
> +.\" $OpenBSD$
> +.\"
> +.\" Copyright (c) 2019 James Hastings
> +.\"
> +.\" Permission to use, copy, modify, and distribute this software for any
> +.\" purpose with or without fee is hereby granted, provided that the above
> +.\" copyright notice and this permission notice appear in all copies.
> +.\"
> +.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
> +.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> +.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
> +.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
> +.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
> +.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
> +.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
> +.\"
> +.Dd $Mdocdate$
> +.Dt APLGPIO 4
> +.Os
> +.Sh NAME
> +.Nm aplgpio
> +.Nd Intel Apollo Lake GPIO controller
> +.Sh SYNOPSIS
> +.Cd "aplgpio* at acpi?"
> +.Sh DESCRIPTION
> +The
> +.Nm
> +driver provides support for the GPIO controllers found on Intel's Apollo
> +Lake SoC.
> +It does not provide direct device driver entry points but makes its
> +functions available to
> +.Xr acpi 4 .
> +.Sh SEE ALSO
> +.Xr acpi 4 ,
> +.Xr intro 4
> +.Sh HISTORY
> +The
> +.Nm
> +driver first appeared in
> +.Ox 6.6 .
> +.Sh AUTHORS
> +.An -nosplit
> +The
> +.Nm
> +driver was written by
> +.An James Hastings
> +based on the
> +.Xr bytgpio 4
> +driver by
> +.An Mark Kettenis Aq Mt [hidden email] .
> Index: sys/arch/amd64/conf/GENERIC
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
> retrieving revision 1.473
> diff -u -p -u -r1.473 GENERIC
> --- sys/arch/amd64/conf/GENERIC 7 Jun 2019 16:06:59 -0000 1.473
> +++ sys/arch/amd64/conf/GENERIC 17 Jun 2019 16:18:16 -0000
> @@ -61,6 +61,7 @@ acpivideo* at acpi?
>  acpivout* at acpivideo?
>  acpipwrres* at acpi?
>  aibs* at acpi?
> +aplgpio* at acpi?
>  bytgpio* at acpi?
>  chvgpio* at acpi?
>  sdhc* at acpi?
> Index: sys/arch/amd64/conf/RAMDISK_CD
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
> retrieving revision 1.179
> diff -u -p -u -r1.179 RAMDISK_CD
> --- sys/arch/amd64/conf/RAMDISK_CD 4 May 2019 17:59:40 -0000 1.179
> +++ sys/arch/amd64/conf/RAMDISK_CD 17 Jun 2019 16:18:16 -0000
> @@ -42,6 +42,7 @@ acpiec* at acpi?
>  acpiprt* at acpi?
>  acpimadt0 at acpi?
>  #acpitz* at acpi?
> +aplgpio* at acpi?
>  bytgpio* at acpi?
>  sdhc* at acpi?
>  acpihve* at acpi?
> Index: sys/dev/acpi/aplgpio.c
> ===================================================================
> RCS file: sys/dev/acpi/aplgpio.c
> diff -N sys/dev/acpi/aplgpio.c
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ sys/dev/acpi/aplgpio.c 17 Jun 2019 16:18:16 -0000
> @@ -0,0 +1,304 @@
> +/* $OpenBSD$ */
> +/*
> + * Copyright (c) 2016 Mark Kettenis
> + * Copyright (c) 2019 James Hastings
> + *
> + * Permission to use, copy, modify, and distribute this software for any
> + * purpose with or without fee is hereby granted, provided that the above
> + * copyright notice and this permission notice appear in all copies.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
> + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
> + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
> + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
> + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
> + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
> + */
> +
> +#include <sys/param.h>
> +#include <sys/malloc.h>
> +#include <sys/systm.h>
> +
> +#include <dev/acpi/acpireg.h>
> +#include <dev/acpi/acpivar.h>
> +#include <dev/acpi/acpidev.h>
> +#include <dev/acpi/amltypes.h>
> +#include <dev/acpi/dsdt.h>
> +
> +#define APLGPIO_CONF_TXSTATE 0x00000001
> +#define APLGPIO_CONF_RXSTATE 0x00000002
> +#define APLGPIO_CONF_RXINV 0x00800000
> +#define APLGPIO_CONF_RXEV_EDGE 0x02000000
> +#define APLGPIO_CONF_RXEV_ZERO 0x04000000
> +#define APLGPIO_CONF_RXEV_MASK 0x06000000
> +
> +#define APLGPIO_IRQ_STS 0x100
> +#define APLGPIO_IRQ_EN 0x110
> +#define APLGPIO_PAD_CFG0 0x500
> +
> +struct aplgpio_intrhand {
> + int (*ih_func)(void *);
> + void *ih_arg;
> +};
> +
> +struct aplgpio_softc {
> + struct device sc_dev;
> + struct acpi_softc *sc_acpi;
> + struct aml_node *sc_node;
> +
> + bus_space_tag_t sc_memt;
> + bus_space_handle_t sc_memh;
> + bus_addr_t sc_addr;
> + bus_size_t sc_size;
> +
> + int sc_irq;
> + int sc_irq_flags;
> + void *sc_ih;
> +
> + int sc_npins;
> + struct aplgpio_intrhand *sc_pin_ih;
> +
> + struct acpi_gpio sc_gpio;
> +};
> +
> +int aplgpio_match(struct device *, void *, void *);
> +void aplgpio_attach(struct device *, struct device *, void *);
> +
> +struct cfattach aplgpio_ca = {
> + sizeof(struct aplgpio_softc), aplgpio_match, aplgpio_attach
> +};
> +
> +struct cfdriver aplgpio_cd = {
> + NULL, "aplgpio", DV_DULL
> +};
> +
> +const char *aplgpio_hids[] = {
> + "INT3452",
> + NULL
> +};
> +
> +int aplgpio_parse_resources(int, union acpi_resource *, void *);
> +int aplgpio_read_pin(void *, int);
> +void aplgpio_write_pin(void *, int, int);
> +void aplgpio_intr_establish(void *, int, int, int (*)(), void *);
> +int aplgpio_intr(void *);
> +
> +int
> +aplgpio_match(struct device *parent, void *match, void *aux)
> +{
> + struct acpi_attach_args *aaa = aux;
> + struct cfdata *cf = match;
> +
> + return acpi_matchhids(aaa, aplgpio_hids, cf->cf_driver->cd_name);
> +}
> +
> +void
> +aplgpio_attach(struct device *parent, struct device *self, void *aux)
> +{
> + struct acpi_attach_args *aaa = aux;
> + struct aplgpio_softc *sc = (struct aplgpio_softc *)self;
> + struct aml_value res;
> + int64_t uid;
> + int i;
> +
> + sc->sc_acpi = (struct acpi_softc *)parent;
> + sc->sc_node = aaa->aaa_node;
> + printf(": %s", sc->sc_node->name);
> +
> + if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, &uid)) {
> + printf(", can't find uid\n");
> + return;
> + }
> +
> + printf(" uid %lld", uid);
> +
> + switch (uid) {
> + case 1:
> + sc->sc_npins = 78;
> + break;
> + case 2:
> + sc->sc_npins = 77;
> + break;
> + case 3:
> + sc->sc_npins = 47;
> + break;
> + case 4:
> + sc->sc_npins = 43;
> + break;
> + default:
> + printf("\n");
> + return;
> + }
> +
> + if (aml_evalname(sc->sc_acpi, sc->sc_node, "_CRS", 0, NULL, &res)) {
> + printf(", can't find registers\n");
> + return;
> + }
> +
> + aml_parse_resource(&res, aplgpio_parse_resources, sc);
> + printf(" addr 0x%lx/0x%lx", sc->sc_addr, sc->sc_size);
> + if (sc->sc_addr == 0 || sc->sc_size == 0) {
> + printf("\n");
> + return;
> + }
> + aml_freevalue(&res);
> +
> + sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih),
> +    M_DEVBUF, M_NOWAIT | M_ZERO);
> + if (sc->sc_pin_ih == NULL) {
> + printf("\n");
> + return;
> + }
> +
> + printf(" irq %d", sc->sc_irq);
> +
> + sc->sc_memt = aaa->aaa_memt;
> + if (bus_space_map(sc->sc_memt, sc->sc_addr, sc->sc_size, 0,
> +    &sc->sc_memh)) {
> + printf(", can't map registers\n");
> + goto free;
> + }
> +
> + sc->sc_ih = acpi_intr_establish(sc->sc_irq, sc->sc_irq_flags, IPL_BIO,
> +    aplgpio_intr, sc, sc->sc_dev.dv_xname);
> + if (sc->sc_ih == NULL) {
> + printf(", can't establish interrupt\n");
> + goto unmap;
> + }
> +
> + sc->sc_gpio.cookie = sc;
> + sc->sc_gpio.read_pin = aplgpio_read_pin;
> + sc->sc_gpio.write_pin = aplgpio_write_pin;
> + sc->sc_gpio.intr_establish = aplgpio_intr_establish;
> + sc->sc_node->gpio = &sc->sc_gpio;
> +
> + /* Mask and clear all interrupts. */
> + for (i = 0; i < sc->sc_npins; i++) {
> + if (i % 32 == 0) {
> + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_IRQ_EN + (i / 32) * 4, 0x00000000);
> + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_IRQ_STS + (i / 32) * 4, 0xffffffff);
> + }
> + }
> +
> + printf(", %d pins\n", sc->sc_npins);
> +
> + acpi_register_gpio(sc->sc_acpi, sc->sc_node);
> + return;
> +
> +unmap:
> + bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size);
> +free:
> + free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih));
> +}
> +
> +int
> +aplgpio_parse_resources(int crsidx, union acpi_resource *crs, void *arg)
> +{
> + struct aplgpio_softc *sc = arg;
> + int type = AML_CRSTYPE(crs);
> +
> + switch (type) {
> + case LR_MEM32FIXED:
> + sc->sc_addr = crs->lr_m32fixed._bas;
> + sc->sc_size = crs->lr_m32fixed._len;
> + break;
> + case LR_EXTIRQ:
> + sc->sc_irq = crs->lr_extirq.irq[0];
> + sc->sc_irq_flags = crs->lr_extirq.flags;
> + break;
> + default:
> + printf(" type 0x%x\n", type);
> + break;
> + }
> +
> + return 0;
> +}
> +
> +int
> +aplgpio_read_pin(void *cookie, int pin)
> +{
> + struct aplgpio_softc *sc = cookie;
> + uint32_t reg;
> +
> + reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_PAD_CFG0 + pin * 8);
> +
> + return !!(reg & APLGPIO_CONF_RXSTATE);
> +}
> +
> +void
> +aplgpio_write_pin(void *cookie, int pin, int value)
> +{
> + struct aplgpio_softc *sc = cookie;
> + uint32_t reg;
> +
> + reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_PAD_CFG0 + pin * 8);
> + if (value)
> + reg |= APLGPIO_CONF_TXSTATE;
> + else
> + reg &= ~APLGPIO_CONF_TXSTATE;
> + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_PAD_CFG0 + pin * 8, reg);
> +}
> +
> +void
> +aplgpio_intr_establish(void *cookie, int pin, int flags,
> +    int (*func)(void *), void *arg)
> +{
> + struct aplgpio_softc *sc = cookie;
> + uint32_t reg;
> +
> + KASSERT(pin >= 0 && pin < sc->sc_npins);
> +
> + sc->sc_pin_ih[pin].ih_func = func;
> + sc->sc_pin_ih[pin].ih_arg = arg;
> +
> + reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_PAD_CFG0 + pin * 8);
> + reg &= ~(APLGPIO_CONF_RXEV_MASK | APLGPIO_CONF_RXINV);
> + if ((flags & LR_GPIO_MODE) == 1)
> + reg |= APLGPIO_CONF_RXEV_EDGE;
> + if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO)
> + reg |= APLGPIO_CONF_RXINV;
> + if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH)
> + reg |= APLGPIO_CONF_RXEV_EDGE | APLGPIO_CONF_RXEV_ZERO;
> + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_PAD_CFG0 + pin * 8, reg);
> +
> + reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_IRQ_EN + (pin / 32) * 4);
> + reg |= (1 << (pin % 32));
> + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_IRQ_EN + (pin / 32) * 4, reg);
> +}
> +
> +int
> +aplgpio_intr(void *arg)
> +{
> + struct aplgpio_softc *sc = arg;
> + uint32_t status, enable;
> + int rc = 0;
> + int pin;
> +
> + for (pin = 0; pin < sc->sc_npins; pin++) {
> + if (pin % 32 == 0) {
> + status = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_IRQ_STS + (pin / 32) * 4);
> + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_IRQ_STS + (pin / 32) * 4, status);
> + enable = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> +    APLGPIO_IRQ_EN + (pin / 32) * 4);
> + status &= enable;
> + }
> + if (status & (1 << (pin % 32))) {
> + if (sc->sc_pin_ih[pin].ih_func)
> + sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg);
> + rc = 1;
> + }
> + }
> + return rc;
> +}
> Index: sys/dev/acpi/files.acpi
> ===================================================================
> RCS file: /cvs/src/sys/dev/acpi/files.acpi,v
> retrieving revision 1.50
> diff -u -p -u -r1.50 files.acpi
> --- sys/dev/acpi/files.acpi 23 Apr 2019 18:34:06 -0000 1.50
> +++ sys/dev/acpi/files.acpi 17 Jun 2019 16:18:16 -0000
> @@ -116,6 +116,11 @@ device aibs
>  attach aibs at acpi
>  file dev/acpi/atk0110.c aibs
>  
> +# Intel Apollo Lake GPIO
> +device aplgpio
> +attach aplgpio at acpi
> +file dev/acpi/aplgpio.c aplgpio
> +
>  # Intel Bay Trail GPIO
>  device bytgpio
>  attach bytgpio at acpi
>
>

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Re: apollo lake gpio

Patrick Wildt-3
Committed, thanks!

On Mon, Jun 17, 2019 at 07:53:50PM +0200, Mark Kettenis wrote:

> > From: James Hastings <[hidden email]>
> > Date: Mon, 17 Jun 2019 13:24:36 -0400 (EDT)
>
> This diff is ok kettenis@
>
> It might take a few days for me to commit this.  If anybody else wants
> to do it based on my ok, go ahead.
>
>
> > Index: share/man/man4/Makefile
> > ===================================================================
> > RCS file: /cvs/src/share/man/man4/Makefile,v
> > retrieving revision 1.713
> > diff -u -p -u -r1.713 Makefile
> > --- share/man/man4/Makefile 7 Jun 2019 16:06:59 -0000 1.713
> > +++ share/man/man4/Makefile 17 Jun 2019 16:18:15 -0000
> > @@ -10,7 +10,7 @@ MAN= aac.4 abcrtc.4 ac97.4 acphy.4 acrtc
> >   admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 alc.4 ale.4 agp.4 \
> >   ahc.4 ahci.4 ahd.4 aibs.4 aic.4 \
> >   akbd.4 alipm.4 amas.4 amdiic.4 amdpm.4 ami.4 amphy.4 \
> > - ams.4 an.4 andl.4 aps.4 arc.4 arcofi.4 \
> > + ams.4 an.4 andl.4 aplgpio.4 aps.4 arc.4 arcofi.4 \
> >   asbtm.4 asmc.4 ast.4 atapiscsi.4 atphy.4 ath.4 athn.4 atu.4 atw.4 \
> >   auacer.4 audio.4 aue.4 auglx.4 auich.4 auixp.4 autri.4 auvia.4 \
> >   axe.4 axen.4 axppmic.4 azalia.4 \
> > Index: share/man/man4/acpi.4
> > ===================================================================
> > RCS file: /cvs/src/share/man/man4/acpi.4,v
> > retrieving revision 1.57
> > diff -u -p -u -r1.57 acpi.4
> > --- share/man/man4/acpi.4 23 Apr 2019 20:23:36 -0000 1.57
> > +++ share/man/man4/acpi.4 17 Jun 2019 16:18:15 -0000
> > @@ -90,6 +90,8 @@ ACPI video
> >  ACPI video output
> >  .It Xr aibs 4
> >  ASUSTeK AI Booster ACPI ATK0110 temperature, voltage, and fan sensor
> > +.It Xr aplgpio 4
> > +Intel Apollo Lake GPIO controller
> >  .It Xr bytgpio 4
> >  Intel Bay Trail GPIO controller
> >  .It Xr ccp 4
> > Index: share/man/man4/aplgpio.4
> > ===================================================================
> > RCS file: share/man/man4/aplgpio.4
> > diff -N share/man/man4/aplgpio.4
> > --- /dev/null 1 Jan 1970 00:00:00 -0000
> > +++ share/man/man4/aplgpio.4 17 Jun 2019 16:18:15 -0000
> > @@ -0,0 +1,50 @@
> > +.\" $OpenBSD$
> > +.\"
> > +.\" Copyright (c) 2019 James Hastings
> > +.\"
> > +.\" Permission to use, copy, modify, and distribute this software for any
> > +.\" purpose with or without fee is hereby granted, provided that the above
> > +.\" copyright notice and this permission notice appear in all copies.
> > +.\"
> > +.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
> > +.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> > +.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
> > +.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
> > +.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
> > +.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
> > +.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
> > +.\"
> > +.Dd $Mdocdate$
> > +.Dt APLGPIO 4
> > +.Os
> > +.Sh NAME
> > +.Nm aplgpio
> > +.Nd Intel Apollo Lake GPIO controller
> > +.Sh SYNOPSIS
> > +.Cd "aplgpio* at acpi?"
> > +.Sh DESCRIPTION
> > +The
> > +.Nm
> > +driver provides support for the GPIO controllers found on Intel's Apollo
> > +Lake SoC.
> > +It does not provide direct device driver entry points but makes its
> > +functions available to
> > +.Xr acpi 4 .
> > +.Sh SEE ALSO
> > +.Xr acpi 4 ,
> > +.Xr intro 4
> > +.Sh HISTORY
> > +The
> > +.Nm
> > +driver first appeared in
> > +.Ox 6.6 .
> > +.Sh AUTHORS
> > +.An -nosplit
> > +The
> > +.Nm
> > +driver was written by
> > +.An James Hastings
> > +based on the
> > +.Xr bytgpio 4
> > +driver by
> > +.An Mark Kettenis Aq Mt [hidden email] .
> > Index: sys/arch/amd64/conf/GENERIC
> > ===================================================================
> > RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
> > retrieving revision 1.473
> > diff -u -p -u -r1.473 GENERIC
> > --- sys/arch/amd64/conf/GENERIC 7 Jun 2019 16:06:59 -0000 1.473
> > +++ sys/arch/amd64/conf/GENERIC 17 Jun 2019 16:18:16 -0000
> > @@ -61,6 +61,7 @@ acpivideo* at acpi?
> >  acpivout* at acpivideo?
> >  acpipwrres* at acpi?
> >  aibs* at acpi?
> > +aplgpio* at acpi?
> >  bytgpio* at acpi?
> >  chvgpio* at acpi?
> >  sdhc* at acpi?
> > Index: sys/arch/amd64/conf/RAMDISK_CD
> > ===================================================================
> > RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
> > retrieving revision 1.179
> > diff -u -p -u -r1.179 RAMDISK_CD
> > --- sys/arch/amd64/conf/RAMDISK_CD 4 May 2019 17:59:40 -0000 1.179
> > +++ sys/arch/amd64/conf/RAMDISK_CD 17 Jun 2019 16:18:16 -0000
> > @@ -42,6 +42,7 @@ acpiec* at acpi?
> >  acpiprt* at acpi?
> >  acpimadt0 at acpi?
> >  #acpitz* at acpi?
> > +aplgpio* at acpi?
> >  bytgpio* at acpi?
> >  sdhc* at acpi?
> >  acpihve* at acpi?
> > Index: sys/dev/acpi/aplgpio.c
> > ===================================================================
> > RCS file: sys/dev/acpi/aplgpio.c
> > diff -N sys/dev/acpi/aplgpio.c
> > --- /dev/null 1 Jan 1970 00:00:00 -0000
> > +++ sys/dev/acpi/aplgpio.c 17 Jun 2019 16:18:16 -0000
> > @@ -0,0 +1,304 @@
> > +/* $OpenBSD$ */
> > +/*
> > + * Copyright (c) 2016 Mark Kettenis
> > + * Copyright (c) 2019 James Hastings
> > + *
> > + * Permission to use, copy, modify, and distribute this software for any
> > + * purpose with or without fee is hereby granted, provided that the above
> > + * copyright notice and this permission notice appear in all copies.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
> > + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> > + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
> > + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
> > + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
> > + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
> > + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
> > + */
> > +
> > +#include <sys/param.h>
> > +#include <sys/malloc.h>
> > +#include <sys/systm.h>
> > +
> > +#include <dev/acpi/acpireg.h>
> > +#include <dev/acpi/acpivar.h>
> > +#include <dev/acpi/acpidev.h>
> > +#include <dev/acpi/amltypes.h>
> > +#include <dev/acpi/dsdt.h>
> > +
> > +#define APLGPIO_CONF_TXSTATE 0x00000001
> > +#define APLGPIO_CONF_RXSTATE 0x00000002
> > +#define APLGPIO_CONF_RXINV 0x00800000
> > +#define APLGPIO_CONF_RXEV_EDGE 0x02000000
> > +#define APLGPIO_CONF_RXEV_ZERO 0x04000000
> > +#define APLGPIO_CONF_RXEV_MASK 0x06000000
> > +
> > +#define APLGPIO_IRQ_STS 0x100
> > +#define APLGPIO_IRQ_EN 0x110
> > +#define APLGPIO_PAD_CFG0 0x500
> > +
> > +struct aplgpio_intrhand {
> > + int (*ih_func)(void *);
> > + void *ih_arg;
> > +};
> > +
> > +struct aplgpio_softc {
> > + struct device sc_dev;
> > + struct acpi_softc *sc_acpi;
> > + struct aml_node *sc_node;
> > +
> > + bus_space_tag_t sc_memt;
> > + bus_space_handle_t sc_memh;
> > + bus_addr_t sc_addr;
> > + bus_size_t sc_size;
> > +
> > + int sc_irq;
> > + int sc_irq_flags;
> > + void *sc_ih;
> > +
> > + int sc_npins;
> > + struct aplgpio_intrhand *sc_pin_ih;
> > +
> > + struct acpi_gpio sc_gpio;
> > +};
> > +
> > +int aplgpio_match(struct device *, void *, void *);
> > +void aplgpio_attach(struct device *, struct device *, void *);
> > +
> > +struct cfattach aplgpio_ca = {
> > + sizeof(struct aplgpio_softc), aplgpio_match, aplgpio_attach
> > +};
> > +
> > +struct cfdriver aplgpio_cd = {
> > + NULL, "aplgpio", DV_DULL
> > +};
> > +
> > +const char *aplgpio_hids[] = {
> > + "INT3452",
> > + NULL
> > +};
> > +
> > +int aplgpio_parse_resources(int, union acpi_resource *, void *);
> > +int aplgpio_read_pin(void *, int);
> > +void aplgpio_write_pin(void *, int, int);
> > +void aplgpio_intr_establish(void *, int, int, int (*)(), void *);
> > +int aplgpio_intr(void *);
> > +
> > +int
> > +aplgpio_match(struct device *parent, void *match, void *aux)
> > +{
> > + struct acpi_attach_args *aaa = aux;
> > + struct cfdata *cf = match;
> > +
> > + return acpi_matchhids(aaa, aplgpio_hids, cf->cf_driver->cd_name);
> > +}
> > +
> > +void
> > +aplgpio_attach(struct device *parent, struct device *self, void *aux)
> > +{
> > + struct acpi_attach_args *aaa = aux;
> > + struct aplgpio_softc *sc = (struct aplgpio_softc *)self;
> > + struct aml_value res;
> > + int64_t uid;
> > + int i;
> > +
> > + sc->sc_acpi = (struct acpi_softc *)parent;
> > + sc->sc_node = aaa->aaa_node;
> > + printf(": %s", sc->sc_node->name);
> > +
> > + if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, &uid)) {
> > + printf(", can't find uid\n");
> > + return;
> > + }
> > +
> > + printf(" uid %lld", uid);
> > +
> > + switch (uid) {
> > + case 1:
> > + sc->sc_npins = 78;
> > + break;
> > + case 2:
> > + sc->sc_npins = 77;
> > + break;
> > + case 3:
> > + sc->sc_npins = 47;
> > + break;
> > + case 4:
> > + sc->sc_npins = 43;
> > + break;
> > + default:
> > + printf("\n");
> > + return;
> > + }
> > +
> > + if (aml_evalname(sc->sc_acpi, sc->sc_node, "_CRS", 0, NULL, &res)) {
> > + printf(", can't find registers\n");
> > + return;
> > + }
> > +
> > + aml_parse_resource(&res, aplgpio_parse_resources, sc);
> > + printf(" addr 0x%lx/0x%lx", sc->sc_addr, sc->sc_size);
> > + if (sc->sc_addr == 0 || sc->sc_size == 0) {
> > + printf("\n");
> > + return;
> > + }
> > + aml_freevalue(&res);
> > +
> > + sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih),
> > +    M_DEVBUF, M_NOWAIT | M_ZERO);
> > + if (sc->sc_pin_ih == NULL) {
> > + printf("\n");
> > + return;
> > + }
> > +
> > + printf(" irq %d", sc->sc_irq);
> > +
> > + sc->sc_memt = aaa->aaa_memt;
> > + if (bus_space_map(sc->sc_memt, sc->sc_addr, sc->sc_size, 0,
> > +    &sc->sc_memh)) {
> > + printf(", can't map registers\n");
> > + goto free;
> > + }
> > +
> > + sc->sc_ih = acpi_intr_establish(sc->sc_irq, sc->sc_irq_flags, IPL_BIO,
> > +    aplgpio_intr, sc, sc->sc_dev.dv_xname);
> > + if (sc->sc_ih == NULL) {
> > + printf(", can't establish interrupt\n");
> > + goto unmap;
> > + }
> > +
> > + sc->sc_gpio.cookie = sc;
> > + sc->sc_gpio.read_pin = aplgpio_read_pin;
> > + sc->sc_gpio.write_pin = aplgpio_write_pin;
> > + sc->sc_gpio.intr_establish = aplgpio_intr_establish;
> > + sc->sc_node->gpio = &sc->sc_gpio;
> > +
> > + /* Mask and clear all interrupts. */
> > + for (i = 0; i < sc->sc_npins; i++) {
> > + if (i % 32 == 0) {
> > + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_IRQ_EN + (i / 32) * 4, 0x00000000);
> > + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_IRQ_STS + (i / 32) * 4, 0xffffffff);
> > + }
> > + }
> > +
> > + printf(", %d pins\n", sc->sc_npins);
> > +
> > + acpi_register_gpio(sc->sc_acpi, sc->sc_node);
> > + return;
> > +
> > +unmap:
> > + bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size);
> > +free:
> > + free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih));
> > +}
> > +
> > +int
> > +aplgpio_parse_resources(int crsidx, union acpi_resource *crs, void *arg)
> > +{
> > + struct aplgpio_softc *sc = arg;
> > + int type = AML_CRSTYPE(crs);
> > +
> > + switch (type) {
> > + case LR_MEM32FIXED:
> > + sc->sc_addr = crs->lr_m32fixed._bas;
> > + sc->sc_size = crs->lr_m32fixed._len;
> > + break;
> > + case LR_EXTIRQ:
> > + sc->sc_irq = crs->lr_extirq.irq[0];
> > + sc->sc_irq_flags = crs->lr_extirq.flags;
> > + break;
> > + default:
> > + printf(" type 0x%x\n", type);
> > + break;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +int
> > +aplgpio_read_pin(void *cookie, int pin)
> > +{
> > + struct aplgpio_softc *sc = cookie;
> > + uint32_t reg;
> > +
> > + reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_PAD_CFG0 + pin * 8);
> > +
> > + return !!(reg & APLGPIO_CONF_RXSTATE);
> > +}
> > +
> > +void
> > +aplgpio_write_pin(void *cookie, int pin, int value)
> > +{
> > + struct aplgpio_softc *sc = cookie;
> > + uint32_t reg;
> > +
> > + reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_PAD_CFG0 + pin * 8);
> > + if (value)
> > + reg |= APLGPIO_CONF_TXSTATE;
> > + else
> > + reg &= ~APLGPIO_CONF_TXSTATE;
> > + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_PAD_CFG0 + pin * 8, reg);
> > +}
> > +
> > +void
> > +aplgpio_intr_establish(void *cookie, int pin, int flags,
> > +    int (*func)(void *), void *arg)
> > +{
> > + struct aplgpio_softc *sc = cookie;
> > + uint32_t reg;
> > +
> > + KASSERT(pin >= 0 && pin < sc->sc_npins);
> > +
> > + sc->sc_pin_ih[pin].ih_func = func;
> > + sc->sc_pin_ih[pin].ih_arg = arg;
> > +
> > + reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_PAD_CFG0 + pin * 8);
> > + reg &= ~(APLGPIO_CONF_RXEV_MASK | APLGPIO_CONF_RXINV);
> > + if ((flags & LR_GPIO_MODE) == 1)
> > + reg |= APLGPIO_CONF_RXEV_EDGE;
> > + if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO)
> > + reg |= APLGPIO_CONF_RXINV;
> > + if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH)
> > + reg |= APLGPIO_CONF_RXEV_EDGE | APLGPIO_CONF_RXEV_ZERO;
> > + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_PAD_CFG0 + pin * 8, reg);
> > +
> > + reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_IRQ_EN + (pin / 32) * 4);
> > + reg |= (1 << (pin % 32));
> > + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_IRQ_EN + (pin / 32) * 4, reg);
> > +}
> > +
> > +int
> > +aplgpio_intr(void *arg)
> > +{
> > + struct aplgpio_softc *sc = arg;
> > + uint32_t status, enable;
> > + int rc = 0;
> > + int pin;
> > +
> > + for (pin = 0; pin < sc->sc_npins; pin++) {
> > + if (pin % 32 == 0) {
> > + status = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_IRQ_STS + (pin / 32) * 4);
> > + bus_space_write_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_IRQ_STS + (pin / 32) * 4, status);
> > + enable = bus_space_read_4(sc->sc_memt, sc->sc_memh,
> > +    APLGPIO_IRQ_EN + (pin / 32) * 4);
> > + status &= enable;
> > + }
> > + if (status & (1 << (pin % 32))) {
> > + if (sc->sc_pin_ih[pin].ih_func)
> > + sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg);
> > + rc = 1;
> > + }
> > + }
> > + return rc;
> > +}
> > Index: sys/dev/acpi/files.acpi
> > ===================================================================
> > RCS file: /cvs/src/sys/dev/acpi/files.acpi,v
> > retrieving revision 1.50
> > diff -u -p -u -r1.50 files.acpi
> > --- sys/dev/acpi/files.acpi 23 Apr 2019 18:34:06 -0000 1.50
> > +++ sys/dev/acpi/files.acpi 17 Jun 2019 16:18:16 -0000
> > @@ -116,6 +116,11 @@ device aibs
> >  attach aibs at acpi
> >  file dev/acpi/atk0110.c aibs
> >  
> > +# Intel Apollo Lake GPIO
> > +device aplgpio
> > +attach aplgpio at acpi
> > +file dev/acpi/aplgpio.c aplgpio
> > +
> >  # Intel Bay Trail GPIO
> >  device bytgpio
> >  attach bytgpio at acpi
> >
> >
>