alc(4) support for Atheros AR815x

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alc(4) support for Atheros AR815x

Kevin Lo-3
Hi,

The following diff adds support for Atheros AR8151/AR8152 chipsets;
mostly from FreeBSD. It also fixes an issue i386/6311.
Tested on Acer AOD255E.

Index: share/man/man4/alc.4
===================================================================
RCS file: /cvs/src/share/man/man4/alc.4,v
retrieving revision 1.2
diff -u -p -r1.2 alc.4
--- share/man/man4/alc.4 8 Aug 2009 14:12:41 -0000 1.2
+++ share/man/man4/alc.4 25 Jan 2011 10:19:48 -0000
@@ -19,7 +19,7 @@
 .Os
 .Sh NAME
 .Nm alc
-.Nd Atheros AR8131/AR8132 10/100/Gigabit Ethernet device
+.Nd Atheros AR813x/AR815x 10/100/Gigabit Ethernet device
 .Sh SYNOPSIS
 .Cd "alc* at pci?"
 .Cd "atphy* at mii?"
@@ -27,8 +27,7 @@
 The
 .Nm
 driver provides support for Ethernet interfaces based on the
-Atheros AR8131/AR8132 Ethernet chipset, also known as
-the Attansic L1C/L2C respectively.
+Atheros AR813x/AR815x Ethernet chipset.
 .Pp
 The
 .Nm
Index: sys/arch/amd64/conf/GENERIC
===================================================================
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.312
diff -u -p -r1.312 GENERIC
--- sys/arch/amd64/conf/GENERIC 8 Jan 2011 11:56:30 -0000 1.312
+++ sys/arch/amd64/conf/GENERIC 25 Jan 2011 10:19:49 -0000
@@ -473,7 +473,7 @@ gem* at pci? # Sun 'gem' ethernet
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/arch/amd64/conf/RAMDISK_CD
===================================================================
RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
retrieving revision 1.115
diff -u -p -r1.115 RAMDISK_CD
--- sys/arch/amd64/conf/RAMDISK_CD 4 Aug 2010 21:44:41 -0000 1.115
+++ sys/arch/amd64/conf/RAMDISK_CD 25 Jan 2011 10:19:49 -0000
@@ -291,7 +291,7 @@ xge* at pci? # Neterion Xframe-I/II 10
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/arch/i386/conf/GENERIC
===================================================================
RCS file: /cvs/src/sys/arch/i386/conf/GENERIC,v
retrieving revision 1.708
diff -u -p -r1.708 GENERIC
--- sys/arch/i386/conf/GENERIC 15 Jan 2011 04:39:27 -0000 1.708
+++ sys/arch/i386/conf/GENERIC 25 Jan 2011 10:19:50 -0000
@@ -634,7 +634,7 @@ gem* at pci? # Sun 'gem' ethernet
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/arch/i386/conf/RAMDISK_CD
===================================================================
RCS file: /cvs/src/sys/arch/i386/conf/RAMDISK_CD,v
retrieving revision 1.183
diff -u -p -r1.183 RAMDISK_CD
--- sys/arch/i386/conf/RAMDISK_CD 15 Jan 2011 04:39:27 -0000 1.183
+++ sys/arch/i386/conf/RAMDISK_CD 25 Jan 2011 10:19:51 -0000
@@ -372,7 +372,7 @@ xge* at pci? # Neterion Xframe-I/II 1
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/dev/pci/files.pci
===================================================================
RCS file: /cvs/src/sys/dev/pci/files.pci,v
retrieving revision 1.277
diff -u -p -r1.277 files.pci
--- sys/dev/pci/files.pci 15 Jan 2011 04:35:34 -0000 1.277
+++ sys/dev/pci/files.pci 25 Jan 2011 10:19:54 -0000
@@ -643,7 +643,7 @@ device age: ether, ifnet, mii, ifmedia,
 attach age at pci
 file dev/pci/if_age.c age
 
-# Attansic/Atheros L1C/L2C Gigabit Ethernet
+# Attansic/Atheros L1C/L1D/L2C Gigabit Ethernet
 device alc: ether, ifnet, mii, ifmedia, mii_phy
 attach alc at pci
 file dev/pci/if_alc.c alc
Index: sys/dev/pci/if_alc.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_alc.c,v
retrieving revision 1.8
diff -u -p -r1.8 if_alc.c
--- sys/dev/pci/if_alc.c 31 Aug 2010 17:13:44 -0000 1.8
+++ sys/dev/pci/if_alc.c 25 Jan 2011 10:19:55 -0000
@@ -88,7 +88,7 @@ void alc_watchdog(struct ifnet *);
 int alc_mediachange(struct ifnet *);
 void alc_mediastatus(struct ifnet *, struct ifmediareq *);
 
-void alc_aspm(struct alc_softc *);
+void alc_aspm(struct alc_softc *, int);
 void alc_disable_l0s_l1(struct alc_softc *);
 int alc_dma_alloc(struct alc_softc *);
 void alc_dma_free(struct alc_softc *);
@@ -109,7 +109,7 @@ void alc_phy_down(struct alc_softc *);
 void alc_phy_reset(struct alc_softc *);
 void alc_reset(struct alc_softc *);
 void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
-int alc_rxintr(struct alc_softc *);
+void alc_rxintr(struct alc_softc *);
 void alc_iff(struct alc_softc *);
 void alc_rxvlan(struct alc_softc *);
 void alc_start_queue(struct alc_softc *);
@@ -125,7 +125,11 @@ uint32_t alc_dma_burst[] = { 128, 256, 5
 
 const struct pci_matchid alc_devices[] = {
  { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C },
- { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 }
 };
 
 struct cfattach alc_ca = {
@@ -236,8 +240,8 @@ alc_miibus_statchg(struct device *dev)
  reg = CSR_READ_4(sc, ALC_MAC_CFG);
  reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
  CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
+ alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active));
  }
- alc_aspm(sc);
 }
 
 void
@@ -280,20 +284,53 @@ void
 alc_get_macaddr(struct alc_softc *sc)
 {
  uint32_t ea[2], opt;
- int i;
+ uint16_t val;
+ int eeprom, i;
 
+ eeprom = 0;
  opt = CSR_READ_4(sc, ALC_OPT_CFG);
- if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
+ if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
+    (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
  /*
  * EEPROM found, let TWSI reload EEPROM configuration.
  * This will set ethernet address of controller.
  */
- if ((opt & OPT_CFG_CLK_ENB) == 0) {
- opt |= OPT_CFG_CLK_ENB;
- CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
- CSR_READ_4(sc, ALC_OPT_CFG);
- DELAY(1000);
+ eeprom++;
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1C:
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ if ((opt & OPT_CFG_CLK_ENB) == 0) {
+ opt |= OPT_CFG_CLK_ENB;
+ CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
+ CSR_READ_4(sc, ALC_OPT_CFG);
+ DELAY(1000);
+ }
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x00);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val & 0xFF7F);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x3B);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val | 0x0008);
+ DELAY(20);
+ break;
  }
+
+ CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
+    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
+ CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
+ CSR_READ_4(sc, ALC_WOL_CFG);
+
  CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
     TWSI_CFG_SW_LD_START);
  for (i = 100; i > 0; i--) {
@@ -309,11 +346,36 @@ alc_get_macaddr(struct alc_softc *sc)
  if (alcdebug)
  printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname);
  }
- if ((opt & OPT_CFG_CLK_ENB) != 0) {
- opt &= ~OPT_CFG_CLK_ENB;
- CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
- CSR_READ_4(sc, ALC_OPT_CFG);
- DELAY(1000);
+ if (eeprom != 0) {
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1C:
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ if ((opt & OPT_CFG_CLK_ENB) != 0) {
+ opt &= ~OPT_CFG_CLK_ENB;
+ CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
+ CSR_READ_4(sc, ALC_OPT_CFG);
+ DELAY(1000);
+ }
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x00);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val | 0x0080);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x3B);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val & 0xFFF7);
+ DELAY(20);
+ break;
+ }
  }
 
  ea[0] = CSR_READ_4(sc, ALC_PAR0);
@@ -358,6 +420,43 @@ alc_phy_reset(struct alc_softc *sc)
  CSR_READ_2(sc, ALC_GPHY_CFG);
  DELAY(10 * 1000);
 
+ /* DSP fixup, Vendor magic. */
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x000A);
+ data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, data & 0xDFFF);
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x003B);
+ data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, data & 0xFFF7);
+ DELAY(20 * 1000);
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x0029);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, 0x929D);
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x0029);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, 0xB6DD);
+ }
+
  /* Load DSP codes, vendor magic. */
  data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
     ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) &
ANA_INTERVAL_SEL_TIMER_MASK);
@@ -406,35 +505,114 @@ alc_phy_reset(struct alc_softc *sc)
 void
 alc_phy_down(struct alc_softc *sc)
 {
-
- /* Force PHY down. */
- CSR_WRITE_2(sc, ALC_GPHY_CFG,
-    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
-    GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW);
- DELAY(1000);
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ /*
+ * GPHY power down caused more problems on AR8151 v2.0.
+ * When driver is reloaded after GPHY power down,
+ * accesses to PHY/MAC registers hung the system. Only
+ * cold boot recovered from it.  I'm not sure whether
+ * AR8151 v1.0 also requires this one though.  I don't
+ * have AR8151 v1.0 controller in hand.
+ * The only option left is to isolate the PHY and
+ * initiates power down the PHY which in turn saves
+ * more power when driver is unloaded.
+ */
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    MII_BMCR, BMCR_ISO | BMCR_PDOWN);
+ break;
+ default:
+ /* Force PHY down. */
+ CSR_WRITE_2(sc, ALC_GPHY_CFG,
+    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
+    GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
+    GPHY_CFG_PWDOWN_HW);
+ DELAY(1000);
+ break;
+ }
 }
 
 void
-alc_aspm(struct alc_softc *sc)
+alc_aspm(struct alc_softc *sc, int media)
 {
  uint32_t pmcfg;
+ uint16_t linkcfg;
 
  pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
+ if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
+    (ALC_FLAG_APS | ALC_FLAG_PCIE))
+ linkcfg = CSR_READ_2(sc, sc->alc_expcap +
+    PCI_PCIE_LCSR);
+ else
+ linkcfg = 0;
  pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
- pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB;
- pmcfg |= PM_CFG_SERDES_L1_ENB;
- pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
+ pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
  pmcfg |= PM_CFG_MAC_ASPM_CHK;
+ pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
+ pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
+
+ if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
+ /* Disable extended sync except AR8152 B v1.0 */
+ linkcfg &= ~0x80;
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
+    sc->alc_rev == ATHEROS_AR8152_B_V10)
+ linkcfg |= 0x80;
+ CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR,
+    linkcfg);
+ pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
+    PM_CFG_HOTRST);
+ pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
+ pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
+    PM_CFG_PM_REQ_TIMER_SHIFT);
+ pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
+ }
+
  if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
- pmcfg |= PM_CFG_SERDES_PLL_L1_ENB;
- pmcfg &= ~PM_CFG_CLK_SWH_L1;
- pmcfg &= ~PM_CFG_ASPM_L1_ENB;
- pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
+ pmcfg |= PM_CFG_ASPM_L0S_ENB;
+ if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
+ pmcfg |= PM_CFG_ASPM_L1_ENB;
+ if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
+ pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
+    PM_CFG_SERDES_PLL_L1_ENB |
+    PM_CFG_SERDES_BUDS_RX_L1_ENB);
+ pmcfg |= PM_CFG_CLK_SWH_L1;
+ if (media == IFM_100_TX || media == IFM_1000_T) {
+ pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ pmcfg |= (7 <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ pmcfg |= (4 <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ break;
+ default:
+ pmcfg |= (15 <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ break;
+ }
+ }
+ } else {
+ pmcfg |= PM_CFG_SERDES_L1_ENB |
+    PM_CFG_SERDES_PLL_L1_ENB |
+    PM_CFG_SERDES_BUDS_RX_L1_ENB;
+ pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
+    PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
+ }
  } else {
- pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB;
+ pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
+    PM_CFG_SERDES_PLL_L1_ENB);
  pmcfg |= PM_CFG_CLK_SWH_L1;
- pmcfg &= ~PM_CFG_ASPM_L1_ENB;
- pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
+ pmcfg |= PM_CFG_ASPM_L1_ENB;
  }
  CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
 }
@@ -450,9 +628,9 @@ alc_attach(struct device *parent, struct
  const char *intrstr;
  struct ifnet *ifp;
  pcireg_t memtype;
- char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" };
+ char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
  uint16_t burst;
- int base, mii_flags, state, error = 0;
+ int base, state, error = 0;
  uint32_t cap, ctl, val;
 
  /*
@@ -499,6 +677,7 @@ alc_attach(struct device *parent, struct
  if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
     &base, NULL)) {
  sc->alc_flags |= ALC_FLAG_PCIE;
+ sc->alc_expcap = base;
  burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
     base + PCI_PCIE_DCSR) >> 16;
  sc->alc_dma_rd_burst = (burst & 0x7000) >> 12;
@@ -515,6 +694,20 @@ alc_attach(struct device *parent, struct
  val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
  val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
  CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
+ CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
+    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
+ CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
+    CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
+    PCIE_PHYMISC_FORCE_RCV_DET);
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
+    sc->alc_rev == ATHEROS_AR8152_B_V10) {
+ val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
+ val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
+    PCIE_PHYMISC2_SERDES_TH_MASK);
+ val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
+ val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
+ CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
+ }
  /* Disable ASPM L0S and L1. */
  cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
     base + PCI_PCIE_LCAP) >> 16;
@@ -528,13 +721,16 @@ alc_attach(struct device *parent, struct
     sc->sc_dev.dv_xname,
     sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
  state = ctl & 0x03;
+ if (state & 0x01)
+ sc->alc_flags |= ALC_FLAG_L0S;
+ if (state & 0x02)
+ sc->alc_flags |= ALC_FLAG_L1S;
  if (alcdebug)
  printf("%s: ASPM %s %s\n",
     sc->sc_dev.dv_xname,
     aspm_state[state],
     state == 0 ? "disabled" : "enabled");
- if (state != 0)
- alc_disable_l0s_l1(sc);
+ alc_disable_l0s_l1(sc);
  }
  }
 
@@ -551,12 +747,39 @@ alc_attach(struct device *parent, struct
  * used in AR8132 can't establish gigabit link even if it
  * shows the same PHY model/revision number of AR8131.
  */
- if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_L2C)
- sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO;
- else
- sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON;
+ sc->sc_product = PCI_PRODUCT(pa->pa_id);
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ sc->alc_flags |= ALC_FLAG_APS;
+ /* FALLTHROUGH */
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ sc->alc_flags |= ALC_FLAG_FASTETHER;
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ sc->alc_flags |= ALC_FLAG_APS;
+ /* FALLTHROUGH */
+ default:
+ break;
+ }
+ sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO;
+
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1C:
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ sc->alc_max_framelen = 9 * 1024;
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ sc->alc_max_framelen = 6 * 1024;
+ break;
+ }
+
  /*
- * It seems that AR8131/AR8132 has silicon bug for SMB. In
+ * It seems that AR813x/AR815x has silicon bug for SMB. In
  * addition, Atheros said that enabling SMB wouldn't improve
  * performance. However I think it's bad to access lots of
  * registers to extract MAC statistics.
@@ -619,11 +842,8 @@ alc_attach(struct device *parent, struct
 
  ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange,
     alc_mediastatus);
- mii_flags = 0;
- if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0)
- mii_flags |= MIIF_DOPAUSE;
  mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY,
- MII_OFFSET_ANY, mii_flags);
+ MII_OFFSET_ANY, MIIF_DOPAUSE);
 
  if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) {
  printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
@@ -1136,16 +1356,15 @@ alc_start(struct ifnet *ifp)
 {
  struct alc_softc *sc = ifp->if_softc;
  struct mbuf *m_head;
- int enq;
-
- if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
- return;
+ int enq = 0;
 
  /* Reclaim transmitted frames. */
  if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
  alc_txeof(sc);
 
- enq = 0;
+ if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
+ return;
+
  for (;;) {
  IFQ_DEQUEUE(&ifp->if_snd, m_head);
  if (m_head == NULL)
@@ -1162,7 +1381,7 @@ alc_start(struct ifnet *ifp)
  ifp->if_flags |= IFF_OACTIVE;
  break;
  }
- enq = 1;
+ enq++;
 
 #if NBPFILTER > 0
  /*
@@ -1174,7 +1393,7 @@ alc_start(struct ifnet *ifp)
 #endif
  }
 
- if (enq) {
+ if (enq > 0) {
  /* Sync descriptors. */
  bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
     sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
@@ -1274,6 +1493,10 @@ alc_mac_config(struct alc_softc *sc)
  reg = CSR_READ_4(sc, ALC_MAC_CFG);
  reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
     MAC_CFG_SPEED_MASK);
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
+ reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
  /* Reprogram MAC with resolved speed/duplex. */
  switch (IFM_SUBTYPE(mii->mii_media_active)) {
  case IFM_10_T:
@@ -1451,24 +1674,25 @@ alc_intr(void *arg)
  struct alc_softc *sc = arg;
  struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  uint32_t status;
+ int claimed = 0;
 
  status = CSR_READ_4(sc, ALC_INTR_STATUS);
  if ((status & ALC_INTRS) == 0)
  return (0);
 
+ /* Disable interrupts. */
+ CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
+
+ status = CSR_READ_4(sc, ALC_INTR_STATUS);
+ if ((status & ALC_INTRS) == 0)
+ goto back;
+
  /* Acknowledge and disable interrupts. */
  CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
 
  if (ifp->if_flags & IFF_RUNNING) {
- if (status & INTR_RX_PKT) {
- int error;
-
- error = alc_rxintr(sc);
- if (error) {
- alc_init(ifp);
- return (0);
- }
- }
+ if (status & INTR_RX_PKT)
+ alc_rxintr(sc);
 
  if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
     INTR_TXQ_TO_RST)) {
@@ -1485,14 +1709,17 @@ alc_intr(void *arg)
  return (0);
  }
 
- alc_txeof(sc);
- if (!IFQ_IS_EMPTY(&ifp->if_snd))
+ if (status & INTR_TX_PKT) {
+ alc_txeof(sc);
+    if (!IFQ_IS_EMPTY(&ifp->if_snd))
  alc_start(ifp);
+ }
  }
-
+ claimed = 1;
+back:
  /* Re-enable interrupts. */
  CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
- return (1);
+ return (claimed);
 }
 
 void
@@ -1507,7 +1734,7 @@ alc_txeof(struct alc_softc *sc)
  return;
  bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
     sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
-    BUS_DMASYNC_POSTREAD);
+    BUS_DMASYNC_POSTWRITE);
  if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
  bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
     sc->alc_cdata.alc_cmb_map->dm_mapsize,
@@ -1601,7 +1828,7 @@ alc_newbuf(struct alc_softc *sc, struct
  return (0);
 }
 
-int
+void
 alc_rxintr(struct alc_softc *sc)
 {
  struct ifnet *ifp = &sc->sc_arpcom.ac_if;
@@ -1625,7 +1852,7 @@ alc_rxintr(struct alc_softc *sc)
  if (alcdebug)
  printf("%s: unexpected segment count -- "
     "resetting\n", sc->sc_dev.dv_xname);
- return (EIO);
+ break;
  }
  alc_rxeof(sc, rrd);
  /* Clear Rx return status. */
@@ -1663,8 +1890,6 @@ alc_rxintr(struct alc_softc *sc)
  CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
     sc->alc_cdata.alc_rx_cons);
  }
-
- return (0);
 }
 
 /* Receive a frame. */
@@ -1696,9 +1921,8 @@ alc_rxeof(struct alc_softc *sc, struct r
  *  Force network stack compute checksum for
  *  errored frames.
  */
- status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
- if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC |
-    RRD_ERR_RUNT) != 0)
+ if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN |
+    RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0)
  return;
  }
 
@@ -1811,7 +2035,9 @@ alc_reset(struct alc_softc *sc)
  uint32_t reg;
  int i;
 
- CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET);
+ reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF;
+ reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
+ CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
  for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
  DELAY(10);
  if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
@@ -1862,6 +2088,9 @@ alc_init(struct ifnet *ifp)
  alc_init_cmb(sc);
  alc_init_smb(sc);
 
+ /* Enable all clocks. */
+ CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
+
  /* Reprogram the station address. */
  bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN);
  CSR_WRITE_4(sc, ALC_PAR0,
@@ -1923,6 +2152,18 @@ alc_init(struct ifnet *ifp)
  CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
  CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
 
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
+ /* Reconfigure SRAM - Vendor magic. */
+ CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
+ CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
+ CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
+ CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
+ CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
+ CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
+ CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
+ CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
+ }
+
  /* Tell hardware that we're ready to load DMA blocks. */
  CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
 
@@ -1932,14 +2173,11 @@ alc_init(struct ifnet *ifp)
  reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
  reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
  CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
- reg = CSR_READ_4(sc, ALC_MASTER_CFG);
- reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
  /*
  * We don't want to automatic interrupt clear as task queue
  * for the interrupt should know interrupt status.
  */
- reg &= ~MASTER_INTR_RD_CLR;
- reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
+ reg = MASTER_SA_TIMER_ENB;
  if (ALC_USECS(sc->alc_int_rx_mod) != 0)
  reg |= MASTER_IM_RX_TIMER_ENB;
  if (ALC_USECS(sc->alc_int_tx_mod) != 0)
@@ -1980,7 +2218,7 @@ alc_init(struct ifnet *ifp)
  * Be conservative in what you do, be liberal in what you
  * accept from others - RFC 793.
  */
- CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN);
+ CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen);
 
  /* Disable header split(?) */
  CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
@@ -2007,11 +2245,14 @@ alc_init(struct ifnet *ifp)
  * TSO/checksum offloading.
  */
  CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
-    (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
+    (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
     TSO_OFFLOAD_THRESH_MASK);
  /* Configure TxQ. */
  reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
     TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
+ reg >>= 1;
  reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
     TXQ_CFG_TD_BURST_MASK;
  CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
@@ -2028,14 +2269,22 @@ alc_init(struct ifnet *ifp)
  * XON  : 80% of Rx FIFO
  * XOFF : 30% of Rx FIFO
  */
- reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
- rxf_hi = (reg * 8) / 10;
- rxf_lo = (reg * 3)/ 10;
- CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
-    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
-    RX_FIFO_PAUSE_THRESH_LO_MASK) |
-    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
-     RX_FIFO_PAUSE_THRESH_HI_MASK));
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) {
+ reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
+ rxf_hi = (reg * 8) / 10;
+ rxf_lo = (reg * 3) / 10;
+ CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
+    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
+    RX_FIFO_PAUSE_THRESH_LO_MASK) |
+    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
+    RX_FIFO_PAUSE_THRESH_HI_MASK));
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
+ CSR_WRITE_4(sc, ALC_SERDES_LOCK,
+    CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
+    SERDES_PHY_CLK_SLOWDOWN);
 
  /* Disable RSS until I understand L1C/L2C's RSS logic. */
  CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
@@ -2046,15 +2295,9 @@ alc_init(struct ifnet *ifp)
     RXQ_CFG_RD_BURST_MASK;
  reg |= RXQ_CFG_RSS_MODE_DIS;
  if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
- reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
+ reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
  CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
 
- /* Configure Rx DMAW request thresold. */
- CSR_WRITE_4(sc, ALC_RD_DMA_CFG,
-    ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) &
-    RD_DMA_CFG_THRESH_MASK) |
-    ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) &
-    RD_DMA_CFG_TIMER_MASK));
  /* Configure DMA parameters. */
  reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
  reg |= sc->alc_rcb;
@@ -2080,7 +2323,7 @@ alc_init(struct ifnet *ifp)
  *  - Enable CRC generation.
  *  Actual reconfiguration of MAC for resolved speed/duplex
  *  is followed after detection of link establishment.
- *  AR8131/AR8132 always does checksum computation regardless
+ *  AR813x/AR815x always does checksum computation regardless
  *  of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
  *  have bug in protocol field in Rx return structure so
  *  these controllers can't handle fragmented frames. Disable
@@ -2090,6 +2333,10 @@ alc_init(struct ifnet *ifp)
  reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
     ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
     MAC_CFG_PREAMBLE_MASK);
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
+ reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
  if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
  reg |= MAC_CFG_SPEED_10_100;
  else
@@ -2191,7 +2438,7 @@ alc_stop_mac(struct alc_softc *sc)
  /* Disable Rx/Tx MAC. */
  reg = CSR_READ_4(sc, ALC_MAC_CFG);
  if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
- reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
+ reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
  CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
  }
  for (i = ALC_TIMEOUT; i > 0; i--) {
Index: sys/dev/pci/if_alcreg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_alcreg.h,v
retrieving revision 1.1
diff -u -p -r1.1 if_alcreg.h
--- sys/dev/pci/if_alcreg.h 8 Aug 2009 09:31:13 -0000 1.1
+++ sys/dev/pci/if_alcreg.h 25 Jan 2011 10:19:56 -0000
@@ -31,7 +31,10 @@
 #ifndef _IF_ALCREG_H
 #define _IF_ALCREG_H
 
-#define ALC_PCIR_BAR 0x10
+#define ALC_PCIR_BAR 0x10
+
+#define ATHEROS_AR8152_B_V10 0xC0
+#define ATHEROS_AR8152_B_V11 0xC1
 
 /* 0x0000 - 0x02FF : PCIe configuration space */
 
@@ -56,6 +59,12 @@
 #define ALC_PCIE_PHYMISC 0x1000
 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
 
+#define ALC_PCIE_PHYMISC2 0x1004
+#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
+#define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
+#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
+#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
+
 #define ALC_TWSI_DEBUG 0x1108
 #define TWSI_DEBUG_DEV_EXIST 0x20000000
 
@@ -88,7 +97,9 @@
 #define PM_CFG_PCIE_RECV 0x00008000
 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
-#define PM_CFG_LCKDET_TIMER_MASK 0x3F000000
+#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
+#define PM_CFG_EN_BUFS_RX_L0S 0x10000000
+#define PM_CFG_SA_DLY_ENB 0x20000000
 #define PM_CFG_MAC_ASPM_CHK 0x40000000
 #define PM_CFG_HOTRST 0x80000000
 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8
@@ -96,10 +107,20 @@
 #define PM_CFG_PM_REQ_TIMER_SHIFT 20
 #define PM_CFG_LCKDET_TIMER_SHIFT 24
 
+#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
+#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1
+#define PM_CFG_LCKDET_TIMER_DEFAULT 12
+#define PM_CFG_PM_REQ_TIMER_DEFAULT 12
+
+#define ALC_LTSSM_ID_CFG 0x12FC
+#define LTSSM_ID_WRO_ENB 0x00001000
+
 #define ALC_MASTER_CFG 0x1400
 #define MASTER_RESET 0x00000001
+#define MASTER_TEST_MODE_MASK 0x0000000C
 #define MASTER_BERT_START 0x00000010
-#define MASTER_TEST_MODE_MASK 0x000000C0
+#define MASTER_OOB_DIS_OFF 0x00000040
+#define MASTER_SA_TIMER_ENB 0x00000080
 #define MASTER_MTIMER_ENB 0x00000100
 #define MASTER_MANUAL_INTR_ENB 0x00000200
 #define MASTER_IM_TX_TIMER_ENB 0x00000400
@@ -114,7 +135,7 @@
 #define MASTER_CHIP_REV_SHIFT 16
 #define MASTER_CHIP_ID_SHIFT 24
 
-/* Number of ticks per usec for AR8131/AR8132. */
+/* Number of ticks per usec for AR813x/AR815x. */
 #define ALC_TICK_USECS 2
 #define ALC_USECS(x) ((x) / ALC_TICK_USECS)
 
@@ -136,7 +157,7 @@
  * alc(4) does not rely on Tx completion interrupts, so set it
  * somewhat large value to reduce Tx completion interrupts.
  */
-#define ALC_IM_TX_TIMER_DEFAULT 50000 /* 50ms */
+#define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */
 
 #define ALC_GPHY_CFG 0x140C /* 16bits */
 #define GPHY_CFG_EXT_RESET 0x0001
@@ -212,6 +233,8 @@
 #define ALC_SERDES_LOCK 0x1424
 #define SERDES_LOCK_DET 0x00000001
 #define SERDES_LOCK_DET_ENB 0x00000002
+#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
+#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
 
 #define ALC_MAC_CFG 0x1480
 #define MAC_CFG_TX_ENB 0x00000001
@@ -241,6 +264,8 @@
 #define MAC_CFG_BCAST 0x04000000
 #define MAC_CFG_DBG 0x08000000
 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
+#define MAC_CFG_HASH_ALG_CRC32 0x20000000
+#define MAC_CFG_SPEED_MODE_SW 0x40000000
 #define MAC_CFG_PREAMBLE_SHIFT 10
 #define MAC_CFG_PREAMBLE_DEFAULT 7
 
@@ -683,11 +708,19 @@
 #define HDS_CFG_BACKFILLSIZE_SHIFT 8
 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20
 
-/* AR8131/AR8132 registers for MAC statistics */
+/* AR813x/AR815x registers for MAC statistics */
 #define ALC_RX_MIB_BASE 0x1700
 
 #define ALC_TX_MIB_BASE 0x1760
 
+#define ALC_CLK_GATING_CFG 0x1814
+#define CLK_GATING_DMAW_ENB 0x0001
+#define CLK_GATING_DMAR_ENB 0x0002
+#define CLK_GATING_TXQ_ENB 0x0004
+#define CLK_GATING_RXQ_ENB 0x0008
+#define CLK_GATING_TXMAC_ENB 0x0010
+#define CLK_GATING_RXMAC_ENB 0x0020
+
 #define ALC_DEBUG_DATA0 0x1900
 
 #define ALC_DEBUG_DATA1 0x1904
@@ -1112,6 +1145,7 @@ struct alc_softc {
  bus_dma_tag_t sc_dmat;
  pci_chipset_tag_t sc_pct;
  pcitag_t sc_pcitag;
+ pci_vendor_id_t sc_product;
 
  void *sc_irq_handle;
 
@@ -1120,19 +1154,23 @@ struct alc_softc {
  int alc_chip_rev;
  int alc_phyaddr;
  uint8_t alc_eaddr[ETHER_ADDR_LEN];
+ uint32_t alc_max_framelen;
  uint32_t alc_dma_rd_burst;
  uint32_t alc_dma_wr_burst;
  uint32_t alc_rcb;
+ int alc_expcap;
  int alc_flags;
 #define ALC_FLAG_PCIE 0x0001
 #define ALC_FLAG_PCIX 0x0002
-#define ALC_FLAG_MSI 0x0004
-#define ALC_FLAG_MSIX 0x0008
+#define ALC_FLAG_PM 0x0010
 #define ALC_FLAG_FASTETHER 0x0020
 #define ALC_FLAG_JUMBO 0x0040
 #define ALC_FLAG_ASPM_MON 0x0080
 #define ALC_FLAG_CMB_BUG 0x0100
 #define ALC_FLAG_SMB_BUG 0x0200
+#define ALC_FLAG_L0S 0x0400
+#define ALC_FLAG_L1S 0x0800
+#define ALC_FLAG_APS 0x1000
 #define ALC_FLAG_DETACH 0x4000
 #define ALC_FLAG_LINK 0x8000
 
Index: sys/dev/pci/pcidevs
===================================================================
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1588
diff -u -p -r1.1588 pcidevs
--- sys/dev/pci/pcidevs 19 Jan 2011 10:56:37 -0000 1.1588
+++ sys/dev/pci/pcidevs 25 Jan 2011 10:19:59 -0000
@@ -1429,6 +1429,10 @@ product ATTANSIC L1 0x1048 L1
 product ATTANSIC L2C 0x1062 L2C
 product ATTANSIC L1C 0x1063 L1C
 product ATTANSIC L2 0x2048 L2
+product ATTANSIC L1D 0x1073 L1D
+product ATTANSIC L1D_1 0x1083 L1D
+product ATTANSIC L2C_1 0x2060 L2C
+product ATTANSIC L2C_2 0x2062 L2C
 
 /* Aureal products */
 product AUREAL AU8820 0x0001 Vortex 1

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Re: alc(4) support for Atheros AR815x

damien.bergamini
See my comments inline.

Damien

|  void
| -alc_aspm(struct alc_softc *sc)
| +alc_aspm(struct alc_softc *sc, int media)
|  {
|   uint32_t pmcfg;
| + uint16_t linkcfg;
|  
|   pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
| + if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
| +    (ALC_FLAG_APS | ALC_FLAG_PCIE))
| + linkcfg = CSR_READ_2(sc, sc->alc_expcap +
| +    PCI_PCIE_LCSR);

You should probably use pci_conf_read() here.
Just turn linkcfg into a pcireg_t.


| + else
| + linkcfg = 0;
|   pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
| - pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB;
| - pmcfg |= PM_CFG_SERDES_L1_ENB;
| - pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
| + pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
|   pmcfg |= PM_CFG_MAC_ASPM_CHK;
| + pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT <<
| PM_CFG_LCKDET_TIMER_SHIFT);
| + pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
| +
| + if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
| + /* Disable extended sync except AR8152 B v1.0 */
| + linkcfg &= ~0x80;
| + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
| +    sc->alc_rev == ATHEROS_AR8152_B_V10)
| + linkcfg |= 0x80;

I recently added the definition of the "Extended Synch" bit to pcireg.h
so you could use PCI_PCIE_LCSR_ES instead of 0x80 here.


| + CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR,
| +    linkcfg);

and use pci_conf_write() here.


| + pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
| +    PM_CFG_HOTRST);
| + pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
| +    PM_CFG_L1_ENTRY_TIMER_SHIFT);
| + pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
| + pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
| +    PM_CFG_PM_REQ_TIMER_SHIFT);
| + pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
| + }
| +
|   if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
| - pmcfg |= PM_CFG_SERDES_PLL_L1_ENB;
| - pmcfg &= ~PM_CFG_CLK_SWH_L1;
| - pmcfg &= ~PM_CFG_ASPM_L1_ENB;
| - pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
| + if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
| + pmcfg |= PM_CFG_ASPM_L0S_ENB;
| + if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
| + pmcfg |= PM_CFG_ASPM_L1_ENB;
| + if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
| + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
| + pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
| + pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
| +    PM_CFG_SERDES_PLL_L1_ENB |
| +    PM_CFG_SERDES_BUDS_RX_L1_ENB);
| + pmcfg |= PM_CFG_CLK_SWH_L1;
| + if (media == IFM_100_TX || media == IFM_1000_T) {
| + pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
| + switch (sc->sc_product) {
| + case PCI_PRODUCT_ATTANSIC_L2C_1:
| + pmcfg |= (7 <<
| +    PM_CFG_L1_ENTRY_TIMER_SHIFT);
| + break;
| + case PCI_PRODUCT_ATTANSIC_L1D_1:
| + case PCI_PRODUCT_ATTANSIC_L2C_2:
| + pmcfg |= (4 <<
| +    PM_CFG_L1_ENTRY_TIMER_SHIFT);
| + break;
| + default:
| + pmcfg |= (15 <<
| +    PM_CFG_L1_ENTRY_TIMER_SHIFT);
| + break;
| + }
| + }
| + } else {
| + pmcfg |= PM_CFG_SERDES_L1_ENB |
| +    PM_CFG_SERDES_PLL_L1_ENB |
| +    PM_CFG_SERDES_BUDS_RX_L1_ENB;
| + pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
| +    PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
| + }
|   } else {
| - pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB;
| + pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
| +    PM_CFG_SERDES_PLL_L1_ENB);
|   pmcfg |= PM_CFG_CLK_SWH_L1;
| - pmcfg &= ~PM_CFG_ASPM_L1_ENB;
| - pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
| + if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
| + pmcfg |= PM_CFG_ASPM_L1_ENB;
|   }
|   CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
|  }

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Re: alc(4) support for Atheros AR815x

Gabriel Linder
In reply to this post by Kevin Lo-3
On 01/25/11 11:24, Kevin Lo wrote:
> Hi,
>
> The following diff adds support for Atheros AR8151/AR8152 chipsets;
> mostly from FreeBSD. It also fixes an issue i386/6311.
> Tested on Acer AOD255E.

Tried yesterday on EeePC 1005PX, some comments inline.

> @@ -515,6 +694,20 @@ alc_attach(struct device *parent, struct
>   val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
>   val&= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
>   CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
> + CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
> +    CSR_READ_4(sc, ALC_LTSSM_ID_CFG)&  ~LTSSM_ID_WRO_ENB);
> + CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
> +    CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
> +    PCIE_PHYMISC_FORCE_RCV_DET);
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1&&
> +    sc->alc_rev == ATHEROS_AR8152_B_V10) {

Using sc->sc_product and sc->alc_rev, but they are initialized later.

> @@ -551,12 +747,39 @@ alc_attach(struct device *parent, struct
>   * used in AR8132 can't establish gigabit link even if it
>   * shows the same PHY model/revision number of AR8131.
>   */
> - if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_L2C)
> - sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO;
> - else
> - sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON;
> + sc->sc_product = PCI_PRODUCT(pa->pa_id);

Here is sc->sc_product, sc->alc_rev initialized line 569 of if_alc.c r1.9

alc_newbuf should always use M_DONTWAIT (get rid of init), see
http://marc.info/?l=openbsd-tech&m=129639859909043&w=2

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Re: alc(4) support for Atheros AR815x

Jonathan Gray
In reply to this post by Kevin Lo-3
On Tue, Jan 25, 2011 at 06:24:28PM +0800, Kevin Lo wrote:
> Hi,
>
> The following diff adds support for Atheros AR8151/AR8152 chipsets;
> mostly from FreeBSD. It also fixes an issue i386/6311.
> Tested on Acer AOD255E.

Is there an updated diff for this?  It seems this never made it
into the tree.

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Re: alc(4) support for Atheros AR815x

Edd Barrett
On Thu, Apr 28, 2011 at 07:21:16AM +1000, Jonathan Gray wrote:
> On Tue, Jan 25, 2011 at 06:24:28PM +0800, Kevin Lo wrote:
> > Hi,
> >
> > The following diff adds support for Atheros AR8151/AR8152 chipsets;
> > mostly from FreeBSD. It also fixes an issue i386/6311.
> > Tested on Acer AOD255E.
>
> Is there an updated diff for this?  It seems this never made it
> into the tree.

I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
there an updated diff?

Dmesg:

OpenBSD 4.9-current (RAMDISK_CD) #41: Thu Apr 21 00:17:13 MDT 2011
    [hidden email]:/usr/src/sys/arch/i386/compile/RAMDISK_CD
cpu0: Intel(R) Atom(TM) CPU N455 @ 1.66GHz ("GenuineIntel" 686-class) 1.67 GHz
cpu0: FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,EST,TM2,SSSE3,CX16,xTPR,PDCM,MOVBE
real mem  = 1061335040 (1012MB)
avail mem = 1036996608 (988MB)
mainbus0 at root
bios0 at mainbus0: AT/286+ BIOS, date 01/10/11, SMBIOS rev. 2.6 @ 0xe8080 (36 entries)
bios0: vendor Packard Bell version "V3.14(DDR3)" date 01/10/2011
bios0: Packard Bell DOTS E2
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP HPET APIC MCFG SLIC BOOT SSDT WDAT
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: apic clock running at 166MHz
cpu at mainbus0: not configured
ioapic0 at mainbus0: apid 4 pa 0xfec00000, version 20, 24 pins
ioapic0: misconfigured as apic 0, remapped to apid 4
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus 1 (EXP1)
acpiprt2 at acpi0: bus 2 (EXP2)
acpiprt3 at acpi0: bus -1 (EXP3)
acpiprt4 at acpi0: bus -1 (EXP4)
bios0: ROM list: 0xc0000/0xda00! 0xce000/0x1000
pci0 at mainbus0 bus 0: configuration mode 1 (bios)
pchb0 at pci0 dev 0 function 0 "Intel Pineview DMI" rev 0x00
vga1 at pci0 dev 2 function 0 "Intel Pineview Video" rev 0x00
wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation)
"Intel Pineview Video" rev 0x00 at pci0 dev 2 function 1 not configured
"Intel 82801GB HD Audio" rev 0x02 at pci0 dev 27 function 0 not configured
ppb0 at pci0 dev 28 function 0 "Intel 82801GB PCIE" rev 0x02: apic 4 int 16 (irq 255)
pci1 at ppb0 bus 1
"Attansic Technology L2C" rev 0xc1 at pci1 dev 0 function 0 not configured
ppb1 at pci0 dev 28 function 1 "Intel 82801GB PCIE" rev 0x02: apic 4 int 17 (irq 255)
pci2 at ppb1 bus 2
"Broadcom BCM4313" rev 0x01 at pci2 dev 0 function 0 not configured
uhci0 at pci0 dev 29 function 0 "Intel 82801GB USB" rev 0x02: apic 4 int 18 (irq 11)
uhci1 at pci0 dev 29 function 1 "Intel 82801GB USB" rev 0x02: apic 4 int 20 (irq 10)
uhci2 at pci0 dev 29 function 2 "Intel 82801GB USB" rev 0x02: apic 4 int 21 (irq 11)
uhci3 at pci0 dev 29 function 3 "Intel 82801GB USB" rev 0x02: apic 4 int 22 (irq 11)
ehci0 at pci0 dev 29 function 7 "Intel 82801GB USB" rev 0x02: apic 4 int 22 (irq 11)
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Intel EHCI root hub" rev 2.00/1.00 addr 1
ppb2 at pci0 dev 30 function 0 "Intel 82801BAM Hub-to-PCI" rev 0xe2
pci3 at ppb2 bus 5
pcib0 at pci0 dev 31 function 0 "Intel Tigerpoint LPC" rev 0x02
ahci0 at pci0 dev 31 function 2 "Intel 82801GR AHCI" rev 0x02: apic 4 int 17 (irq 10), AHCI 1.1
ahci0: PHY offline on port 1
scsibus0 at ahci0: 32 targets
sd0 at scsibus0 targ 0 lun 0: <ATA, Hitachi HTS54502, PB2O> SCSI3 0/direct fixed naa.5000cca62bf2b42f
sd0: 238475MB, 512 bytes/sec, 488397168 sec total
"Intel 82801GB SMBus" rev 0x02 at pci0 dev 31 function 3 not configured
usb1 at uhci0: USB revision 1.0
uhub1 at usb1 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb2 at uhci1: USB revision 1.0
uhub2 at usb2 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb3 at uhci2: USB revision 1.0
uhub3 at usb3 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb4 at uhci3: USB revision 1.0
uhub4 at usb4 "Intel UHCI root hub" rev 1.00/1.00 addr 1
isa0 at pcib0
isadma0 at isa0
pckbc0 at isa0 port 0x60/5
pckbd0 at pckbc0 (kbd slot)
pckbc0: using irq 1 for kbd slot
wskbd0 at pckbd0: console keyboard, using wsdisplay0
npx0 at isa0 port 0xf0/16: reported by CPUID; using exception 16
rd0: fixed, 3872 blocks
"Y2B2D0JXB WebCam" rev 2.00/0.04 addr 2 at uhub0 port 4 not configured
softraid0 at root
PXE boot MAC address 1c:75:08:d5:53:c4, interface unknown
root on rd0a swap on rd0b dump on rd0b
umass0 at uhub1 port 2 configuration 1 interface 0 "vendor 0x0204 product 0x6025" rev 1.10/1.00 addr 2
umass0: using SCSI over Bulk-Only
scsibus1 at umass0: 2 targets, initiator 0
sd1 at scsibus1 targ 1 lun 0: <CBM, Flash Disk, 2.00> SCSI2 0/direct removable
sd1: 486MB, 512 bytes/sec, 996415 sec total

--
Best Regards
Edd Barrett

http://www.theunixzoo.co.uk

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Re: alc(4) support for Atheros AR815x

Stuart Henderson
On 2011/05/01 18:35, Edd Barrett wrote:
> I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
> there an updated diff?

Yes I just took the 2 minutes it took to apply it and fix
the minor conflicts and linewrapping issue with the diff.
Untested beyond "it builds".

Test reports and dmesg lines from existing working alc(4) L1C and
L2C wanted. If it makes new chips work that's a bonus, but the
important thing is making sure it doesn't break something that
already works.

Doesn't seem any point disabling interrupts in the ISR though.
I haven't touched that in this diff but that should probably be
done too.

Index: share/man/man4/alc.4
===================================================================
RCS file: /cvs/src/share/man/man4/alc.4,v
retrieving revision 1.2
diff -u -p -r1.2 alc.4
--- share/man/man4/alc.4 8 Aug 2009 14:12:41 -0000 1.2
+++ share/man/man4/alc.4 1 May 2011 18:55:25 -0000
@@ -19,7 +19,7 @@
 .Os
 .Sh NAME
 .Nm alc
-.Nd Atheros AR8131/AR8132 10/100/Gigabit Ethernet device
+.Nd Atheros AR813x/AR815x 10/100/Gigabit Ethernet device
 .Sh SYNOPSIS
 .Cd "alc* at pci?"
 .Cd "atphy* at mii?"
@@ -27,8 +27,7 @@
 The
 .Nm
 driver provides support for Ethernet interfaces based on the
-Atheros AR8131/AR8132 Ethernet chipset, also known as
-the Attansic L1C/L2C respectively.
+Atheros AR813x/AR815x Ethernet chipset.
 .Pp
 The
 .Nm
Index: sys/arch/amd64/conf/GENERIC
===================================================================
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.316
diff -u -p -r1.316 GENERIC
--- sys/arch/amd64/conf/GENERIC 10 Apr 2011 20:27:02 -0000 1.316
+++ sys/arch/amd64/conf/GENERIC 1 May 2011 18:55:25 -0000
@@ -472,7 +472,7 @@ bce* at pci? # Broadcom BCM4401
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/arch/amd64/conf/RAMDISK_CD
===================================================================
RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
retrieving revision 1.116
diff -u -p -r1.116 RAMDISK_CD
--- sys/arch/amd64/conf/RAMDISK_CD 3 Apr 2011 12:32:05 -0000 1.116
+++ sys/arch/amd64/conf/RAMDISK_CD 1 May 2011 18:55:25 -0000
@@ -291,7 +291,7 @@ bce* at pci? # Broadcom BCM4401
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/arch/i386/conf/GENERIC
===================================================================
RCS file: /cvs/src/sys/arch/i386/conf/GENERIC,v
retrieving revision 1.713
diff -u -p -r1.713 GENERIC
--- sys/arch/i386/conf/GENERIC 10 Apr 2011 20:27:02 -0000 1.713
+++ sys/arch/i386/conf/GENERIC 1 May 2011 18:55:25 -0000
@@ -632,7 +632,7 @@ gem* at pci? # Sun 'gem' ethernet
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/arch/i386/conf/RAMDISK_CD
===================================================================
RCS file: /cvs/src/sys/arch/i386/conf/RAMDISK_CD,v
retrieving revision 1.185
diff -u -p -r1.185 RAMDISK_CD
--- sys/arch/i386/conf/RAMDISK_CD 3 Apr 2011 12:32:05 -0000 1.185
+++ sys/arch/i386/conf/RAMDISK_CD 1 May 2011 18:55:25 -0000
@@ -372,7 +372,7 @@ xge* at pci? # Neterion Xframe-I/II 1
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/dev/pci/files.pci
===================================================================
RCS file: /cvs/src/sys/dev/pci/files.pci,v
retrieving revision 1.278
diff -u -p -r1.278 files.pci
--- sys/dev/pci/files.pci 10 Apr 2011 20:27:02 -0000 1.278
+++ sys/dev/pci/files.pci 1 May 2011 18:55:25 -0000
@@ -643,7 +643,7 @@ device age: ether, ifnet, mii, ifmedia,
 attach age at pci
 file dev/pci/if_age.c age
 
-# Attansic/Atheros L1C/L2C Gigabit Ethernet
+# Attansic/Atheros L1C/L1D/L2C Gigabit Ethernet
 device alc: ether, ifnet, mii, ifmedia, mii_phy
 attach alc at pci
 file dev/pci/if_alc.c alc
Index: sys/dev/pci/if_alc.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_alc.c,v
retrieving revision 1.11
diff -u -p -r1.11 if_alc.c
--- sys/dev/pci/if_alc.c 5 Apr 2011 18:01:21 -0000 1.11
+++ sys/dev/pci/if_alc.c 1 May 2011 18:55:25 -0000
@@ -88,7 +88,7 @@ void alc_watchdog(struct ifnet *);
 int alc_mediachange(struct ifnet *);
 void alc_mediastatus(struct ifnet *, struct ifmediareq *);
 
-void alc_aspm(struct alc_softc *);
+void alc_aspm(struct alc_softc *, int);
 void alc_disable_l0s_l1(struct alc_softc *);
 int alc_dma_alloc(struct alc_softc *);
 void alc_dma_free(struct alc_softc *);
@@ -109,7 +109,7 @@ void alc_phy_down(struct alc_softc *);
 void alc_phy_reset(struct alc_softc *);
 void alc_reset(struct alc_softc *);
 void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
-int alc_rxintr(struct alc_softc *);
+void alc_rxintr(struct alc_softc *);
 void alc_iff(struct alc_softc *);
 void alc_rxvlan(struct alc_softc *);
 void alc_start_queue(struct alc_softc *);
@@ -125,7 +125,11 @@ uint32_t alc_dma_burst[] = { 128, 256, 5
 
 const struct pci_matchid alc_devices[] = {
  { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C },
- { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 }
 };
 
 struct cfattach alc_ca = {
@@ -236,8 +240,8 @@ alc_miibus_statchg(struct device *dev)
  reg = CSR_READ_4(sc, ALC_MAC_CFG);
  reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
  CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
+ alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active));
  }
- alc_aspm(sc);
 }
 
 void
@@ -280,20 +284,53 @@ void
 alc_get_macaddr(struct alc_softc *sc)
 {
  uint32_t ea[2], opt;
- int i;
+ uint16_t val;
+ int eeprom, i;
 
+ eeprom = 0;
  opt = CSR_READ_4(sc, ALC_OPT_CFG);
- if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
+ if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
+    (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
  /*
  * EEPROM found, let TWSI reload EEPROM configuration.
  * This will set ethernet address of controller.
  */
- if ((opt & OPT_CFG_CLK_ENB) == 0) {
- opt |= OPT_CFG_CLK_ENB;
- CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
- CSR_READ_4(sc, ALC_OPT_CFG);
- DELAY(1000);
+ eeprom++;
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1C:
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ if ((opt & OPT_CFG_CLK_ENB) == 0) {
+ opt |= OPT_CFG_CLK_ENB;
+ CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
+ CSR_READ_4(sc, ALC_OPT_CFG);
+ DELAY(1000);
+ }
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x00);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val & 0xFF7F);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x3B);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val | 0x0008);
+ DELAY(20);
+ break;
  }
+
+ CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
+    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
+ CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
+ CSR_READ_4(sc, ALC_WOL_CFG);
+
  CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
     TWSI_CFG_SW_LD_START);
  for (i = 100; i > 0; i--) {
@@ -309,11 +346,36 @@ alc_get_macaddr(struct alc_softc *sc)
  if (alcdebug)
  printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname);
  }
- if ((opt & OPT_CFG_CLK_ENB) != 0) {
- opt &= ~OPT_CFG_CLK_ENB;
- CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
- CSR_READ_4(sc, ALC_OPT_CFG);
- DELAY(1000);
+ if (eeprom != 0) {
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1C:
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ if ((opt & OPT_CFG_CLK_ENB) != 0) {
+ opt &= ~OPT_CFG_CLK_ENB;
+ CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
+ CSR_READ_4(sc, ALC_OPT_CFG);
+ DELAY(1000);
+ }
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x00);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val | 0x0080);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x3B);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val & 0xFFF7);
+ DELAY(20);
+ break;
+ }
  }
 
  ea[0] = CSR_READ_4(sc, ALC_PAR0);
@@ -358,6 +420,43 @@ alc_phy_reset(struct alc_softc *sc)
  CSR_READ_2(sc, ALC_GPHY_CFG);
  DELAY(10 * 1000);
 
+ /* DSP fixup, Vendor magic. */
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x000A);
+ data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, data & 0xDFFF);
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x003B);
+ data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, data & 0xFFF7);
+ DELAY(20 * 1000);
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x0029);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, 0x929D);
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x0029);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, 0xB6DD);
+ }
+
  /* Load DSP codes, vendor magic. */
  data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
     ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
@@ -406,35 +505,114 @@ alc_phy_reset(struct alc_softc *sc)
 void
 alc_phy_down(struct alc_softc *sc)
 {
-
- /* Force PHY down. */
- CSR_WRITE_2(sc, ALC_GPHY_CFG,
-    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
-    GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW);
- DELAY(1000);
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ /*
+ * GPHY power down caused more problems on AR8151 v2.0.
+ * When driver is reloaded after GPHY power down,
+ * accesses to PHY/MAC registers hung the system. Only
+ * cold boot recovered from it.  I'm not sure whether
+ * AR8151 v1.0 also requires this one though.  I don't
+ * have AR8151 v1.0 controller in hand.
+ * The only option left is to isolate the PHY and
+ * initiates power down the PHY which in turn saves
+ * more power when driver is unloaded.
+ */
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    MII_BMCR, BMCR_ISO | BMCR_PDOWN);
+ break;
+ default:
+ /* Force PHY down. */
+ CSR_WRITE_2(sc, ALC_GPHY_CFG,
+    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
+    GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
+    GPHY_CFG_PWDOWN_HW);
+ DELAY(1000);
+ break;
+ }
 }
 
 void
-alc_aspm(struct alc_softc *sc)
+alc_aspm(struct alc_softc *sc, int media)
 {
  uint32_t pmcfg;
+ uint16_t linkcfg;
 
  pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
+ if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
+    (ALC_FLAG_APS | ALC_FLAG_PCIE))
+ linkcfg = CSR_READ_2(sc, sc->alc_expcap +
+    PCI_PCIE_LCSR);
+ else
+ linkcfg = 0;
  pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
- pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB;
- pmcfg |= PM_CFG_SERDES_L1_ENB;
- pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
+ pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
  pmcfg |= PM_CFG_MAC_ASPM_CHK;
+ pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
+ pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
+
+ if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
+ /* Disable extended sync except AR8152 B v1.0 */
+ linkcfg &= ~0x80;
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
+    sc->alc_rev == ATHEROS_AR8152_B_V10)
+ linkcfg |= 0x80;
+ CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR,
+    linkcfg);
+ pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
+    PM_CFG_HOTRST);
+ pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
+ pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
+    PM_CFG_PM_REQ_TIMER_SHIFT);
+ pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
+ }
+
  if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
- pmcfg |= PM_CFG_SERDES_PLL_L1_ENB;
- pmcfg &= ~PM_CFG_CLK_SWH_L1;
- pmcfg &= ~PM_CFG_ASPM_L1_ENB;
- pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
+ pmcfg |= PM_CFG_ASPM_L0S_ENB;
+ if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
+ pmcfg |= PM_CFG_ASPM_L1_ENB;
+ if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
+ pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
+    PM_CFG_SERDES_PLL_L1_ENB |
+    PM_CFG_SERDES_BUDS_RX_L1_ENB);
+ pmcfg |= PM_CFG_CLK_SWH_L1;
+ if (media == IFM_100_TX || media == IFM_1000_T) {
+ pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ pmcfg |= (7 <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ pmcfg |= (4 <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ break;
+ default:
+ pmcfg |= (15 <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ break;
+ }
+ }
+ } else {
+ pmcfg |= PM_CFG_SERDES_L1_ENB |
+    PM_CFG_SERDES_PLL_L1_ENB |
+    PM_CFG_SERDES_BUDS_RX_L1_ENB;
+ pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
+    PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
+ }
  } else {
- pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB;
+ pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
+    PM_CFG_SERDES_PLL_L1_ENB);
  pmcfg |= PM_CFG_CLK_SWH_L1;
- pmcfg &= ~PM_CFG_ASPM_L1_ENB;
- pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
+ pmcfg |= PM_CFG_ASPM_L1_ENB;
  }
  CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
 }
@@ -450,9 +628,9 @@ alc_attach(struct device *parent, struct
  const char *intrstr;
  struct ifnet *ifp;
  pcireg_t memtype;
- char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" };
+ char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
  uint16_t burst;
- int base, mii_flags, state, error = 0;
+ int base, state, error = 0;
  uint32_t cap, ctl, val;
 
  /*
@@ -499,6 +677,7 @@ alc_attach(struct device *parent, struct
  if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
     &base, NULL)) {
  sc->alc_flags |= ALC_FLAG_PCIE;
+ sc->alc_expcap = base;
  burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
     base + PCI_PCIE_DCSR) >> 16;
  sc->alc_dma_rd_burst = (burst & 0x7000) >> 12;
@@ -515,6 +694,20 @@ alc_attach(struct device *parent, struct
  val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
  val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
  CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
+ CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
+    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
+ CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
+    CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
+    PCIE_PHYMISC_FORCE_RCV_DET);
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
+    sc->alc_rev == ATHEROS_AR8152_B_V10) {
+ val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
+ val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
+    PCIE_PHYMISC2_SERDES_TH_MASK);
+ val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
+ val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
+ CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
+ }
  /* Disable ASPM L0S and L1. */
  cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
     base + PCI_PCIE_LCAP) >> 16;
@@ -528,13 +721,16 @@ alc_attach(struct device *parent, struct
     sc->sc_dev.dv_xname,
     sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
  state = ctl & 0x03;
+ if (state & 0x01)
+ sc->alc_flags |= ALC_FLAG_L0S;
+ if (state & 0x02)
+ sc->alc_flags |= ALC_FLAG_L1S;
  if (alcdebug)
  printf("%s: ASPM %s %s\n",
     sc->sc_dev.dv_xname,
     aspm_state[state],
     state == 0 ? "disabled" : "enabled");
- if (state != 0)
- alc_disable_l0s_l1(sc);
+ alc_disable_l0s_l1(sc);
  }
  }
 
@@ -551,12 +747,39 @@ alc_attach(struct device *parent, struct
  * used in AR8132 can't establish gigabit link even if it
  * shows the same PHY model/revision number of AR8131.
  */
- if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_L2C)
- sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO;
- else
- sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON;
+ sc->sc_product = PCI_PRODUCT(pa->pa_id);
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ sc->alc_flags |= ALC_FLAG_APS;
+ /* FALLTHROUGH */
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ sc->alc_flags |= ALC_FLAG_FASTETHER;
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ sc->alc_flags |= ALC_FLAG_APS;
+ /* FALLTHROUGH */
+ default:
+ break;
+ }
+ sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO;
+
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1C:
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ sc->alc_max_framelen = 9 * 1024;
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ sc->alc_max_framelen = 6 * 1024;
+ break;
+ }
+
  /*
- * It seems that AR8131/AR8132 has silicon bug for SMB. In
+ * It seems that AR813x/AR815x has silicon bug for SMB. In
  * addition, Atheros said that enabling SMB wouldn't improve
  * performance. However I think it's bad to access lots of
  * registers to extract MAC statistics.
@@ -619,11 +842,8 @@ alc_attach(struct device *parent, struct
 
  ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange,
     alc_mediastatus);
- mii_flags = 0;
- if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0)
- mii_flags |= MIIF_DOPAUSE;
  mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY,
- MII_OFFSET_ANY, mii_flags);
+ MII_OFFSET_ANY, MIIF_DOPAUSE);
 
  if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) {
  printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
@@ -1136,16 +1356,15 @@ alc_start(struct ifnet *ifp)
 {
  struct alc_softc *sc = ifp->if_softc;
  struct mbuf *m_head;
- int enq;
-
- if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
- return;
+ int enq = 0;
 
  /* Reclaim transmitted frames. */
  if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
  alc_txeof(sc);
 
- enq = 0;
+ if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
+ return;
+
  for (;;) {
  IFQ_DEQUEUE(&ifp->if_snd, m_head);
  if (m_head == NULL)
@@ -1162,7 +1381,7 @@ alc_start(struct ifnet *ifp)
  ifp->if_flags |= IFF_OACTIVE;
  break;
  }
- enq = 1;
+ enq++;
 
 #if NBPFILTER > 0
  /*
@@ -1174,7 +1393,7 @@ alc_start(struct ifnet *ifp)
 #endif
  }
 
- if (enq) {
+ if (enq > 0) {
  /* Sync descriptors. */
  bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
     sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
@@ -1274,6 +1493,10 @@ alc_mac_config(struct alc_softc *sc)
  reg = CSR_READ_4(sc, ALC_MAC_CFG);
  reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
     MAC_CFG_SPEED_MASK);
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
+ reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
  /* Reprogram MAC with resolved speed/duplex. */
  switch (IFM_SUBTYPE(mii->mii_media_active)) {
  case IFM_10_T:
@@ -1451,24 +1674,25 @@ alc_intr(void *arg)
  struct alc_softc *sc = arg;
  struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  uint32_t status;
+ int claimed = 0;
 
  status = CSR_READ_4(sc, ALC_INTR_STATUS);
  if ((status & ALC_INTRS) == 0)
  return (0);
 
+ /* Disable interrupts. */
+ CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
+
+ status = CSR_READ_4(sc, ALC_INTR_STATUS);
+ if ((status & ALC_INTRS) == 0)
+ goto back;
+
  /* Acknowledge and disable interrupts. */
  CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
 
  if (ifp->if_flags & IFF_RUNNING) {
- if (status & INTR_RX_PKT) {
- int error;
-
- error = alc_rxintr(sc);
- if (error) {
- alc_init(ifp);
- return (0);
- }
- }
+ if (status & INTR_RX_PKT)
+ alc_rxintr(sc);
 
  if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
     INTR_TXQ_TO_RST)) {
@@ -1485,14 +1709,17 @@ alc_intr(void *arg)
  return (0);
  }
 
- alc_txeof(sc);
- if (!IFQ_IS_EMPTY(&ifp->if_snd))
+ if (status & INTR_TX_PKT) {
+ alc_txeof(sc);
+    if (!IFQ_IS_EMPTY(&ifp->if_snd))
  alc_start(ifp);
+ }
  }
-
+ claimed = 1;
+back:
  /* Re-enable interrupts. */
  CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
- return (1);
+ return (claimed);
 }
 
 void
@@ -1507,7 +1734,7 @@ alc_txeof(struct alc_softc *sc)
  return;
  bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
     sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
-    BUS_DMASYNC_POSTREAD);
+    BUS_DMASYNC_POSTWRITE);
  if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
  bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
     sc->alc_cdata.alc_cmb_map->dm_mapsize,
@@ -1591,7 +1818,7 @@ alc_newbuf(struct alc_softc *sc, struct
  return (0);
 }
 
-int
+void
 alc_rxintr(struct alc_softc *sc)
 {
  struct ifnet *ifp = &sc->sc_arpcom.ac_if;
@@ -1615,7 +1842,7 @@ alc_rxintr(struct alc_softc *sc)
  if (alcdebug)
  printf("%s: unexpected segment count -- "
     "resetting\n", sc->sc_dev.dv_xname);
- return (EIO);
+ break;
  }
  alc_rxeof(sc, rrd);
  /* Clear Rx return status. */
@@ -1653,8 +1880,6 @@ alc_rxintr(struct alc_softc *sc)
  CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
     sc->alc_cdata.alc_rx_cons);
  }
-
- return (0);
 }
 
 /* Receive a frame. */
@@ -1686,9 +1911,8 @@ alc_rxeof(struct alc_softc *sc, struct r
  *  Force network stack compute checksum for
  *  errored frames.
  */
- status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
- if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC |
-    RRD_ERR_RUNT) != 0)
+ if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN |
+    RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0)
  return;
  }
 
@@ -1801,7 +2025,9 @@ alc_reset(struct alc_softc *sc)
  uint32_t reg;
  int i;
 
- CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET);
+ reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF;
+ reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
+ CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
  for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
  DELAY(10);
  if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
@@ -1852,6 +2078,9 @@ alc_init(struct ifnet *ifp)
  alc_init_cmb(sc);
  alc_init_smb(sc);
 
+ /* Enable all clocks. */
+ CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
+
  /* Reprogram the station address. */
  bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN);
  CSR_WRITE_4(sc, ALC_PAR0,
@@ -1913,6 +2142,18 @@ alc_init(struct ifnet *ifp)
  CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
  CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
 
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
+ /* Reconfigure SRAM - Vendor magic. */
+ CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
+ CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
+ CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
+ CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
+ CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
+ CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
+ CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
+ CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
+ }
+
  /* Tell hardware that we're ready to load DMA blocks. */
  CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
 
@@ -1922,14 +2163,11 @@ alc_init(struct ifnet *ifp)
  reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
  reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
  CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
- reg = CSR_READ_4(sc, ALC_MASTER_CFG);
- reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
  /*
  * We don't want to automatic interrupt clear as task queue
  * for the interrupt should know interrupt status.
  */
- reg &= ~MASTER_INTR_RD_CLR;
- reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
+ reg = MASTER_SA_TIMER_ENB;
  if (ALC_USECS(sc->alc_int_rx_mod) != 0)
  reg |= MASTER_IM_RX_TIMER_ENB;
  if (ALC_USECS(sc->alc_int_tx_mod) != 0)
@@ -1970,7 +2208,7 @@ alc_init(struct ifnet *ifp)
  * Be conservative in what you do, be liberal in what you
  * accept from others - RFC 793.
  */
- CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN);
+ CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen);
 
  /* Disable header split(?) */
  CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
@@ -1997,11 +2235,14 @@ alc_init(struct ifnet *ifp)
  * TSO/checksum offloading.
  */
  CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
-    (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
+    (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
     TSO_OFFLOAD_THRESH_MASK);
  /* Configure TxQ. */
  reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
     TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
+ reg >>= 1;
  reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
     TXQ_CFG_TD_BURST_MASK;
  CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
@@ -2018,14 +2259,22 @@ alc_init(struct ifnet *ifp)
  * XON  : 80% of Rx FIFO
  * XOFF : 30% of Rx FIFO
  */
- reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
- rxf_hi = (reg * 8) / 10;
- rxf_lo = (reg * 3)/ 10;
- CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
-    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
-    RX_FIFO_PAUSE_THRESH_LO_MASK) |
-    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
-     RX_FIFO_PAUSE_THRESH_HI_MASK));
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) {
+ reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
+ rxf_hi = (reg * 8) / 10;
+ rxf_lo = (reg * 3) / 10;
+ CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
+    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
+    RX_FIFO_PAUSE_THRESH_LO_MASK) |
+    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
+    RX_FIFO_PAUSE_THRESH_HI_MASK));
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
+ CSR_WRITE_4(sc, ALC_SERDES_LOCK,
+    CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
+    SERDES_PHY_CLK_SLOWDOWN);
 
  /* Disable RSS until I understand L1C/L2C's RSS logic. */
  CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
@@ -2036,15 +2285,9 @@ alc_init(struct ifnet *ifp)
     RXQ_CFG_RD_BURST_MASK;
  reg |= RXQ_CFG_RSS_MODE_DIS;
  if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
- reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
+ reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
  CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
 
- /* Configure Rx DMAW request thresold. */
- CSR_WRITE_4(sc, ALC_RD_DMA_CFG,
-    ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) &
-    RD_DMA_CFG_THRESH_MASK) |
-    ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) &
-    RD_DMA_CFG_TIMER_MASK));
  /* Configure DMA parameters. */
  reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
  reg |= sc->alc_rcb;
@@ -2070,7 +2313,7 @@ alc_init(struct ifnet *ifp)
  *  - Enable CRC generation.
  *  Actual reconfiguration of MAC for resolved speed/duplex
  *  is followed after detection of link establishment.
- *  AR8131/AR8132 always does checksum computation regardless
+ *  AR813x/AR815x always does checksum computation regardless
  *  of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
  *  have bug in protocol field in Rx return structure so
  *  these controllers can't handle fragmented frames. Disable
@@ -2080,6 +2323,10 @@ alc_init(struct ifnet *ifp)
  reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
     ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
     MAC_CFG_PREAMBLE_MASK);
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
+ reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
  if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
  reg |= MAC_CFG_SPEED_10_100;
  else
Index: sys/dev/pci/if_alcreg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_alcreg.h,v
retrieving revision 1.1
diff -u -p -r1.1 if_alcreg.h
--- sys/dev/pci/if_alcreg.h 8 Aug 2009 09:31:13 -0000 1.1
+++ sys/dev/pci/if_alcreg.h 1 May 2011 18:55:25 -0000
@@ -31,7 +31,10 @@
 #ifndef _IF_ALCREG_H
 #define _IF_ALCREG_H
 
-#define ALC_PCIR_BAR 0x10
+#define ALC_PCIR_BAR 0x10
+
+#define ATHEROS_AR8152_B_V10 0xC0
+#define ATHEROS_AR8152_B_V11 0xC1
 
 /* 0x0000 - 0x02FF : PCIe configuration space */
 
@@ -56,6 +59,12 @@
 #define ALC_PCIE_PHYMISC 0x1000
 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
 
+#define ALC_PCIE_PHYMISC2 0x1004
+#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
+#define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
+#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
+#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
+
 #define ALC_TWSI_DEBUG 0x1108
 #define TWSI_DEBUG_DEV_EXIST 0x20000000
 
@@ -88,7 +97,9 @@
 #define PM_CFG_PCIE_RECV 0x00008000
 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
-#define PM_CFG_LCKDET_TIMER_MASK 0x3F000000
+#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
+#define PM_CFG_EN_BUFS_RX_L0S 0x10000000
+#define PM_CFG_SA_DLY_ENB 0x20000000
 #define PM_CFG_MAC_ASPM_CHK 0x40000000
 #define PM_CFG_HOTRST 0x80000000
 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8
@@ -96,10 +107,20 @@
 #define PM_CFG_PM_REQ_TIMER_SHIFT 20
 #define PM_CFG_LCKDET_TIMER_SHIFT 24
 
+#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
+#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1
+#define PM_CFG_LCKDET_TIMER_DEFAULT 12
+#define PM_CFG_PM_REQ_TIMER_DEFAULT 12
+
+#define ALC_LTSSM_ID_CFG 0x12FC
+#define LTSSM_ID_WRO_ENB 0x00001000
+
 #define ALC_MASTER_CFG 0x1400
 #define MASTER_RESET 0x00000001
+#define MASTER_TEST_MODE_MASK 0x0000000C
 #define MASTER_BERT_START 0x00000010
-#define MASTER_TEST_MODE_MASK 0x000000C0
+#define MASTER_OOB_DIS_OFF 0x00000040
+#define MASTER_SA_TIMER_ENB 0x00000080
 #define MASTER_MTIMER_ENB 0x00000100
 #define MASTER_MANUAL_INTR_ENB 0x00000200
 #define MASTER_IM_TX_TIMER_ENB 0x00000400
@@ -114,7 +135,7 @@
 #define MASTER_CHIP_REV_SHIFT 16
 #define MASTER_CHIP_ID_SHIFT 24
 
-/* Number of ticks per usec for AR8131/AR8132. */
+/* Number of ticks per usec for AR813x/AR815x. */
 #define ALC_TICK_USECS 2
 #define ALC_USECS(x) ((x) / ALC_TICK_USECS)
 
@@ -136,7 +157,7 @@
  * alc(4) does not rely on Tx completion interrupts, so set it
  * somewhat large value to reduce Tx completion interrupts.
  */
-#define ALC_IM_TX_TIMER_DEFAULT 50000 /* 50ms */
+#define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */
 
 #define ALC_GPHY_CFG 0x140C /* 16bits */
 #define GPHY_CFG_EXT_RESET 0x0001
@@ -212,6 +233,8 @@
 #define ALC_SERDES_LOCK 0x1424
 #define SERDES_LOCK_DET 0x00000001
 #define SERDES_LOCK_DET_ENB 0x00000002
+#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
+#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
 
 #define ALC_MAC_CFG 0x1480
 #define MAC_CFG_TX_ENB 0x00000001
@@ -241,6 +264,8 @@
 #define MAC_CFG_BCAST 0x04000000
 #define MAC_CFG_DBG 0x08000000
 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
+#define MAC_CFG_HASH_ALG_CRC32 0x20000000
+#define MAC_CFG_SPEED_MODE_SW 0x40000000
 #define MAC_CFG_PREAMBLE_SHIFT 10
 #define MAC_CFG_PREAMBLE_DEFAULT 7
 
@@ -683,11 +708,19 @@
 #define HDS_CFG_BACKFILLSIZE_SHIFT 8
 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20
 
-/* AR8131/AR8132 registers for MAC statistics */
+/* AR813x/AR815x registers for MAC statistics */
 #define ALC_RX_MIB_BASE 0x1700
 
 #define ALC_TX_MIB_BASE 0x1760
 
+#define ALC_CLK_GATING_CFG 0x1814
+#define CLK_GATING_DMAW_ENB 0x0001
+#define CLK_GATING_DMAR_ENB 0x0002
+#define CLK_GATING_TXQ_ENB 0x0004
+#define CLK_GATING_RXQ_ENB 0x0008
+#define CLK_GATING_TXMAC_ENB 0x0010
+#define CLK_GATING_RXMAC_ENB 0x0020
+
 #define ALC_DEBUG_DATA0 0x1900
 
 #define ALC_DEBUG_DATA1 0x1904
@@ -1112,6 +1145,7 @@ struct alc_softc {
  bus_dma_tag_t sc_dmat;
  pci_chipset_tag_t sc_pct;
  pcitag_t sc_pcitag;
+ pci_vendor_id_t sc_product;
 
  void *sc_irq_handle;
 
@@ -1120,19 +1154,23 @@ struct alc_softc {
  int alc_chip_rev;
  int alc_phyaddr;
  uint8_t alc_eaddr[ETHER_ADDR_LEN];
+ uint32_t alc_max_framelen;
  uint32_t alc_dma_rd_burst;
  uint32_t alc_dma_wr_burst;
  uint32_t alc_rcb;
+ int alc_expcap;
  int alc_flags;
 #define ALC_FLAG_PCIE 0x0001
 #define ALC_FLAG_PCIX 0x0002
-#define ALC_FLAG_MSI 0x0004
-#define ALC_FLAG_MSIX 0x0008
+#define ALC_FLAG_PM 0x0010
 #define ALC_FLAG_FASTETHER 0x0020
 #define ALC_FLAG_JUMBO 0x0040
 #define ALC_FLAG_ASPM_MON 0x0080
 #define ALC_FLAG_CMB_BUG 0x0100
 #define ALC_FLAG_SMB_BUG 0x0200
+#define ALC_FLAG_L0S 0x0400
+#define ALC_FLAG_L1S 0x0800
+#define ALC_FLAG_APS 0x1000
 #define ALC_FLAG_DETACH 0x4000
 #define ALC_FLAG_LINK 0x8000

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Re: alc(4) support for Atheros AR815x

Abel Abraham Camarillo Ojeda-2
On Sun, May 1, 2011 at 2:10 PM, Stuart Henderson <[hidden email]> wrote:

> On 2011/05/01 18:35, Edd Barrett wrote:
>> I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
>> there an updated diff?
>
> Yes I just took the 2 minutes it took to apply it and fix
> the minor conflicts and linewrapping issue with the diff.
> Untested beyond "it builds".
>
> Test reports and dmesg lines from existing working alc(4) L1C and
> L2C wanted. If it makes new chips work that's a bonus, but the
> important thing is making sure it doesn't break something that
> already works.
>
> Doesn't seem any point disabling interrupts in the ISR though.
> I haven't touched that in this diff but that should probably be
> done too.
>
> ....

Tested here on amd64.mp:

No relevant changes in dmesg (i guess)...

Old dmesg:

OpenBSD 4.9-current (kobj) #0: Tue Apr 26 18:02:56 CDT 2011
    root@maetel.00z:/usr/kobj
real mem = 1608056832 (1533MB)
avail mem = 1551200256 (1479MB)
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 2.6 @ 0xfd400 (50 entries)
bios0: vendor American Megatrends Inc. version "V1.3" date 11/15/2010
bios0: MSI MS-7623
acpi0 at bios0: rev 0
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP APIC MCFG OEMB SRAT HPET SSDT
acpi0: wakeup devices PCE2(S4) PCE3(S4) PCE4(S4) PCE5(S4) PCE6(S4)
PCE7(S4) PCE9(S4) PCEA(S4) PCEB(S4) PCEC(S4) SBAZ(S4) PSKE(S4)
PSMS(S4) ECIR(S4) PS2K(S3) PS2M(S3) P0PC(S4) UHC1(S4) UHC2(S4)
UHC3(S4) USB4(S4) UHC5(S4) UHC6(S4) UHC7(S4) PWRB(S3)
acpitimer0 at acpi0: 3579545 Hz, 32 bits
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: AMD Phenom(tm) II X4 955 Processor, 3200.65 MHz
cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DNOW
cpu0: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
64b/line 16-way L2 cache
cpu0: ITLB 32 4KB entries fully associative, 16 4MB entries fully associative
cpu0: DTLB 48 4KB entries fully associative, 48 4MB entries fully associative
cpu0: apic clock running at 200MHz
cpu1 at mainbus0: apid 1 (application processor)
cpu1: AMD Phenom(tm) II X4 955 Processor, 3200.16 MHz
cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DNOW
cpu1: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
64b/line 16-way L2 cache
cpu1: ITLB 32 4KB entries fully associative, 16 4MB entries fully associative
cpu1: DTLB 48 4KB entries fully associative, 48 4MB entries fully associative
cpu2 at mainbus0: apid 2 (application processor)
cpu2: AMD Phenom(tm) II X4 955 Processor, 3200.15 MHz
cpu2: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DNOW
cpu2: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
64b/line 16-way L2 cache
cpu2: ITLB 32 4KB entries fully associative, 16 4MB entries fully associative
cpu2: DTLB 48 4KB entries fully associative, 48 4MB entries fully associative
cpu3 at mainbus0: apid 3 (application processor)
cpu3: AMD Phenom(tm) II X4 955 Processor, 3200.15 MHz
cpu3: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DNOW
cpu3: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
64b/line 16-way L2 cache
cpu3: ITLB 32 4KB entries fully associative, 16 4MB entries fully associative
cpu3: DTLB 48 4KB entries fully associative, 48 4MB entries fully associative
ioapic0 at mainbus0: apid 4 pa 0xfec00000, version 21, 24 pins
acpimcfg0 at acpi0 addr 0xe0000000, bus 0-255
acpihpet0 at acpi0: 14318180 Hz
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus 1 (P0P1)
acpiprt2 at acpi0: bus -1 (PCE2)
acpiprt3 at acpi0: bus -1 (PCE3)
acpiprt4 at acpi0: bus -1 (PCE4)
acpiprt5 at acpi0: bus 2 (PCE5)
acpiprt6 at acpi0: bus -1 (PCE6)
acpiprt7 at acpi0: bus -1 (PCE7)
acpiprt8 at acpi0: bus -1 (PCE9)
acpiprt9 at acpi0: bus -1 (PCEA)
acpiprt10 at acpi0: bus -1 (PCEB)
acpiprt11 at acpi0: bus -1 (PCEC)
acpiprt12 at acpi0: bus 3 (P0PC)
acpicpu0 at acpi0: PSS
acpicpu1 at acpi0: PSS
acpicpu2 at acpi0: PSS
acpicpu3 at acpi0: PSS
acpibtn0 at acpi0: PWRB
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 "AMD RS780 Host" rev 0x00
ppb0 at pci0 dev 1 function 0 "AMD RS780 PCIE" rev 0x00
pci1 at ppb0 bus 1
vga1 at pci1 dev 5 function 0 vendor "ATI", unknown product 0x9616 rev 0x00
wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation)
wsdisplay0: screen 1-5 added (80x25, vt100 emulation)
ppb1 at pci0 dev 5 function 0 "AMD RS780 PCIE" rev 0x00: apic 4 int 17
pci2 at ppb1 bus 2
alc0 at pci2 dev 0 function 0 "Attansic Technology L1C" rev 0xc0: apic
4 int 17, address 6c:62:6d:de:03:76
atphy0 at alc0 phy 0: F1 10/100/1000 PHY, rev. 11
ahci0 at pci0 dev 17 function 0 "ATI SBx00 SATA" rev 0x00: apic 4 int
22, AHCI 1.1
scsibus0 at ahci0: 32 targets
sd0 at scsibus0 targ 0 lun 0: <ATA, WDC WD5000AAJS-2, 01.0> SCSI3
0/direct fixed naa.50014ee10176d64c
sd0: 476940MB, 512 bytes/sec, 976773168 sec total
sd1 at scsibus0 targ 1 lun 0: <ATA, WDC WD10EARS-00Y, 80.0> SCSI3
0/direct fixed naa.50014ee05735bde1
sd1: 953869MB, 512 bytes/sec, 1953525168 sec total
ohci0 at pci0 dev 18 function 0 "ATI SB700 USB" rev 0x00: apic 4 int
16, version 1.0, legacy support
ohci1 at pci0 dev 18 function 1 "ATI SB700 USB" rev 0x00: apic 4 int
16, version 1.0, legacy support
ehci0 at pci0 dev 18 function 2 "ATI SB700 USB2" rev 0x00: apic 4 int 17
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "ATI EHCI root hub" rev 2.00/1.00 addr 1
ohci2 at pci0 dev 19 function 0 "ATI SB700 USB" rev 0x00: apic 4 int
18, version 1.0, legacy support
ohci3 at pci0 dev 19 function 1 "ATI SB700 USB" rev 0x00: apic 4 int
18, version 1.0, legacy support
ehci1 at pci0 dev 19 function 2 "ATI SB700 USB2" rev 0x00: apic 4 int 19
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 "ATI EHCI root hub" rev 2.00/1.00 addr 1
piixpm0 at pci0 dev 20 function 0 "ATI SBx00 SMBus" rev 0x3c: SMI
iic0 at piixpm0
spdmem0 at iic0 addr 0x50: 2GB DDR3 SDRAM PC3-10600
pciide0 at pci0 dev 20 function 1 "ATI SB700 IDE" rev 0x00: DMA,
channel 0 configured to compatibility, channel 1 configured to
compatibility
atapiscsi0 at pciide0 channel 0 drive 1
scsibus1 at atapiscsi0: 2 targets
cd0 at scsibus1 targ 0 lun 0: <PIONEER, DVD-RW DVR-116D, 1.08> ATAPI
5/cdrom removable
cd0(pciide0:0:1): using PIO mode 4, DMA mode 2, Ultra-DMA mode 4
azalia0 at pci0 dev 20 function 2 "ATI SBx00 HD Audio" rev 0x00: apic 4 int 16
azalia0: codecs: VIA/0x0397
audio0 at azalia0
pcib0 at pci0 dev 20 function 3 "ATI SB700 ISA" rev 0x00
ppb2 at pci0 dev 20 function 4 "ATI SB600 PCI" rev 0x00
pci3 at ppb2 bus 3
re0 at pci3 dev 2 function 0 "Realtek 8169" rev 0x10: RTL8169/8110SB
(0x1000), apic 4 int 20, address 00:08:54:a6:be:f6
rgephy0 at re0 phy 7: RTL8169S/8110S PHY, rev. 3
ohci4 at pci0 dev 20 function 5 "ATI SB700 USB" rev 0x00: apic 4 int
18, version 1.0, legacy support
pchb1 at pci0 dev 24 function 0 "AMD AMD64 10h HyperTransport" rev 0x00
pchb2 at pci0 dev 24 function 1 "AMD AMD64 10h Address Map" rev 0x00
pchb3 at pci0 dev 24 function 2 "AMD AMD64 10h DRAM Cfg" rev 0x00
km0 at pci0 dev 24 function 3 "AMD AMD64 10h Misc Cfg" rev 0x00
pchb4 at pci0 dev 24 function 4 "AMD AMD64 10h Link Cfg" rev 0x00
usb2 at ohci0: USB revision 1.0
uhub2 at usb2 "ATI OHCI root hub" rev 1.00/1.00 addr 1
usb3 at ohci1: USB revision 1.0
uhub3 at usb3 "ATI OHCI root hub" rev 1.00/1.00 addr 1
usb4 at ohci2: USB revision 1.0
uhub4 at usb4 "ATI OHCI root hub" rev 1.00/1.00 addr 1
usb5 at ohci3: USB revision 1.0
uhub5 at usb5 "ATI OHCI root hub" rev 1.00/1.00 addr 1
isa0 at pcib0
isadma0 at isa0
com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
com0: probed fifo depth: 15 bytes
com1 at isa0 port 0x2f8/8 irq 3: ns16550a, 16 byte fifo
com1: probed fifo depth: 15 bytes
pckbc0 at isa0 port 0x60/5
pckbd0 at pckbc0 (kbd slot)
pckbc0: using irq 1 for kbd slot
wskbd0 at pckbd0: console keyboard, using wsdisplay0
pcppi0 at isa0 port 0x61
spkr0 at pcppi0
lpt0 at isa0 port 0x378/4 irq 7
usb6 at ohci4: USB revision 1.0
uhub6 at usb6 "ATI OHCI root hub" rev 1.00/1.00 addr 1
mtrr: Pentium Pro MTRR support
uhidev0 at uhub3 port 2 configuration 1 interface 0 "Microsoft Basic
Optical Mouse" rev 1.10/0.00 addr 2
uhidev0: iclass 3/1
ums0 at uhidev0: 3 buttons, Z dir
wsmouse0 at ums0 mux 0
uhidev1 at uhub3 port 3 configuration 1 interface 0 "Logitech Logitech
USB Keyboard" rev 2.00/60.00 addr 3
uhidev1: iclass 3/1
ukbd0 at uhidev1: 8 modifier keys, 6 key codes
wskbd1 at ukbd0 mux 1
wskbd1: connecting to wsdisplay0
uhidev2 at uhub3 port 3 configuration 1 interface 1 "Logitech Logitech
USB Keyboard" rev 2.00/60.00 addr 3
uhidev2: iclass 3/0, 4 report ids
uhid0 at uhidev2 reportid 3: input=4, output=0, feature=0
uhid1 at uhidev2 reportid 4: input=1, output=0, feature=0
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
root on sd0a swap on sd0b dump on sd0b

--- /home/the00z/diff/alc.dmesgold Sun May  1 14:46:33 2011
+++ /home/the00z/diff/alc.dmesg Sun May  1 14:45:43 2011
@@ -1,7 +1,7 @@
-OpenBSD 4.9-current (kobj) #0: Tue Apr 26 18:02:56 CDT 2011
+OpenBSD 4.9-current (kobj) #0: Sun May  1 14:32:33 CDT 2011
     root@maetel.00z:/usr/kobj
 real mem = 1608056832 (1533MB)
-avail mem = 1551200256 (1479MB)
+avail mem = 1551196160 (1479MB)
 mainbus0 at root
 bios0 at mainbus0: SMBIOS rev. 2.6 @ 0xfd400 (50 entries)
 bios0: vendor American Megatrends Inc. version "V1.3" date 11/15/2010
@@ -13,14 +13,14 @@
 acpitimer0 at acpi0: 3579545 Hz, 32 bits
 acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
 cpu0 at mainbus0: apid 0 (boot processor)
-cpu0: AMD Phenom(tm) II X4 955 Processor, 3200.65 MHz
+cpu0: AMD Phenom(tm) II X4 955 Processor, 3200.55 MHz
 cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DNOW
 cpu0: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
64b/line 16-way L2 cache
 cpu0: ITLB 32 4KB entries fully associative, 16 4MB entries fully associative
 cpu0: DTLB 48 4KB entries fully associative, 48 4MB entries fully associative
 cpu0: apic clock running at 200MHz
 cpu1 at mainbus0: apid 1 (application processor)
-cpu1: AMD Phenom(tm) II X4 955 Processor, 3200.16 MHz
+cpu1: AMD Phenom(tm) II X4 955 Processor, 3200.15 MHz
 cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DNOW
 cpu1: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
64b/line 16-way L2 cache
 cpu1: ITLB 32 4KB entries fully associative, 16 4MB entries fully associative

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Re: alc(4) support for Atheros AR815x

Abel Abraham Camarillo Ojeda-2
I mean... my alc0 still works...


On Sun, May 1, 2011 at 2:49 PM, Abel Abraham Camarillo Ojeda
<[hidden email]> wrote:
> On Sun, May 1, 2011 at 2:10 PM, Stuart Henderson <[hidden email]>
wrote:
>> On 2011/05/01 18:35, Edd Barrett wrote:
>>> I have acquired a netboot (packard bell dot s), which I think uses this
NIC. Is

>>> there an updated diff?
>>
>> Yes I just took the 2 minutes it took to apply it and fix
>> the minor conflicts and linewrapping issue with the diff.
>> Untested beyond "it builds".
>>
>> Test reports and dmesg lines from existing working alc(4) L1C and
>> L2C wanted. If it makes new chips work that's a bonus, but the
>> important thing is making sure it doesn't break something that
>> already works.
>>
>> Doesn't seem any point disabling interrupts in the ISR though.
>> I haven't touched that in this diff but that should probably be
>> done too.
>>
>> ....
>
> Tested here on amd64.mp:
>
> No relevant changes in dmesg (i guess)...
>
> Old dmesg:
>
> OpenBSD 4.9-current (kobj) #0: Tue Apr 26 18:02:56 CDT 2011
> B  B root@maetel.00z:/usr/kobj
> real mem = 1608056832 (1533MB)
> avail mem = 1551200256 (1479MB)
> mainbus0 at root
> bios0 at mainbus0: SMBIOS rev. 2.6 @ 0xfd400 (50 entries)
> bios0: vendor American Megatrends Inc. version "V1.3" date 11/15/2010
> bios0: MSI MS-7623
> acpi0 at bios0: rev 0
> acpi0: sleep states S0 S3 S4 S5
> acpi0: tables DSDT FACP APIC MCFG OEMB SRAT HPET SSDT
> acpi0: wakeup devices PCE2(S4) PCE3(S4) PCE4(S4) PCE5(S4) PCE6(S4)
> PCE7(S4) PCE9(S4) PCEA(S4) PCEB(S4) PCEC(S4) SBAZ(S4) PSKE(S4)
> PSMS(S4) ECIR(S4) PS2K(S3) PS2M(S3) P0PC(S4) UHC1(S4) UHC2(S4)
> UHC3(S4) USB4(S4) UHC5(S4) UHC6(S4) UHC7(S4) PWRB(S3)
> acpitimer0 at acpi0: 3579545 Hz, 32 bits
> acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
> cpu0 at mainbus0: apid 0 (boot processor)
> cpu0: AMD Phenom(tm) II X4 955 Processor, 3200.65 MHz
> cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUS
H,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DN
OW
> cpu0: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
> 64b/line 16-way L2 cache
> cpu0: ITLB 32 4KB entries fully associative, 16 4MB entries fully
associative
> cpu0: DTLB 48 4KB entries fully associative, 48 4MB entries fully
associative
> cpu0: apic clock running at 200MHz
> cpu1 at mainbus0: apid 1 (application processor)
> cpu1: AMD Phenom(tm) II X4 955 Processor, 3200.16 MHz
> cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUS
H,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DN
OW
> cpu1: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
> 64b/line 16-way L2 cache
> cpu1: ITLB 32 4KB entries fully associative, 16 4MB entries fully
associative
> cpu1: DTLB 48 4KB entries fully associative, 48 4MB entries fully
associative
> cpu2 at mainbus0: apid 2 (application processor)
> cpu2: AMD Phenom(tm) II X4 955 Processor, 3200.15 MHz
> cpu2:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUS
H,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DN
OW
> cpu2: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
> 64b/line 16-way L2 cache
> cpu2: ITLB 32 4KB entries fully associative, 16 4MB entries fully
associative
> cpu2: DTLB 48 4KB entries fully associative, 48 4MB entries fully
associative
> cpu3 at mainbus0: apid 3 (application processor)
> cpu3: AMD Phenom(tm) II X4 955 Processor, 3200.15 MHz
> cpu3:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUS
H,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DN
OW
> cpu3: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
> 64b/line 16-way L2 cache
> cpu3: ITLB 32 4KB entries fully associative, 16 4MB entries fully
associative
> cpu3: DTLB 48 4KB entries fully associative, 48 4MB entries fully
associative

> ioapic0 at mainbus0: apid 4 pa 0xfec00000, version 21, 24 pins
> acpimcfg0 at acpi0 addr 0xe0000000, bus 0-255
> acpihpet0 at acpi0: 14318180 Hz
> acpiprt0 at acpi0: bus 0 (PCI0)
> acpiprt1 at acpi0: bus 1 (P0P1)
> acpiprt2 at acpi0: bus -1 (PCE2)
> acpiprt3 at acpi0: bus -1 (PCE3)
> acpiprt4 at acpi0: bus -1 (PCE4)
> acpiprt5 at acpi0: bus 2 (PCE5)
> acpiprt6 at acpi0: bus -1 (PCE6)
> acpiprt7 at acpi0: bus -1 (PCE7)
> acpiprt8 at acpi0: bus -1 (PCE9)
> acpiprt9 at acpi0: bus -1 (PCEA)
> acpiprt10 at acpi0: bus -1 (PCEB)
> acpiprt11 at acpi0: bus -1 (PCEC)
> acpiprt12 at acpi0: bus 3 (P0PC)
> acpicpu0 at acpi0: PSS
> acpicpu1 at acpi0: PSS
> acpicpu2 at acpi0: PSS
> acpicpu3 at acpi0: PSS
> acpibtn0 at acpi0: PWRB
> pci0 at mainbus0 bus 0
> pchb0 at pci0 dev 0 function 0 "AMD RS780 Host" rev 0x00
> ppb0 at pci0 dev 1 function 0 "AMD RS780 PCIE" rev 0x00
> pci1 at ppb0 bus 1
> vga1 at pci1 dev 5 function 0 vendor "ATI", unknown product 0x9616 rev 0x00
> wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation)
> wsdisplay0: screen 1-5 added (80x25, vt100 emulation)
> ppb1 at pci0 dev 5 function 0 "AMD RS780 PCIE" rev 0x00: apic 4 int 17
> pci2 at ppb1 bus 2
> alc0 at pci2 dev 0 function 0 "Attansic Technology L1C" rev 0xc0: apic
> 4 int 17, address 6c:62:6d:de:03:76
> atphy0 at alc0 phy 0: F1 10/100/1000 PHY, rev. 11
> ahci0 at pci0 dev 17 function 0 "ATI SBx00 SATA" rev 0x00: apic 4 int
> 22, AHCI 1.1
> scsibus0 at ahci0: 32 targets
> sd0 at scsibus0 targ 0 lun 0: <ATA, WDC WD5000AAJS-2, 01.0> SCSI3
> 0/direct fixed naa.50014ee10176d64c
> sd0: 476940MB, 512 bytes/sec, 976773168 sec total
> sd1 at scsibus0 targ 1 lun 0: <ATA, WDC WD10EARS-00Y, 80.0> SCSI3
> 0/direct fixed naa.50014ee05735bde1
> sd1: 953869MB, 512 bytes/sec, 1953525168 sec total
> ohci0 at pci0 dev 18 function 0 "ATI SB700 USB" rev 0x00: apic 4 int
> 16, version 1.0, legacy support
> ohci1 at pci0 dev 18 function 1 "ATI SB700 USB" rev 0x00: apic 4 int
> 16, version 1.0, legacy support
> ehci0 at pci0 dev 18 function 2 "ATI SB700 USB2" rev 0x00: apic 4 int 17
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 "ATI EHCI root hub" rev 2.00/1.00 addr 1
> ohci2 at pci0 dev 19 function 0 "ATI SB700 USB" rev 0x00: apic 4 int
> 18, version 1.0, legacy support
> ohci3 at pci0 dev 19 function 1 "ATI SB700 USB" rev 0x00: apic 4 int
> 18, version 1.0, legacy support
> ehci1 at pci0 dev 19 function 2 "ATI SB700 USB2" rev 0x00: apic 4 int 19
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 "ATI EHCI root hub" rev 2.00/1.00 addr 1
> piixpm0 at pci0 dev 20 function 0 "ATI SBx00 SMBus" rev 0x3c: SMI
> iic0 at piixpm0
> spdmem0 at iic0 addr 0x50: 2GB DDR3 SDRAM PC3-10600
> pciide0 at pci0 dev 20 function 1 "ATI SB700 IDE" rev 0x00: DMA,
> channel 0 configured to compatibility, channel 1 configured to
> compatibility
> atapiscsi0 at pciide0 channel 0 drive 1
> scsibus1 at atapiscsi0: 2 targets
> cd0 at scsibus1 targ 0 lun 0: <PIONEER, DVD-RW DVR-116D, 1.08> ATAPI
> 5/cdrom removable
> cd0(pciide0:0:1): using PIO mode 4, DMA mode 2, Ultra-DMA mode 4
> azalia0 at pci0 dev 20 function 2 "ATI SBx00 HD Audio" rev 0x00: apic 4 int
16

> azalia0: codecs: VIA/0x0397
> audio0 at azalia0
> pcib0 at pci0 dev 20 function 3 "ATI SB700 ISA" rev 0x00
> ppb2 at pci0 dev 20 function 4 "ATI SB600 PCI" rev 0x00
> pci3 at ppb2 bus 3
> re0 at pci3 dev 2 function 0 "Realtek 8169" rev 0x10: RTL8169/8110SB
> (0x1000), apic 4 int 20, address 00:08:54:a6:be:f6
> rgephy0 at re0 phy 7: RTL8169S/8110S PHY, rev. 3
> ohci4 at pci0 dev 20 function 5 "ATI SB700 USB" rev 0x00: apic 4 int
> 18, version 1.0, legacy support
> pchb1 at pci0 dev 24 function 0 "AMD AMD64 10h HyperTransport" rev 0x00
> pchb2 at pci0 dev 24 function 1 "AMD AMD64 10h Address Map" rev 0x00
> pchb3 at pci0 dev 24 function 2 "AMD AMD64 10h DRAM Cfg" rev 0x00
> km0 at pci0 dev 24 function 3 "AMD AMD64 10h Misc Cfg" rev 0x00
> pchb4 at pci0 dev 24 function 4 "AMD AMD64 10h Link Cfg" rev 0x00
> usb2 at ohci0: USB revision 1.0
> uhub2 at usb2 "ATI OHCI root hub" rev 1.00/1.00 addr 1
> usb3 at ohci1: USB revision 1.0
> uhub3 at usb3 "ATI OHCI root hub" rev 1.00/1.00 addr 1
> usb4 at ohci2: USB revision 1.0
> uhub4 at usb4 "ATI OHCI root hub" rev 1.00/1.00 addr 1
> usb5 at ohci3: USB revision 1.0
> uhub5 at usb5 "ATI OHCI root hub" rev 1.00/1.00 addr 1
> isa0 at pcib0
> isadma0 at isa0
> com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
> com0: probed fifo depth: 15 bytes
> com1 at isa0 port 0x2f8/8 irq 3: ns16550a, 16 byte fifo
> com1: probed fifo depth: 15 bytes
> pckbc0 at isa0 port 0x60/5
> pckbd0 at pckbc0 (kbd slot)
> pckbc0: using irq 1 for kbd slot
> wskbd0 at pckbd0: console keyboard, using wsdisplay0
> pcppi0 at isa0 port 0x61
> spkr0 at pcppi0
> lpt0 at isa0 port 0x378/4 irq 7
> usb6 at ohci4: USB revision 1.0
> uhub6 at usb6 "ATI OHCI root hub" rev 1.00/1.00 addr 1
> mtrr: Pentium Pro MTRR support
> uhidev0 at uhub3 port 2 configuration 1 interface 0 "Microsoft Basic
> Optical Mouse" rev 1.10/0.00 addr 2
> uhidev0: iclass 3/1
> ums0 at uhidev0: 3 buttons, Z dir
> wsmouse0 at ums0 mux 0
> uhidev1 at uhub3 port 3 configuration 1 interface 0 "Logitech Logitech
> USB Keyboard" rev 2.00/60.00 addr 3
> uhidev1: iclass 3/1
> ukbd0 at uhidev1: 8 modifier keys, 6 key codes
> wskbd1 at ukbd0 mux 1
> wskbd1: connecting to wsdisplay0
> uhidev2 at uhub3 port 3 configuration 1 interface 1 "Logitech Logitech
> USB Keyboard" rev 2.00/60.00 addr 3
> uhidev2: iclass 3/0, 4 report ids
> uhid0 at uhidev2 reportid 3: input=4, output=0, feature=0
> uhid1 at uhidev2 reportid 4: input=1, output=0, feature=0
> vscsi0 at root
> scsibus2 at vscsi0: 256 targets
> softraid0 at root
> root on sd0a swap on sd0b dump on sd0b
>
> --- /home/the00z/diff/alc.dmesgold B  B  B Sun May B 1 14:46:33 2011
> +++ /home/the00z/diff/alc.dmesg Sun May B 1 14:45:43 2011
> @@ -1,7 +1,7 @@
> -OpenBSD 4.9-current (kobj) #0: Tue Apr 26 18:02:56 CDT 2011
> +OpenBSD 4.9-current (kobj) #0: Sun May B 1 14:32:33 CDT 2011
> B  B  root@maetel.00z:/usr/kobj
> B real mem = 1608056832 (1533MB)
> -avail mem = 1551200256 (1479MB)
> +avail mem = 1551196160 (1479MB)
> B mainbus0 at root
> B bios0 at mainbus0: SMBIOS rev. 2.6 @ 0xfd400 (50 entries)
> B bios0: vendor American Megatrends Inc. version "V1.3" date 11/15/2010
> @@ -13,14 +13,14 @@
> B acpitimer0 at acpi0: 3579545 Hz, 32 bits
> B acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
> B cpu0 at mainbus0: apid 0 (boot processor)
> -cpu0: AMD Phenom(tm) II X4 955 Processor, 3200.65 MHz
> +cpu0: AMD Phenom(tm) II X4 955 Processor, 3200.55 MHz
> B cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUS
H,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DN
OW
> B cpu0: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
> 64b/line 16-way L2 cache
> B cpu0: ITLB 32 4KB entries fully associative, 16 4MB entries fully
associative
> B cpu0: DTLB 48 4KB entries fully associative, 48 4MB entries fully
associative
> B cpu0: apic clock running at 200MHz
> B cpu1 at mainbus0: apid 1 (application processor)
> -cpu1: AMD Phenom(tm) II X4 955 Processor, 3200.16 MHz
> +cpu1: AMD Phenom(tm) II X4 955 Processor, 3200.15 MHz
> B cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUS
H,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,CX16,POPCNT,NXE,MMXX,FFXSR,LONG,3DNOW2,3DN
OW
> B cpu1: 64KB 64b/line 2-way I-cache, 64KB 64b/line 2-way D-cache, 512KB
> 64b/line 16-way L2 cache
> B cpu1: ITLB 32 4KB entries fully associative, 16 4MB entries fully
associative

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Re: alc(4) support for Atheros AR815x

Edd Barrett
In reply to this post by Stuart Henderson
On Sun, May 01, 2011 at 08:10:56PM +0100, Stuart Henderson wrote:
> On 2011/05/01 18:35, Edd Barrett wrote:
> > I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
> > there an updated diff?
>
> Yes I just took the 2 minutes it took to apply it and fix
> the minor conflicts and linewrapping issue with the diff.
> Untested beyond "it builds".

Stu's diff seems to work, although the first time i booted my bsd.rd I was
unable to install due to:

alc0: watchdog timeout (missed link)

I rebooted and tried again and it all went smoothly. The system booted
multiuser and I am able to install packages over the wire.

The BCM4313 wireless is unsupported, but that is another story. If anyone knows
anything about support for this card can they mail me off-list.

Cheers

OpenBSD 4.9-current (GENERIC.MP) #0: Mon May  2 00:51:41 BST 2011
    [hidden email]:/usr/src/sys/arch/i386/compile/GENERIC.MP
cpu0: Intel(R) Atom(TM) CPU N455 @ 1.66GHz ("GenuineIntel" 686-class) 1.67 GHz
cpu0: FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,EST,TM2,SSSE3,CX16,xTPR,PDCM,MOVBE
real mem  = 1061302272 (1012MB)
avail mem = 1033764864 (985MB)
mainbus0 at root
bios0 at mainbus0: AT/286+ BIOS, date 01/10/11, SMBIOS rev. 2.6 @ 0xe8080 (36 entries)
bios0: vendor Packard Bell version "V3.14(DDR3)" date 01/10/2011
bios0: Packard Bell DOTS E2
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP HPET APIC MCFG SLIC BOOT SSDT WDAT
acpi0: wakeup devices UHC1(S3) UHC2(S3) UHC3(S3) UHC4(S3) ECHI(S3) EXP1(S4) EXP2(S0) EXP3(S4) EXP4(S4) AZAL(S4)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpihpet0 at acpi0: 14318179 Hz
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: apic clock running at 166MHz
cpu1 at mainbus0: apid 1 (application processor)
cpu1: Intel(R) Atom(TM) CPU N455 @ 1.66GHz ("GenuineIntel" 686-class) 1.67 GHz
cpu1: FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,EST,TM2,SSSE3,CX16,xTPR,PDCM,MOVBE
ioapic0 at mainbus0: apid 4 pa 0xfec00000, version 20, 24 pins
ioapic0: misconfigured as apic 0, remapped to apid 4
acpimcfg0 at acpi0 addr 0xe0000000, bus 0-255
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus 1 (EXP1)
acpiprt2 at acpi0: bus 2 (EXP2)
acpiprt3 at acpi0: bus -1 (EXP3)
acpiprt4 at acpi0: bus -1 (EXP4)
acpiec0 at acpi0
acpicpu0 at acpi0: C3, C2, C1, PSS
acpicpu1 at acpi0: C3, C2, C1, PSS
acpipwrres0 at acpi0: FN00
acpitz0 at acpi0: critical temperature 100 degC
acpibtn0 at acpi0: PWRB
acpibtn1 at acpi0: SLPB
acpibtn2 at acpi0: LID0
acpibat0 at acpi0: BAT0 model "13848628933250113" type Lion oem "SANYO "
acpiac0 at acpi0: AC unit online
acpivideo0 at acpi0: OVGA
acpivout0 at acpivideo0: DD02
bios0: ROM list: 0xc0000/0xda00! 0xce000/0x1000
cpu0: Enhanced SpeedStep 1663 MHz: speeds: 1666, 1333, 1000 MHz
pci0 at mainbus0 bus 0: configuration mode 1 (bios)
pchb0 at pci0 dev 0 function 0 "Intel Pineview DMI" rev 0x00
vga1 at pci0 dev 2 function 0 "Intel Pineview Video" rev 0x00
wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation)
wsdisplay0: screen 1-5 added (80x25, vt100 emulation)
intagp0 at vga1
agp0 at intagp0: aperture at 0x40000000, size 0x10000000
inteldrm0 at vga1: apic 4 int 16
drm0 at inteldrm0
"Intel Pineview Video" rev 0x00 at pci0 dev 2 function 1 not configured
azalia0 at pci0 dev 27 function 0 "Intel 82801GB HD Audio" rev 0x02: apic 4 int 19
azalia0: codecs: Realtek ALC272
audio0 at azalia0
ppb0 at pci0 dev 28 function 0 "Intel 82801GB PCIE" rev 0x02: apic 4 int 16
pci1 at ppb0 bus 1
alc0 at pci1 dev 0 function 0 "Attansic Technology L2C" rev 0xc1: apic 4 int 16, address 1c:75:08:d5:53:c4
atphy0 at alc0 phy 0: F2 10/100 PHY, rev. 4
ppb1 at pci0 dev 28 function 1 "Intel 82801GB PCIE" rev 0x02: apic 4 int 17
pci2 at ppb1 bus 2
"Broadcom BCM4313" rev 0x01 at pci2 dev 0 function 0 not configured
uhci0 at pci0 dev 29 function 0 "Intel 82801GB USB" rev 0x02: apic 4 int 18
uhci1 at pci0 dev 29 function 1 "Intel 82801GB USB" rev 0x02: apic 4 int 20
uhci2 at pci0 dev 29 function 2 "Intel 82801GB USB" rev 0x02: apic 4 int 21
uhci3 at pci0 dev 29 function 3 "Intel 82801GB USB" rev 0x02: apic 4 int 22
ehci0 at pci0 dev 29 function 7 "Intel 82801GB USB" rev 0x02: apic 4 int 22
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Intel EHCI root hub" rev 2.00/1.00 addr 1
ppb2 at pci0 dev 30 function 0 "Intel 82801BAM Hub-to-PCI" rev 0xe2
pci3 at ppb2 bus 5
pcib0 at pci0 dev 31 function 0 "Intel Tigerpoint LPC" rev 0x02
ahci0 at pci0 dev 31 function 2 "Intel 82801GR AHCI" rev 0x02: apic 4 int 17, AHCI 1.1
ahci0: PHY offline on port 1
scsibus0 at ahci0: 32 targets
sd0 at scsibus0 targ 0 lun 0: <ATA, Hitachi HTS54502, PB2O> SCSI3 0/direct fixed naa.5000cca62bf2b42f
sd0: 238475MB, 512 bytes/sec, 488397168 sec total
ichiic0 at pci0 dev 31 function 3 "Intel 82801GB SMBus" rev 0x02: apic 4 int 17
iic0 at ichiic0
spdmem0 at iic0 addr 0x50: 1GB DDR3 SDRAM PC3-10600 SO-DIMM
usb1 at uhci0: USB revision 1.0
uhub1 at usb1 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb2 at uhci1: USB revision 1.0
uhub2 at usb2 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb3 at uhci2: USB revision 1.0
uhub3 at usb3 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb4 at uhci3: USB revision 1.0
uhub4 at usb4 "Intel UHCI root hub" rev 1.00/1.00 addr 1
isa0 at pcib0
isadma0 at isa0
pckbc0 at isa0 port 0x60/5
pckbd0 at pckbc0 (kbd slot)
pckbc0: using irq 1 for kbd slot
wskbd0 at pckbd0: console keyboard, using wsdisplay0
pms0 at pckbc0 (aux slot)
pckbc0: using irq 12 for aux slot
wsmouse0 at pms0 mux 0
pcppi0 at isa0 port 0x61
spkr0 at pcppi0
npx0 at isa0 port 0xf0/16: reported by CPUID; using exception 16
mtrr: Pentium Pro MTRR support
uvideo0 at uhub0 port 4 configuration 1 interface 0 "Y2B2D0JXB WebCam" rev 2.00/0.04 addr 2
video0 at uvideo0
vscsi0 at root
scsibus1 at vscsi0: 256 targets
softraid0 at root
root on sd0a swap on sd0b dump on sd0b

--
Best Regards
Edd Barrett

http://www.theunixzoo.co.uk

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Re: alc(4) support for Atheros AR815x

Edd Barrett
On Mon, May 02, 2011 at 01:16:55AM +0100, Edd Barrett wrote:

> On Sun, May 01, 2011 at 08:10:56PM +0100, Stuart Henderson wrote:
> > On 2011/05/01 18:35, Edd Barrett wrote:
> > > I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
> > > there an updated diff?
> >
> > Yes I just took the 2 minutes it took to apply it and fix
> > the minor conflicts and linewrapping issue with the diff.
> > Untested beyond "it builds".
>
> Stu's diff seems to work, although the first time i booted my bsd.rd I was
> unable to install due to:
>
> alc0: watchdog timeout (missed link)

^ this seems to happen quite frequently. I just had the same issue again on the
installed system.

--
Best Regards
Edd Barrett

http://www.theunixzoo.co.uk

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Re: alc(4) support for Atheros AR815x

Kevin Lo
In reply to this post by Edd Barrett
On Sun, 2011-05-01 at 18:35 +0100, Edd Barrett wrote:

> On Thu, Apr 28, 2011 at 07:21:16AM +1000, Jonathan Gray wrote:
> > On Tue, Jan 25, 2011 at 06:24:28PM +0800, Kevin Lo wrote:
> > > Hi,
> > >
> > > The following diff adds support for Atheros AR8151/AR8152 chipsets;
> > > mostly from FreeBSD. It also fixes an issue i386/6311.
> > > Tested on Acer AOD255E.
> >
> > Is there an updated diff for this?  It seems this never made it
> > into the tree.
>
> I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
> there an updated diff?

Hi Edd,

A couple of days ago jsg@ asked the same question:
http://marc.info/?l=openbsd-tech&m=130393940030183&w=2

I forgot to cc tech@. Sorry, I've lacked alc hardware,
I have no updated diff.

        Kevin

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Re: alc(4) support for Atheros AR815x

Stuart Henderson
In reply to this post by Edd Barrett
On 2011/05/02 01:16, Edd Barrett wrote:

> On Sun, May 01, 2011 at 08:10:56PM +0100, Stuart Henderson wrote:
> > On 2011/05/01 18:35, Edd Barrett wrote:
> > > I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
> > > there an updated diff?
> >
> > Yes I just took the 2 minutes it took to apply it and fix
> > the minor conflicts and linewrapping issue with the diff.
> > Untested beyond "it builds".
>
> Stu's diff seems to work,

kevlo's diff really..

> although the first time i booted my bsd.rd I was
> unable to install due to:
>
> alc0: watchdog timeout (missed link)

I had a report of a system with alc(4) which only works if the
cable is connected at boot. Is that what happens for you too?
If so, try this, similar to freebsd r214542.

Index: if_alc.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_alc.c,v
retrieving revision 1.11
diff -u -p -r1.11 if_alc.c
--- if_alc.c 5 Apr 2011 18:01:21 -0000 1.11
+++ if_alc.c 2 May 2011 10:01:12 -0000
@@ -236,8 +236,8 @@ alc_miibus_statchg(struct device *dev)
  reg = CSR_READ_4(sc, ALC_MAC_CFG);
  reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
  CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
+ alc_aspm(sc);
  }
- alc_aspm(sc);
 }
 
 void

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Re: alc(4) support for Atheros AR815x

Edd Barrett
On Mon, May 02, 2011 at 11:02:41AM +0100, Stuart Henderson wrote:

> On 2011/05/02 01:16, Edd Barrett wrote:
> > On Sun, May 01, 2011 at 08:10:56PM +0100, Stuart Henderson wrote:
> > > On 2011/05/01 18:35, Edd Barrett wrote:
> > > > I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
> > > > there an updated diff?
> > >
> > > Yes I just took the 2 minutes it took to apply it and fix
> > > the minor conflicts and linewrapping issue with the diff.
> > > Untested beyond "it builds".
> >
> > Stu's diff seems to work,
>
> kevlo's diff really..
>
> > although the first time i booted my bsd.rd I was
> > unable to install due to:
> >
> > alc0: watchdog timeout (missed link)
>
> I had a report of a system with alc(4) which only works if the
> cable is connected at boot. Is that what happens for you too?
> If so, try this, similar to freebsd r214542.

This change was already included in kevlo's diff. It does seem like it could
still be related to the link state. I managed to get another error by:

 * booting with no cable plugged in.
 * once the system is up, connect a cable
 * run dhclient alc0

 Then as DHREQUESTs were sent some kernel messages:

alc0: watchdog timeout
alc0: could not disable RxQ/TxQ (0x00000008)!
alc0: could not disable RxQ/TxQ MAC(0x00000008)!

Might give some clues?

After those messages, the interface does infact recieve a DHCP address and the
interface does work. So I would not let this hold back the commit.

--
Best Regards
Edd Barrett

http://www.theunixzoo.co.uk

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Re: alc(4) support for Atheros AR815x

Alexey Suslikov
In reply to this post by Kevin Lo-3
Edd Barrett wrote:

> On Mon, May 02, 2011 at 11:02:41AM +0100, Stuart Henderson wrote:
> > On 2011/05/02 01:16, Edd Barrett wrote:
> > > On Sun, May 01, 2011 at 08:10:56PM +0100, Stuart Henderson wrote:
> > > > On 2011/05/01 18:35, Edd Barrett wrote:
> > > > > I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
> > > > > there an updated diff?
> > > >
> > > > Yes I just took the 2 minutes it took to apply it and fix
> > > > the minor conflicts and linewrapping issue with the diff.
> > > > Untested beyond "it builds".
> > >
> > > Stu's diff seems to work,
> >
> > kevlo's diff really..
> >
> > > although the first time i booted my bsd.rd I was
> > > unable to install due to:
> > >
> > > alc0: watchdog timeout (missed link)
> >
> > I had a report of a system with alc(4) which only works if the
> > cable is connected at boot. Is that what happens for you too?
> > If so, try this, similar to freebsd r214542.
>
> This change was already included in kevlo's diff. It does seem like it could
> still be related to the link state. I managed to get another error by:
>
> * booting with no cable plugged in.
> * once the system is up, connect a cable
> * run dhclient alc0
>
> Then as DHREQUESTs were sent some kernel messages:
>
> alc0: watchdog timeout

I have seen such a timeouts on age(4). The issue occurs irregularly, box just
stops responding over network for a while, records watchdog timeout and then
box become available again. dmesg follows (age(4) is dropped in favor of xl(4)
so no watchdog timeouts recorded at the moment).

From my understanding it can be a common issue with atphy(4) so both
alc(4) and age(4) are affected.

Alexey

OpenBSD 4.7-beta (GENERIC.MP) #82: Fri Feb  5 01:05:44 MST 2010
    [hidden email]:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 2145910784 (2046MB)
avail mem = 2079428608 (1983MB)
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 2.4 @ 0xf06e0 (71 entries)
bios0: vendor American Megatrends Inc. version "0603" date 07/03/2007
bios0: ASUSTeK Computer INC. P5K
acpi0 at bios0: rev 0
acpi0: tables DSDT FACP APIC MCFG OEMB HPET OSFR
acpi0: wakeup devices P0P2(S4) P0P1(S4) UAR1(S4) PS2K(S4) EUSB(S4)
USBE(S4) P0P5(S4) P0P6(S4) P0P7(S4) P0P8(S4) P0P9(S4) USB0(S4)
USB1(S4) USB2(S4) USB3(S4) USB4(S4) USB5(S4) USB6(S4) P0P4(S4)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Core(TM)2 Duo CPU E6750 @ 2.66GHz, 2671.97 MHz
cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,SMX,EST,TM2,CX16,xTPR,NXE,LONG
cpu0: 4MB 64b/line 16-way L2 cache
cpu0: apic clock running at 333MHz
cpu1 at mainbus0: apid 1 (application processor)
cpu1: Intel(R) Core(TM)2 Duo CPU E6750 @ 2.66GHz, 2671.61 MHz
cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,SMX,EST,TM2,CX16,xTPR,NXE,LONG
cpu1: 4MB 64b/line 16-way L2 cache
ioapic0 at mainbus0: apid 2 pa 0xfec00000, version 20, 24 pins
acpihpet0 at acpi0: 14318179 Hz
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus 1 (P0P2)
acpiprt2 at acpi0: bus 5 (P0P1)
acpiprt3 at acpi0: bus -1 (P0P5)
acpiprt4 at acpi0: bus -1 (P0P6)
acpiprt5 at acpi0: bus -1 (P0P7)
acpiprt6 at acpi0: bus 3 (P0P8)
acpiprt7 at acpi0: bus 2 (P0P9)
acpiprt8 at acpi0: bus 4 (P0P4)
acpicpu0 at acpi0: PSS
acpicpu1 at acpi0: PSS
aibs0 at acpi0
acpibtn0 at acpi0: PWRB
cpu0: Enhanced SpeedStep 2671 MHz: speeds: 2664, 1998 MHz
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 "Intel 82G33 Host" rev 0x02
ppb0 at pci0 dev 1 function 0 "Intel 82G33 PCIE" rev 0x02: apic 2 int
16 (irq 11)
pci1 at ppb0 bus 1
vga1 at pci1 dev 0 function 0 vendor "NVIDIA", unknown product 0x0400 rev 0xa1
wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation)
wsdisplay0: screen 1-5 added (80x25, vt100 emulation)
uhci0 at pci0 dev 26 function 0 "Intel 82801I USB" rev 0x02: apic 2
int 16 (irq 11)
uhci1 at pci0 dev 26 function 1 "Intel 82801I USB" rev 0x02: apic 2
int 21 (irq 3)
uhci2 at pci0 dev 26 function 2 "Intel 82801I USB" rev 0x02: apic 2
int 18 (irq 5)
ehci0 at pci0 dev 26 function 7 "Intel 82801I USB" rev 0x02: apic 2
int 18 (irq 5)
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Intel EHCI root hub" rev 2.00/1.00 addr 1
azalia0 at pci0 dev 27 function 0 "Intel 82801I HD Audio" rev 0x02:
apic 2 int 22 (irq 15)
azalia0: codecs: Realtek ALC883
audio0 at azalia0
ppb1 at pci0 dev 28 function 0 "Intel 82801I PCIE" rev 0x02: apic 2
int 17 (irq 10)
pci2 at ppb1 bus 4
ppb2 at pci0 dev 28 function 4 "Intel 82801I PCIE" rev 0x02: apic 2
int 17 (irq 10)
pci3 at ppb2 bus 3
jmb0 at pci3 dev 0 function 0 "JMicron JMB363 IDE/SATA" rev 0x03
ahci0 at jmb0: apic 2 int 16 (irq 11), AHCI 1.0
scsibus0 at ahci0: 32 targets
pciide0 at jmb0: DMA, channel 0 wired to native-PCI, channel 1 wired
to native-PCI
pciide0: using apic 2 int 16 (irq 11) for native-PCI interrupt
pciide0: channel 0 disabled (no drives)
pciide0: channel 1 disabled (no drives)
ppb3 at pci0 dev 28 function 5 "Intel 82801I PCIE" rev 0x02: apic 2
int 16 (irq 11)
pci4 at ppb3 bus 2
age0 at pci4 dev 0 function 0 "Attansic Technology L1" rev 0xb0: apic
2 int 17 (irq 10), address 00:1b:fc:5a:2b:66
atphy0 at age0 phy 0: F1 10/100/1000 PHY, rev. 5
uhci3 at pci0 dev 29 function 0 "Intel 82801I USB" rev 0x02: apic 2
int 23 (irq 7)
uhci4 at pci0 dev 29 function 1 "Intel 82801I USB" rev 0x02: apic 2
int 19 (irq 14)
uhci5 at pci0 dev 29 function 2 "Intel 82801I USB" rev 0x02: apic 2
int 18 (irq 5)
ehci1 at pci0 dev 29 function 7 "Intel 82801I USB" rev 0x02: apic 2
int 23 (irq 7)
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 "Intel EHCI root hub" rev 2.00/1.00 addr 1
ppb4 at pci0 dev 30 function 0 "Intel 82801BA Hub-to-PCI" rev 0x92
pci5 at ppb4 bus 5
xl0 at pci5 dev 2 function 0 "3Com 3c905C 100Base-TX" rev 0x78: apic 2
int 18 (irq 5), address 00:03:99:89:c7:1c
bmtphy0 at xl0 phy 24: 3C905C internal PHY, rev. 7
"VIA VT6306 FireWire" rev 0xc0 at pci5 dev 3 function 0 not configured
pcib0 at pci0 dev 31 function 0 "Intel 82801IB LPC" rev 0x02
pciide1 at pci0 dev 31 function 2 "Intel 82801I SATA" rev 0x02: DMA,
channel 0 configured to native-PCI, channel 1 configured to native-PCI
pciide1: using apic 2 int 22 (irq 15) for native-PCI interrupt
atapiscsi0 at pciide1 channel 0 drive 0
scsibus1 at atapiscsi0: 2 targets
cd0 at scsibus1 targ 0 lun 0: <Optiarc, DVD RW AD-7170S, 1.00> ATAPI
5/cdrom removable
cd0(pciide1:0:0): using PIO mode 4, Ultra-DMA mode 4
wd0 at pciide1 channel 1 drive 0: <ST3500630AS>
wd0: 16-sector PIO, LBA48, 476940MB, 976773168 sectors
wd0(pciide1:1:0): using PIO mode 4, Ultra-DMA mode 6
ichiic0 at pci0 dev 31 function 3 "Intel 82801I SMBus" rev 0x02: apic
2 int 18 (irq 5)
iic0 at ichiic0
spdmem0 at iic0 addr 0x50: 1GB DDR2 SDRAM non-parity PC2-6400CL5
spdmem1 at iic0 addr 0x52: 1GB DDR2 SDRAM non-parity PC2-6400CL5
pciide2 at pci0 dev 31 function 5 "Intel 82801I SATA" rev 0x02: DMA,
channel 0 wired to native-PCI, channel 1 wired to native-PCI
pciide2: using apic 2 int 22 (irq 15) for native-PCI interrupt
usb2 at uhci0: USB revision 1.0
uhub2 at usb2 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb3 at uhci1: USB revision 1.0
uhub3 at usb3 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb4 at uhci2: USB revision 1.0
uhub4 at usb4 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb5 at uhci3: USB revision 1.0
uhub5 at usb5 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb6 at uhci4: USB revision 1.0
uhub6 at usb6 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb7 at uhci5: USB revision 1.0
uhub7 at usb7 "Intel UHCI root hub" rev 1.00/1.00 addr 1
isa0 at pcib0
isadma0 at isa0
com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
pckbc0 at isa0 port 0x60/5
pcppi0 at isa0 port 0x61
midi0 at pcppi0: <PC speaker>
spkr0 at pcppi0
wbsio0 at isa0 port 0x2e/2: W83627DHG rev 0x23
lm1 at wbsio0 port 0x290/8: W83627DHG
mtrr: Pentium Pro MTRR support
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
root on wd0a swap on wd0b dump on wd0b

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Re: alc(4) support for Atheros AR815x

Gabriel Linder
In reply to this post by Edd Barrett
On 05/02/11 14:23, Edd Barrett wrote:

> On Mon, May 02, 2011 at 11:02:41AM +0100, Stuart Henderson wrote:
>> On 2011/05/02 01:16, Edd Barrett wrote:
>>> On Sun, May 01, 2011 at 08:10:56PM +0100, Stuart Henderson wrote:
>>>> On 2011/05/01 18:35, Edd Barrett wrote:
>>>>> I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
>>>>> there an updated diff?
>>>> Yes I just took the 2 minutes it took to apply it and fix
>>>> the minor conflicts and linewrapping issue with the diff.
>>>> Untested beyond "it builds".
>>> Stu's diff seems to work,
>> kevlo's diff really..
>>
>>> although the first time i booted my bsd.rd I was
>>> unable to install due to:
>>>
>>> alc0: watchdog timeout (missed link)
>> I had a report of a system with alc(4) which only works if the
>> cable is connected at boot. Is that what happens for you too?
>> If so, try this, similar to freebsd r214542.
> This change was already included in kevlo's diff. It does seem like it could
> still be related to the link state. I managed to get another error by:
>
>   * booting with no cable plugged in.
>   * once the system is up, connect a cable
>   * run dhclient alc0
>
>   Then as DHREQUESTs were sent some kernel messages:
>
> alc0: watchdog timeout
> alc0: could not disable RxQ/TxQ (0x00000008)!
> alc0: could not disable RxQ/TxQ MAC(0x00000008)!
>
> Might give some clues?
>
> After those messages, the interface does infact recieve a DHCP address and the
> interface does work. So I would not let this hold back the commit.
>

Some hints :
http://marc.info/?l=openbsd-tech&m=129651174131694&w=2
http://dargor.servebeer.com/~dargor/openbsd/alc/ (very old diffs)

I have an alc device too, and would like to fix it. Starting from
kevlo's diff I updated it some month ago to compile, and compared
FreeBSD driver to add some more things, finding some bugs in their
driver (reported and fixed in their tree). I now have a working alc,
with and without cable at boot or after boot but I have to update my
tree (lagging some months behind) and probably fix some conflicts before
posting an up to date diff. It would help me if someone could answer my
silly questions about differences between FreeBSD and OpenBSD internals,
by the way. Slides at http://www.openbsd.org/papers/ were very useful
but do not cover this :)

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Re: alc(4) support for Atheros AR815x

Edd Barrett
On Wed, May 04, 2011 at 09:32:47AM +0200, Gabriel Linder wrote:

> I have an alc device too, and would like to fix it. Starting from
> kevlo's diff I updated it some month ago to compile, and compared
> FreeBSD driver to add some more things, finding some bugs in their
> driver (reported and fixed in their tree). I now have a working alc,
> with and without cable at boot or after boot but I have to update my
> tree (lagging some months behind) and probably fix some conflicts
> before posting an up to date diff. It would help me if someone could
> answer my silly questions about differences between FreeBSD and
> OpenBSD internals, by the way. Slides at
> http://www.openbsd.org/papers/ were very useful but do not cover
> this :)

FYI, Marius just made a huge commit which includes some alc/PHY code. I
don't know if it is relevent.
http://svnweb.freebsd.org/base?view=revision&revision=221407

--
Best Regards
Edd Barrett

http://www.theunixzoo.co.uk

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Re: alc(4) support for Atheros AR815x

Stuart Henderson
In reply to this post by Stuart Henderson
So far, only had reports from L1C and the new devices (which is
not the point of sending out this sort of diff). This is a fairly
large diff and changes behaviour for existing devices.

Has anyone with a currently-working L2C tested this to make sure
it doesn't break their nic?


On 2011/05/01 20:10, Stuart Henderson wrote:

> On 2011/05/01 18:35, Edd Barrett wrote:
> > I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
> > there an updated diff?
>
> Yes I just took the 2 minutes it took to apply it and fix
> the minor conflicts and linewrapping issue with the diff.
> Untested beyond "it builds".
>
> Test reports and dmesg lines from existing working alc(4) L1C and
> L2C wanted. If it makes new chips work that's a bonus, but the
> important thing is making sure it doesn't break something that
> already works.
>
> Doesn't seem any point disabling interrupts in the ISR though.
> I haven't touched that in this diff but that should probably be
> done too.

Index: share/man/man4/alc.4
===================================================================
RCS file: /cvs/src/share/man/man4/alc.4,v
retrieving revision 1.2
diff -u -p -r1.2 alc.4
--- share/man/man4/alc.4 8 Aug 2009 14:12:41 -0000 1.2
+++ share/man/man4/alc.4 1 May 2011 18:55:25 -0000
@@ -19,7 +19,7 @@
 .Os
 .Sh NAME
 .Nm alc
-.Nd Atheros AR8131/AR8132 10/100/Gigabit Ethernet device
+.Nd Atheros AR813x/AR815x 10/100/Gigabit Ethernet device
 .Sh SYNOPSIS
 .Cd "alc* at pci?"
 .Cd "atphy* at mii?"
@@ -27,8 +27,7 @@
 The
 .Nm
 driver provides support for Ethernet interfaces based on the
-Atheros AR8131/AR8132 Ethernet chipset, also known as
-the Attansic L1C/L2C respectively.
+Atheros AR813x/AR815x Ethernet chipset.
 .Pp
 The
 .Nm
Index: sys/arch/amd64/conf/GENERIC
===================================================================
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.316
diff -u -p -r1.316 GENERIC
--- sys/arch/amd64/conf/GENERIC 10 Apr 2011 20:27:02 -0000 1.316
+++ sys/arch/amd64/conf/GENERIC 1 May 2011 18:55:25 -0000
@@ -472,7 +472,7 @@ bce* at pci? # Broadcom BCM4401
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/arch/amd64/conf/RAMDISK_CD
===================================================================
RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
retrieving revision 1.116
diff -u -p -r1.116 RAMDISK_CD
--- sys/arch/amd64/conf/RAMDISK_CD 3 Apr 2011 12:32:05 -0000 1.116
+++ sys/arch/amd64/conf/RAMDISK_CD 1 May 2011 18:55:25 -0000
@@ -291,7 +291,7 @@ bce* at pci? # Broadcom BCM4401
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/arch/i386/conf/GENERIC
===================================================================
RCS file: /cvs/src/sys/arch/i386/conf/GENERIC,v
retrieving revision 1.713
diff -u -p -r1.713 GENERIC
--- sys/arch/i386/conf/GENERIC 10 Apr 2011 20:27:02 -0000 1.713
+++ sys/arch/i386/conf/GENERIC 1 May 2011 18:55:25 -0000
@@ -632,7 +632,7 @@ gem* at pci? # Sun 'gem' ethernet
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/arch/i386/conf/RAMDISK_CD
===================================================================
RCS file: /cvs/src/sys/arch/i386/conf/RAMDISK_CD,v
retrieving revision 1.185
diff -u -p -r1.185 RAMDISK_CD
--- sys/arch/i386/conf/RAMDISK_CD 3 Apr 2011 12:32:05 -0000 1.185
+++ sys/arch/i386/conf/RAMDISK_CD 1 May 2011 18:55:25 -0000
@@ -372,7 +372,7 @@ xge* at pci? # Neterion Xframe-I/II 1
 vic* at pci? # VMware VMXnet virtual interface
 et* at pci? # Agere/LSI ET1310
 age* at pci? # Attansic L1 Ethernet
-alc* at pci? # Attansic L1C/L2C Ethernet
+alc* at pci? # Attansic L1C/L1D/L2C Ethernet
 ale* at pci? # Attansic L1E Ethernet
 lii* at pci? # Attansic L2 Ethernet
 jme* at pci? # JMicron JMC250/JMC260 Ethernet
Index: sys/dev/pci/files.pci
===================================================================
RCS file: /cvs/src/sys/dev/pci/files.pci,v
retrieving revision 1.278
diff -u -p -r1.278 files.pci
--- sys/dev/pci/files.pci 10 Apr 2011 20:27:02 -0000 1.278
+++ sys/dev/pci/files.pci 1 May 2011 18:55:25 -0000
@@ -643,7 +643,7 @@ device age: ether, ifnet, mii, ifmedia,
 attach age at pci
 file dev/pci/if_age.c age
 
-# Attansic/Atheros L1C/L2C Gigabit Ethernet
+# Attansic/Atheros L1C/L1D/L2C Gigabit Ethernet
 device alc: ether, ifnet, mii, ifmedia, mii_phy
 attach alc at pci
 file dev/pci/if_alc.c alc
Index: sys/dev/pci/if_alc.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_alc.c,v
retrieving revision 1.11
diff -u -p -r1.11 if_alc.c
--- sys/dev/pci/if_alc.c 5 Apr 2011 18:01:21 -0000 1.11
+++ sys/dev/pci/if_alc.c 1 May 2011 18:55:25 -0000
@@ -88,7 +88,7 @@ void alc_watchdog(struct ifnet *);
 int alc_mediachange(struct ifnet *);
 void alc_mediastatus(struct ifnet *, struct ifmediareq *);
 
-void alc_aspm(struct alc_softc *);
+void alc_aspm(struct alc_softc *, int);
 void alc_disable_l0s_l1(struct alc_softc *);
 int alc_dma_alloc(struct alc_softc *);
 void alc_dma_free(struct alc_softc *);
@@ -109,7 +109,7 @@ void alc_phy_down(struct alc_softc *);
 void alc_phy_reset(struct alc_softc *);
 void alc_reset(struct alc_softc *);
 void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
-int alc_rxintr(struct alc_softc *);
+void alc_rxintr(struct alc_softc *);
 void alc_iff(struct alc_softc *);
 void alc_rxvlan(struct alc_softc *);
 void alc_start_queue(struct alc_softc *);
@@ -125,7 +125,11 @@ uint32_t alc_dma_burst[] = { 128, 256, 5
 
 const struct pci_matchid alc_devices[] = {
  { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C },
- { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 },
+ { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 }
 };
 
 struct cfattach alc_ca = {
@@ -236,8 +240,8 @@ alc_miibus_statchg(struct device *dev)
  reg = CSR_READ_4(sc, ALC_MAC_CFG);
  reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
  CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
+ alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active));
  }
- alc_aspm(sc);
 }
 
 void
@@ -280,20 +284,53 @@ void
 alc_get_macaddr(struct alc_softc *sc)
 {
  uint32_t ea[2], opt;
- int i;
+ uint16_t val;
+ int eeprom, i;
 
+ eeprom = 0;
  opt = CSR_READ_4(sc, ALC_OPT_CFG);
- if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
+ if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
+    (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
  /*
  * EEPROM found, let TWSI reload EEPROM configuration.
  * This will set ethernet address of controller.
  */
- if ((opt & OPT_CFG_CLK_ENB) == 0) {
- opt |= OPT_CFG_CLK_ENB;
- CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
- CSR_READ_4(sc, ALC_OPT_CFG);
- DELAY(1000);
+ eeprom++;
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1C:
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ if ((opt & OPT_CFG_CLK_ENB) == 0) {
+ opt |= OPT_CFG_CLK_ENB;
+ CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
+ CSR_READ_4(sc, ALC_OPT_CFG);
+ DELAY(1000);
+ }
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x00);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val & 0xFF7F);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x3B);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val | 0x0008);
+ DELAY(20);
+ break;
  }
+
+ CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
+    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
+ CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
+ CSR_READ_4(sc, ALC_WOL_CFG);
+
  CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
     TWSI_CFG_SW_LD_START);
  for (i = 100; i > 0; i--) {
@@ -309,11 +346,36 @@ alc_get_macaddr(struct alc_softc *sc)
  if (alcdebug)
  printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname);
  }
- if ((opt & OPT_CFG_CLK_ENB) != 0) {
- opt &= ~OPT_CFG_CLK_ENB;
- CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
- CSR_READ_4(sc, ALC_OPT_CFG);
- DELAY(1000);
+ if (eeprom != 0) {
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1C:
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ if ((opt & OPT_CFG_CLK_ENB) != 0) {
+ opt &= ~OPT_CFG_CLK_ENB;
+ CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
+ CSR_READ_4(sc, ALC_OPT_CFG);
+ DELAY(1000);
+ }
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x00);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val | 0x0080);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x3B);
+ val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, val & 0xFFF7);
+ DELAY(20);
+ break;
+ }
  }
 
  ea[0] = CSR_READ_4(sc, ALC_PAR0);
@@ -358,6 +420,43 @@ alc_phy_reset(struct alc_softc *sc)
  CSR_READ_2(sc, ALC_GPHY_CFG);
  DELAY(10 * 1000);
 
+ /* DSP fixup, Vendor magic. */
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x000A);
+ data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, data & 0xDFFF);
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x003B);
+ data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, data & 0xFFF7);
+ DELAY(20 * 1000);
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x0029);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, 0x929D);
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_ADDR, 0x0029);
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    ALC_MII_DBG_DATA, 0xB6DD);
+ }
+
  /* Load DSP codes, vendor magic. */
  data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
     ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
@@ -406,35 +505,114 @@ alc_phy_reset(struct alc_softc *sc)
 void
 alc_phy_down(struct alc_softc *sc)
 {
-
- /* Force PHY down. */
- CSR_WRITE_2(sc, ALC_GPHY_CFG,
-    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
-    GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW);
- DELAY(1000);
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ /*
+ * GPHY power down caused more problems on AR8151 v2.0.
+ * When driver is reloaded after GPHY power down,
+ * accesses to PHY/MAC registers hung the system. Only
+ * cold boot recovered from it.  I'm not sure whether
+ * AR8151 v1.0 also requires this one though.  I don't
+ * have AR8151 v1.0 controller in hand.
+ * The only option left is to isolate the PHY and
+ * initiates power down the PHY which in turn saves
+ * more power when driver is unloaded.
+ */
+ alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
+    MII_BMCR, BMCR_ISO | BMCR_PDOWN);
+ break;
+ default:
+ /* Force PHY down. */
+ CSR_WRITE_2(sc, ALC_GPHY_CFG,
+    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
+    GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
+    GPHY_CFG_PWDOWN_HW);
+ DELAY(1000);
+ break;
+ }
 }
 
 void
-alc_aspm(struct alc_softc *sc)
+alc_aspm(struct alc_softc *sc, int media)
 {
  uint32_t pmcfg;
+ uint16_t linkcfg;
 
  pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
+ if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
+    (ALC_FLAG_APS | ALC_FLAG_PCIE))
+ linkcfg = CSR_READ_2(sc, sc->alc_expcap +
+    PCI_PCIE_LCSR);
+ else
+ linkcfg = 0;
  pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
- pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB;
- pmcfg |= PM_CFG_SERDES_L1_ENB;
- pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
+ pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
  pmcfg |= PM_CFG_MAC_ASPM_CHK;
+ pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
+ pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
+
+ if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
+ /* Disable extended sync except AR8152 B v1.0 */
+ linkcfg &= ~0x80;
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
+    sc->alc_rev == ATHEROS_AR8152_B_V10)
+ linkcfg |= 0x80;
+ CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR,
+    linkcfg);
+ pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
+    PM_CFG_HOTRST);
+ pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
+ pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
+    PM_CFG_PM_REQ_TIMER_SHIFT);
+ pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
+ }
+
  if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
- pmcfg |= PM_CFG_SERDES_PLL_L1_ENB;
- pmcfg &= ~PM_CFG_CLK_SWH_L1;
- pmcfg &= ~PM_CFG_ASPM_L1_ENB;
- pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
+ pmcfg |= PM_CFG_ASPM_L0S_ENB;
+ if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
+ pmcfg |= PM_CFG_ASPM_L1_ENB;
+ if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
+ pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
+    PM_CFG_SERDES_PLL_L1_ENB |
+    PM_CFG_SERDES_BUDS_RX_L1_ENB);
+ pmcfg |= PM_CFG_CLK_SWH_L1;
+ if (media == IFM_100_TX || media == IFM_1000_T) {
+ pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ pmcfg |= (7 <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ pmcfg |= (4 <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ break;
+ default:
+ pmcfg |= (15 <<
+    PM_CFG_L1_ENTRY_TIMER_SHIFT);
+ break;
+ }
+ }
+ } else {
+ pmcfg |= PM_CFG_SERDES_L1_ENB |
+    PM_CFG_SERDES_PLL_L1_ENB |
+    PM_CFG_SERDES_BUDS_RX_L1_ENB;
+ pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
+    PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
+ }
  } else {
- pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB;
+ pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
+    PM_CFG_SERDES_PLL_L1_ENB);
  pmcfg |= PM_CFG_CLK_SWH_L1;
- pmcfg &= ~PM_CFG_ASPM_L1_ENB;
- pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
+ pmcfg |= PM_CFG_ASPM_L1_ENB;
  }
  CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
 }
@@ -450,9 +628,9 @@ alc_attach(struct device *parent, struct
  const char *intrstr;
  struct ifnet *ifp;
  pcireg_t memtype;
- char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" };
+ char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
  uint16_t burst;
- int base, mii_flags, state, error = 0;
+ int base, state, error = 0;
  uint32_t cap, ctl, val;
 
  /*
@@ -499,6 +677,7 @@ alc_attach(struct device *parent, struct
  if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
     &base, NULL)) {
  sc->alc_flags |= ALC_FLAG_PCIE;
+ sc->alc_expcap = base;
  burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
     base + PCI_PCIE_DCSR) >> 16;
  sc->alc_dma_rd_burst = (burst & 0x7000) >> 12;
@@ -515,6 +694,20 @@ alc_attach(struct device *parent, struct
  val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
  val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
  CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
+ CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
+    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
+ CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
+    CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
+    PCIE_PHYMISC_FORCE_RCV_DET);
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
+    sc->alc_rev == ATHEROS_AR8152_B_V10) {
+ val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
+ val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
+    PCIE_PHYMISC2_SERDES_TH_MASK);
+ val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
+ val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
+ CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
+ }
  /* Disable ASPM L0S and L1. */
  cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
     base + PCI_PCIE_LCAP) >> 16;
@@ -528,13 +721,16 @@ alc_attach(struct device *parent, struct
     sc->sc_dev.dv_xname,
     sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
  state = ctl & 0x03;
+ if (state & 0x01)
+ sc->alc_flags |= ALC_FLAG_L0S;
+ if (state & 0x02)
+ sc->alc_flags |= ALC_FLAG_L1S;
  if (alcdebug)
  printf("%s: ASPM %s %s\n",
     sc->sc_dev.dv_xname,
     aspm_state[state],
     state == 0 ? "disabled" : "enabled");
- if (state != 0)
- alc_disable_l0s_l1(sc);
+ alc_disable_l0s_l1(sc);
  }
  }
 
@@ -551,12 +747,39 @@ alc_attach(struct device *parent, struct
  * used in AR8132 can't establish gigabit link even if it
  * shows the same PHY model/revision number of AR8131.
  */
- if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_L2C)
- sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO;
- else
- sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON;
+ sc->sc_product = PCI_PRODUCT(pa->pa_id);
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ sc->alc_flags |= ALC_FLAG_APS;
+ /* FALLTHROUGH */
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ sc->alc_flags |= ALC_FLAG_FASTETHER;
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ sc->alc_flags |= ALC_FLAG_APS;
+ /* FALLTHROUGH */
+ default:
+ break;
+ }
+ sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO;
+
+ switch (sc->sc_product) {
+ case PCI_PRODUCT_ATTANSIC_L1C:
+ case PCI_PRODUCT_ATTANSIC_L2C:
+ sc->alc_max_framelen = 9 * 1024;
+ break;
+ case PCI_PRODUCT_ATTANSIC_L1D:
+ case PCI_PRODUCT_ATTANSIC_L1D_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_1:
+ case PCI_PRODUCT_ATTANSIC_L2C_2:
+ sc->alc_max_framelen = 6 * 1024;
+ break;
+ }
+
  /*
- * It seems that AR8131/AR8132 has silicon bug for SMB. In
+ * It seems that AR813x/AR815x has silicon bug for SMB. In
  * addition, Atheros said that enabling SMB wouldn't improve
  * performance. However I think it's bad to access lots of
  * registers to extract MAC statistics.
@@ -619,11 +842,8 @@ alc_attach(struct device *parent, struct
 
  ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange,
     alc_mediastatus);
- mii_flags = 0;
- if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0)
- mii_flags |= MIIF_DOPAUSE;
  mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY,
- MII_OFFSET_ANY, mii_flags);
+ MII_OFFSET_ANY, MIIF_DOPAUSE);
 
  if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) {
  printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
@@ -1136,16 +1356,15 @@ alc_start(struct ifnet *ifp)
 {
  struct alc_softc *sc = ifp->if_softc;
  struct mbuf *m_head;
- int enq;
-
- if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
- return;
+ int enq = 0;
 
  /* Reclaim transmitted frames. */
  if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
  alc_txeof(sc);
 
- enq = 0;
+ if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
+ return;
+
  for (;;) {
  IFQ_DEQUEUE(&ifp->if_snd, m_head);
  if (m_head == NULL)
@@ -1162,7 +1381,7 @@ alc_start(struct ifnet *ifp)
  ifp->if_flags |= IFF_OACTIVE;
  break;
  }
- enq = 1;
+ enq++;
 
 #if NBPFILTER > 0
  /*
@@ -1174,7 +1393,7 @@ alc_start(struct ifnet *ifp)
 #endif
  }
 
- if (enq) {
+ if (enq > 0) {
  /* Sync descriptors. */
  bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
     sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
@@ -1274,6 +1493,10 @@ alc_mac_config(struct alc_softc *sc)
  reg = CSR_READ_4(sc, ALC_MAC_CFG);
  reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
     MAC_CFG_SPEED_MASK);
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
+ reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
  /* Reprogram MAC with resolved speed/duplex. */
  switch (IFM_SUBTYPE(mii->mii_media_active)) {
  case IFM_10_T:
@@ -1451,24 +1674,25 @@ alc_intr(void *arg)
  struct alc_softc *sc = arg;
  struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  uint32_t status;
+ int claimed = 0;
 
  status = CSR_READ_4(sc, ALC_INTR_STATUS);
  if ((status & ALC_INTRS) == 0)
  return (0);
 
+ /* Disable interrupts. */
+ CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
+
+ status = CSR_READ_4(sc, ALC_INTR_STATUS);
+ if ((status & ALC_INTRS) == 0)
+ goto back;
+
  /* Acknowledge and disable interrupts. */
  CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
 
  if (ifp->if_flags & IFF_RUNNING) {
- if (status & INTR_RX_PKT) {
- int error;
-
- error = alc_rxintr(sc);
- if (error) {
- alc_init(ifp);
- return (0);
- }
- }
+ if (status & INTR_RX_PKT)
+ alc_rxintr(sc);
 
  if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
     INTR_TXQ_TO_RST)) {
@@ -1485,14 +1709,17 @@ alc_intr(void *arg)
  return (0);
  }
 
- alc_txeof(sc);
- if (!IFQ_IS_EMPTY(&ifp->if_snd))
+ if (status & INTR_TX_PKT) {
+ alc_txeof(sc);
+    if (!IFQ_IS_EMPTY(&ifp->if_snd))
  alc_start(ifp);
+ }
  }
-
+ claimed = 1;
+back:
  /* Re-enable interrupts. */
  CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
- return (1);
+ return (claimed);
 }
 
 void
@@ -1507,7 +1734,7 @@ alc_txeof(struct alc_softc *sc)
  return;
  bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
     sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
-    BUS_DMASYNC_POSTREAD);
+    BUS_DMASYNC_POSTWRITE);
  if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
  bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
     sc->alc_cdata.alc_cmb_map->dm_mapsize,
@@ -1591,7 +1818,7 @@ alc_newbuf(struct alc_softc *sc, struct
  return (0);
 }
 
-int
+void
 alc_rxintr(struct alc_softc *sc)
 {
  struct ifnet *ifp = &sc->sc_arpcom.ac_if;
@@ -1615,7 +1842,7 @@ alc_rxintr(struct alc_softc *sc)
  if (alcdebug)
  printf("%s: unexpected segment count -- "
     "resetting\n", sc->sc_dev.dv_xname);
- return (EIO);
+ break;
  }
  alc_rxeof(sc, rrd);
  /* Clear Rx return status. */
@@ -1653,8 +1880,6 @@ alc_rxintr(struct alc_softc *sc)
  CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
     sc->alc_cdata.alc_rx_cons);
  }
-
- return (0);
 }
 
 /* Receive a frame. */
@@ -1686,9 +1911,8 @@ alc_rxeof(struct alc_softc *sc, struct r
  *  Force network stack compute checksum for
  *  errored frames.
  */
- status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
- if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC |
-    RRD_ERR_RUNT) != 0)
+ if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN |
+    RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0)
  return;
  }
 
@@ -1801,7 +2025,9 @@ alc_reset(struct alc_softc *sc)
  uint32_t reg;
  int i;
 
- CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET);
+ reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF;
+ reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
+ CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
  for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
  DELAY(10);
  if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
@@ -1852,6 +2078,9 @@ alc_init(struct ifnet *ifp)
  alc_init_cmb(sc);
  alc_init_smb(sc);
 
+ /* Enable all clocks. */
+ CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
+
  /* Reprogram the station address. */
  bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN);
  CSR_WRITE_4(sc, ALC_PAR0,
@@ -1913,6 +2142,18 @@ alc_init(struct ifnet *ifp)
  CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
  CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
 
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
+ /* Reconfigure SRAM - Vendor magic. */
+ CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
+ CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
+ CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
+ CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
+ CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
+ CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
+ CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
+ CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
+ }
+
  /* Tell hardware that we're ready to load DMA blocks. */
  CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
 
@@ -1922,14 +2163,11 @@ alc_init(struct ifnet *ifp)
  reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
  reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
  CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
- reg = CSR_READ_4(sc, ALC_MASTER_CFG);
- reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
  /*
  * We don't want to automatic interrupt clear as task queue
  * for the interrupt should know interrupt status.
  */
- reg &= ~MASTER_INTR_RD_CLR;
- reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
+ reg = MASTER_SA_TIMER_ENB;
  if (ALC_USECS(sc->alc_int_rx_mod) != 0)
  reg |= MASTER_IM_RX_TIMER_ENB;
  if (ALC_USECS(sc->alc_int_tx_mod) != 0)
@@ -1970,7 +2208,7 @@ alc_init(struct ifnet *ifp)
  * Be conservative in what you do, be liberal in what you
  * accept from others - RFC 793.
  */
- CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN);
+ CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen);
 
  /* Disable header split(?) */
  CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
@@ -1997,11 +2235,14 @@ alc_init(struct ifnet *ifp)
  * TSO/checksum offloading.
  */
  CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
-    (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
+    (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
     TSO_OFFLOAD_THRESH_MASK);
  /* Configure TxQ. */
  reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
     TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
+ reg >>= 1;
  reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
     TXQ_CFG_TD_BURST_MASK;
  CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
@@ -2018,14 +2259,22 @@ alc_init(struct ifnet *ifp)
  * XON  : 80% of Rx FIFO
  * XOFF : 30% of Rx FIFO
  */
- reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
- rxf_hi = (reg * 8) / 10;
- rxf_lo = (reg * 3)/ 10;
- CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
-    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
-    RX_FIFO_PAUSE_THRESH_LO_MASK) |
-    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
-     RX_FIFO_PAUSE_THRESH_HI_MASK));
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) {
+ reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
+ rxf_hi = (reg * 8) / 10;
+ rxf_lo = (reg * 3) / 10;
+ CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
+    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
+    RX_FIFO_PAUSE_THRESH_LO_MASK) |
+    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
+    RX_FIFO_PAUSE_THRESH_HI_MASK));
+ }
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
+ CSR_WRITE_4(sc, ALC_SERDES_LOCK,
+    CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
+    SERDES_PHY_CLK_SLOWDOWN);
 
  /* Disable RSS until I understand L1C/L2C's RSS logic. */
  CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
@@ -2036,15 +2285,9 @@ alc_init(struct ifnet *ifp)
     RXQ_CFG_RD_BURST_MASK;
  reg |= RXQ_CFG_RSS_MODE_DIS;
  if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
- reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
+ reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
  CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
 
- /* Configure Rx DMAW request thresold. */
- CSR_WRITE_4(sc, ALC_RD_DMA_CFG,
-    ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) &
-    RD_DMA_CFG_THRESH_MASK) |
-    ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) &
-    RD_DMA_CFG_TIMER_MASK));
  /* Configure DMA parameters. */
  reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
  reg |= sc->alc_rcb;
@@ -2070,7 +2313,7 @@ alc_init(struct ifnet *ifp)
  *  - Enable CRC generation.
  *  Actual reconfiguration of MAC for resolved speed/duplex
  *  is followed after detection of link establishment.
- *  AR8131/AR8132 always does checksum computation regardless
+ *  AR813x/AR815x always does checksum computation regardless
  *  of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
  *  have bug in protocol field in Rx return structure so
  *  these controllers can't handle fragmented frames. Disable
@@ -2080,6 +2323,10 @@ alc_init(struct ifnet *ifp)
  reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
     ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
     MAC_CFG_PREAMBLE_MASK);
+ if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
+    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
+ reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
  if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
  reg |= MAC_CFG_SPEED_10_100;
  else
Index: sys/dev/pci/if_alcreg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_alcreg.h,v
retrieving revision 1.1
diff -u -p -r1.1 if_alcreg.h
--- sys/dev/pci/if_alcreg.h 8 Aug 2009 09:31:13 -0000 1.1
+++ sys/dev/pci/if_alcreg.h 1 May 2011 18:55:25 -0000
@@ -31,7 +31,10 @@
 #ifndef _IF_ALCREG_H
 #define _IF_ALCREG_H
 
-#define ALC_PCIR_BAR 0x10
+#define ALC_PCIR_BAR 0x10
+
+#define ATHEROS_AR8152_B_V10 0xC0
+#define ATHEROS_AR8152_B_V11 0xC1
 
 /* 0x0000 - 0x02FF : PCIe configuration space */
 
@@ -56,6 +59,12 @@
 #define ALC_PCIE_PHYMISC 0x1000
 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
 
+#define ALC_PCIE_PHYMISC2 0x1004
+#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
+#define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
+#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
+#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
+
 #define ALC_TWSI_DEBUG 0x1108
 #define TWSI_DEBUG_DEV_EXIST 0x20000000
 
@@ -88,7 +97,9 @@
 #define PM_CFG_PCIE_RECV 0x00008000
 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
-#define PM_CFG_LCKDET_TIMER_MASK 0x3F000000
+#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
+#define PM_CFG_EN_BUFS_RX_L0S 0x10000000
+#define PM_CFG_SA_DLY_ENB 0x20000000
 #define PM_CFG_MAC_ASPM_CHK 0x40000000
 #define PM_CFG_HOTRST 0x80000000
 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8
@@ -96,10 +107,20 @@
 #define PM_CFG_PM_REQ_TIMER_SHIFT 20
 #define PM_CFG_LCKDET_TIMER_SHIFT 24
 
+#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
+#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1
+#define PM_CFG_LCKDET_TIMER_DEFAULT 12
+#define PM_CFG_PM_REQ_TIMER_DEFAULT 12
+
+#define ALC_LTSSM_ID_CFG 0x12FC
+#define LTSSM_ID_WRO_ENB 0x00001000
+
 #define ALC_MASTER_CFG 0x1400
 #define MASTER_RESET 0x00000001
+#define MASTER_TEST_MODE_MASK 0x0000000C
 #define MASTER_BERT_START 0x00000010
-#define MASTER_TEST_MODE_MASK 0x000000C0
+#define MASTER_OOB_DIS_OFF 0x00000040
+#define MASTER_SA_TIMER_ENB 0x00000080
 #define MASTER_MTIMER_ENB 0x00000100
 #define MASTER_MANUAL_INTR_ENB 0x00000200
 #define MASTER_IM_TX_TIMER_ENB 0x00000400
@@ -114,7 +135,7 @@
 #define MASTER_CHIP_REV_SHIFT 16
 #define MASTER_CHIP_ID_SHIFT 24
 
-/* Number of ticks per usec for AR8131/AR8132. */
+/* Number of ticks per usec for AR813x/AR815x. */
 #define ALC_TICK_USECS 2
 #define ALC_USECS(x) ((x) / ALC_TICK_USECS)
 
@@ -136,7 +157,7 @@
  * alc(4) does not rely on Tx completion interrupts, so set it
  * somewhat large value to reduce Tx completion interrupts.
  */
-#define ALC_IM_TX_TIMER_DEFAULT 50000 /* 50ms */
+#define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */
 
 #define ALC_GPHY_CFG 0x140C /* 16bits */
 #define GPHY_CFG_EXT_RESET 0x0001
@@ -212,6 +233,8 @@
 #define ALC_SERDES_LOCK 0x1424
 #define SERDES_LOCK_DET 0x00000001
 #define SERDES_LOCK_DET_ENB 0x00000002
+#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
+#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
 
 #define ALC_MAC_CFG 0x1480
 #define MAC_CFG_TX_ENB 0x00000001
@@ -241,6 +264,8 @@
 #define MAC_CFG_BCAST 0x04000000
 #define MAC_CFG_DBG 0x08000000
 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
+#define MAC_CFG_HASH_ALG_CRC32 0x20000000
+#define MAC_CFG_SPEED_MODE_SW 0x40000000
 #define MAC_CFG_PREAMBLE_SHIFT 10
 #define MAC_CFG_PREAMBLE_DEFAULT 7
 
@@ -683,11 +708,19 @@
 #define HDS_CFG_BACKFILLSIZE_SHIFT 8
 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20
 
-/* AR8131/AR8132 registers for MAC statistics */
+/* AR813x/AR815x registers for MAC statistics */
 #define ALC_RX_MIB_BASE 0x1700
 
 #define ALC_TX_MIB_BASE 0x1760
 
+#define ALC_CLK_GATING_CFG 0x1814
+#define CLK_GATING_DMAW_ENB 0x0001
+#define CLK_GATING_DMAR_ENB 0x0002
+#define CLK_GATING_TXQ_ENB 0x0004
+#define CLK_GATING_RXQ_ENB 0x0008
+#define CLK_GATING_TXMAC_ENB 0x0010
+#define CLK_GATING_RXMAC_ENB 0x0020
+
 #define ALC_DEBUG_DATA0 0x1900
 
 #define ALC_DEBUG_DATA1 0x1904
@@ -1112,6 +1145,7 @@ struct alc_softc {
  bus_dma_tag_t sc_dmat;
  pci_chipset_tag_t sc_pct;
  pcitag_t sc_pcitag;
+ pci_vendor_id_t sc_product;
 
  void *sc_irq_handle;
 
@@ -1120,19 +1154,23 @@ struct alc_softc {
  int alc_chip_rev;
  int alc_phyaddr;
  uint8_t alc_eaddr[ETHER_ADDR_LEN];
+ uint32_t alc_max_framelen;
  uint32_t alc_dma_rd_burst;
  uint32_t alc_dma_wr_burst;
  uint32_t alc_rcb;
+ int alc_expcap;
  int alc_flags;
 #define ALC_FLAG_PCIE 0x0001
 #define ALC_FLAG_PCIX 0x0002
-#define ALC_FLAG_MSI 0x0004
-#define ALC_FLAG_MSIX 0x0008
+#define ALC_FLAG_PM 0x0010
 #define ALC_FLAG_FASTETHER 0x0020
 #define ALC_FLAG_JUMBO 0x0040
 #define ALC_FLAG_ASPM_MON 0x0080
 #define ALC_FLAG_CMB_BUG 0x0100
 #define ALC_FLAG_SMB_BUG 0x0200
+#define ALC_FLAG_L0S 0x0400
+#define ALC_FLAG_L1S 0x0800
+#define ALC_FLAG_APS 0x1000
 #define ALC_FLAG_DETACH 0x4000
 #define ALC_FLAG_LINK 0x8000

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Re: alc(4) support for Atheros AR815x

Stuart Henderson
Since nobody with a working PCI_PRODUCT_ATTANSIC_L2C seems interested,
and the devices newly added in this diff are showing up more often
in submitted dmesg than the L2C version matched by the current driver,
I intend to commit this tomorrow unless there are objections.


On 2011/05/16 11:16, Stuart Henderson wrote:

> So far, only had reports from L1C and the new devices (which is
> not the point of sending out this sort of diff). This is a fairly
> large diff and changes behaviour for existing devices.
>
> Has anyone with a currently-working L2C tested this to make sure
> it doesn't break their nic?
>
>
> On 2011/05/01 20:10, Stuart Henderson wrote:
> > On 2011/05/01 18:35, Edd Barrett wrote:
> > > I have acquired a netboot (packard bell dot s), which I think uses this NIC. Is
> > > there an updated diff?
> >
> > Yes I just took the 2 minutes it took to apply it and fix
> > the minor conflicts and linewrapping issue with the diff.
> > Untested beyond "it builds".
> >
> > Test reports and dmesg lines from existing working alc(4) L1C and
> > L2C wanted. If it makes new chips work that's a bonus, but the
> > important thing is making sure it doesn't break something that
> > already works.
> >
> > Doesn't seem any point disabling interrupts in the ISR though.
> > I haven't touched that in this diff but that should probably be
> > done too.
>
> Index: share/man/man4/alc.4
> ===================================================================
> RCS file: /cvs/src/share/man/man4/alc.4,v
> retrieving revision 1.2
> diff -u -p -r1.2 alc.4
> --- share/man/man4/alc.4 8 Aug 2009 14:12:41 -0000 1.2
> +++ share/man/man4/alc.4 1 May 2011 18:55:25 -0000
> @@ -19,7 +19,7 @@
>  .Os
>  .Sh NAME
>  .Nm alc
> -.Nd Atheros AR8131/AR8132 10/100/Gigabit Ethernet device
> +.Nd Atheros AR813x/AR815x 10/100/Gigabit Ethernet device
>  .Sh SYNOPSIS
>  .Cd "alc* at pci?"
>  .Cd "atphy* at mii?"
> @@ -27,8 +27,7 @@
>  The
>  .Nm
>  driver provides support for Ethernet interfaces based on the
> -Atheros AR8131/AR8132 Ethernet chipset, also known as
> -the Attansic L1C/L2C respectively.
> +Atheros AR813x/AR815x Ethernet chipset.
>  .Pp
>  The
>  .Nm
> Index: sys/arch/amd64/conf/GENERIC
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
> retrieving revision 1.316
> diff -u -p -r1.316 GENERIC
> --- sys/arch/amd64/conf/GENERIC 10 Apr 2011 20:27:02 -0000 1.316
> +++ sys/arch/amd64/conf/GENERIC 1 May 2011 18:55:25 -0000
> @@ -472,7 +472,7 @@ bce* at pci? # Broadcom BCM4401
>  vic* at pci? # VMware VMXnet virtual interface
>  et* at pci? # Agere/LSI ET1310
>  age* at pci? # Attansic L1 Ethernet
> -alc* at pci? # Attansic L1C/L2C Ethernet
> +alc* at pci? # Attansic L1C/L1D/L2C Ethernet
>  ale* at pci? # Attansic L1E Ethernet
>  lii* at pci? # Attansic L2 Ethernet
>  jme* at pci? # JMicron JMC250/JMC260 Ethernet
> Index: sys/arch/amd64/conf/RAMDISK_CD
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
> retrieving revision 1.116
> diff -u -p -r1.116 RAMDISK_CD
> --- sys/arch/amd64/conf/RAMDISK_CD 3 Apr 2011 12:32:05 -0000 1.116
> +++ sys/arch/amd64/conf/RAMDISK_CD 1 May 2011 18:55:25 -0000
> @@ -291,7 +291,7 @@ bce* at pci? # Broadcom BCM4401
>  vic* at pci? # VMware VMXnet virtual interface
>  et* at pci? # Agere/LSI ET1310
>  age* at pci? # Attansic L1 Ethernet
> -alc* at pci? # Attansic L1C/L2C Ethernet
> +alc* at pci? # Attansic L1C/L1D/L2C Ethernet
>  ale* at pci? # Attansic L1E Ethernet
>  lii* at pci? # Attansic L2 Ethernet
>  jme* at pci? # JMicron JMC250/JMC260 Ethernet
> Index: sys/arch/i386/conf/GENERIC
> ===================================================================
> RCS file: /cvs/src/sys/arch/i386/conf/GENERIC,v
> retrieving revision 1.713
> diff -u -p -r1.713 GENERIC
> --- sys/arch/i386/conf/GENERIC 10 Apr 2011 20:27:02 -0000 1.713
> +++ sys/arch/i386/conf/GENERIC 1 May 2011 18:55:25 -0000
> @@ -632,7 +632,7 @@ gem* at pci? # Sun 'gem' ethernet
>  vic* at pci? # VMware VMXnet virtual interface
>  et* at pci? # Agere/LSI ET1310
>  age* at pci? # Attansic L1 Ethernet
> -alc* at pci? # Attansic L1C/L2C Ethernet
> +alc* at pci? # Attansic L1C/L1D/L2C Ethernet
>  ale* at pci? # Attansic L1E Ethernet
>  lii* at pci? # Attansic L2 Ethernet
>  jme* at pci? # JMicron JMC250/JMC260 Ethernet
> Index: sys/arch/i386/conf/RAMDISK_CD
> ===================================================================
> RCS file: /cvs/src/sys/arch/i386/conf/RAMDISK_CD,v
> retrieving revision 1.185
> diff -u -p -r1.185 RAMDISK_CD
> --- sys/arch/i386/conf/RAMDISK_CD 3 Apr 2011 12:32:05 -0000 1.185
> +++ sys/arch/i386/conf/RAMDISK_CD 1 May 2011 18:55:25 -0000
> @@ -372,7 +372,7 @@ xge* at pci? # Neterion Xframe-I/II 1
>  vic* at pci? # VMware VMXnet virtual interface
>  et* at pci? # Agere/LSI ET1310
>  age* at pci? # Attansic L1 Ethernet
> -alc* at pci? # Attansic L1C/L2C Ethernet
> +alc* at pci? # Attansic L1C/L1D/L2C Ethernet
>  ale* at pci? # Attansic L1E Ethernet
>  lii* at pci? # Attansic L2 Ethernet
>  jme* at pci? # JMicron JMC250/JMC260 Ethernet
> Index: sys/dev/pci/files.pci
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/files.pci,v
> retrieving revision 1.278
> diff -u -p -r1.278 files.pci
> --- sys/dev/pci/files.pci 10 Apr 2011 20:27:02 -0000 1.278
> +++ sys/dev/pci/files.pci 1 May 2011 18:55:25 -0000
> @@ -643,7 +643,7 @@ device age: ether, ifnet, mii, ifmedia,
>  attach age at pci
>  file dev/pci/if_age.c age
>  
> -# Attansic/Atheros L1C/L2C Gigabit Ethernet
> +# Attansic/Atheros L1C/L1D/L2C Gigabit Ethernet
>  device alc: ether, ifnet, mii, ifmedia, mii_phy
>  attach alc at pci
>  file dev/pci/if_alc.c alc
> Index: sys/dev/pci/if_alc.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/if_alc.c,v
> retrieving revision 1.11
> diff -u -p -r1.11 if_alc.c
> --- sys/dev/pci/if_alc.c 5 Apr 2011 18:01:21 -0000 1.11
> +++ sys/dev/pci/if_alc.c 1 May 2011 18:55:25 -0000
> @@ -88,7 +88,7 @@ void alc_watchdog(struct ifnet *);
>  int alc_mediachange(struct ifnet *);
>  void alc_mediastatus(struct ifnet *, struct ifmediareq *);
>  
> -void alc_aspm(struct alc_softc *);
> +void alc_aspm(struct alc_softc *, int);
>  void alc_disable_l0s_l1(struct alc_softc *);
>  int alc_dma_alloc(struct alc_softc *);
>  void alc_dma_free(struct alc_softc *);
> @@ -109,7 +109,7 @@ void alc_phy_down(struct alc_softc *);
>  void alc_phy_reset(struct alc_softc *);
>  void alc_reset(struct alc_softc *);
>  void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
> -int alc_rxintr(struct alc_softc *);
> +void alc_rxintr(struct alc_softc *);
>  void alc_iff(struct alc_softc *);
>  void alc_rxvlan(struct alc_softc *);
>  void alc_start_queue(struct alc_softc *);
> @@ -125,7 +125,11 @@ uint32_t alc_dma_burst[] = { 128, 256, 5
>  
>  const struct pci_matchid alc_devices[] = {
>   { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C },
> - { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }
> + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C },
> + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D },
> + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 },
> + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 },
> + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 }
>  };
>  
>  struct cfattach alc_ca = {
> @@ -236,8 +240,8 @@ alc_miibus_statchg(struct device *dev)
>   reg = CSR_READ_4(sc, ALC_MAC_CFG);
>   reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
>   CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
> + alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active));
>   }
> - alc_aspm(sc);
>  }
>  
>  void
> @@ -280,20 +284,53 @@ void
>  alc_get_macaddr(struct alc_softc *sc)
>  {
>   uint32_t ea[2], opt;
> - int i;
> + uint16_t val;
> + int eeprom, i;
>  
> + eeprom = 0;
>   opt = CSR_READ_4(sc, ALC_OPT_CFG);
> - if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
> + if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
> +    (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
>   /*
>   * EEPROM found, let TWSI reload EEPROM configuration.
>   * This will set ethernet address of controller.
>   */
> - if ((opt & OPT_CFG_CLK_ENB) == 0) {
> - opt |= OPT_CFG_CLK_ENB;
> - CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
> - CSR_READ_4(sc, ALC_OPT_CFG);
> - DELAY(1000);
> + eeprom++;
> + switch (sc->sc_product) {
> + case PCI_PRODUCT_ATTANSIC_L1C:
> + case PCI_PRODUCT_ATTANSIC_L2C:
> + if ((opt & OPT_CFG_CLK_ENB) == 0) {
> + opt |= OPT_CFG_CLK_ENB;
> + CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
> + CSR_READ_4(sc, ALC_OPT_CFG);
> + DELAY(1000);
> + }
> + break;
> + case PCI_PRODUCT_ATTANSIC_L1D:
> + case PCI_PRODUCT_ATTANSIC_L1D_1:
> + case PCI_PRODUCT_ATTANSIC_L2C_1:
> + case PCI_PRODUCT_ATTANSIC_L2C_2:
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_ADDR, 0x00);
> + val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA, val & 0xFF7F);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_ADDR, 0x3B);
> + val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA, val | 0x0008);
> + DELAY(20);
> + break;
>   }
> +
> + CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
> +    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
> + CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
> + CSR_READ_4(sc, ALC_WOL_CFG);
> +
>   CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
>      TWSI_CFG_SW_LD_START);
>   for (i = 100; i > 0; i--) {
> @@ -309,11 +346,36 @@ alc_get_macaddr(struct alc_softc *sc)
>   if (alcdebug)
>   printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname);
>   }
> - if ((opt & OPT_CFG_CLK_ENB) != 0) {
> - opt &= ~OPT_CFG_CLK_ENB;
> - CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
> - CSR_READ_4(sc, ALC_OPT_CFG);
> - DELAY(1000);
> + if (eeprom != 0) {
> + switch (sc->sc_product) {
> + case PCI_PRODUCT_ATTANSIC_L1C:
> + case PCI_PRODUCT_ATTANSIC_L2C:
> + if ((opt & OPT_CFG_CLK_ENB) != 0) {
> + opt &= ~OPT_CFG_CLK_ENB;
> + CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
> + CSR_READ_4(sc, ALC_OPT_CFG);
> + DELAY(1000);
> + }
> + break;
> + case PCI_PRODUCT_ATTANSIC_L1D:
> + case PCI_PRODUCT_ATTANSIC_L1D_1:
> + case PCI_PRODUCT_ATTANSIC_L2C_1:
> + case PCI_PRODUCT_ATTANSIC_L2C_2:
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_ADDR, 0x00);
> + val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA, val | 0x0080);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_ADDR, 0x3B);
> + val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA, val & 0xFFF7);
> + DELAY(20);
> + break;
> + }
>   }
>  
>   ea[0] = CSR_READ_4(sc, ALC_PAR0);
> @@ -358,6 +420,43 @@ alc_phy_reset(struct alc_softc *sc)
>   CSR_READ_2(sc, ALC_GPHY_CFG);
>   DELAY(10 * 1000);
>  
> + /* DSP fixup, Vendor magic. */
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_ADDR, 0x000A);
> + data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA, data & 0xDFFF);
> + }
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_ADDR, 0x003B);
> + data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA, data & 0xFFF7);
> + DELAY(20 * 1000);
> + }
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) {
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_ADDR, 0x0029);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA, 0x929D);
> + }
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_ADDR, 0x0029);
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    ALC_MII_DBG_DATA, 0xB6DD);
> + }
> +
>   /* Load DSP codes, vendor magic. */
>   data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
>      ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
> @@ -406,35 +505,114 @@ alc_phy_reset(struct alc_softc *sc)
>  void
>  alc_phy_down(struct alc_softc *sc)
>  {
> -
> - /* Force PHY down. */
> - CSR_WRITE_2(sc, ALC_GPHY_CFG,
> -    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
> -    GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW);
> - DELAY(1000);
> + switch (sc->sc_product) {
> + case PCI_PRODUCT_ATTANSIC_L1D:
> + case PCI_PRODUCT_ATTANSIC_L1D_1:
> + /*
> + * GPHY power down caused more problems on AR8151 v2.0.
> + * When driver is reloaded after GPHY power down,
> + * accesses to PHY/MAC registers hung the system. Only
> + * cold boot recovered from it.  I'm not sure whether
> + * AR8151 v1.0 also requires this one though.  I don't
> + * have AR8151 v1.0 controller in hand.
> + * The only option left is to isolate the PHY and
> + * initiates power down the PHY which in turn saves
> + * more power when driver is unloaded.
> + */
> + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
> +    MII_BMCR, BMCR_ISO | BMCR_PDOWN);
> + break;
> + default:
> + /* Force PHY down. */
> + CSR_WRITE_2(sc, ALC_GPHY_CFG,
> +    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
> +    GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
> +    GPHY_CFG_PWDOWN_HW);
> + DELAY(1000);
> + break;
> + }
>  }
>  
>  void
> -alc_aspm(struct alc_softc *sc)
> +alc_aspm(struct alc_softc *sc, int media)
>  {
>   uint32_t pmcfg;
> + uint16_t linkcfg;
>  
>   pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
> + if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
> +    (ALC_FLAG_APS | ALC_FLAG_PCIE))
> + linkcfg = CSR_READ_2(sc, sc->alc_expcap +
> +    PCI_PCIE_LCSR);
> + else
> + linkcfg = 0;
>   pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
> - pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB;
> - pmcfg |= PM_CFG_SERDES_L1_ENB;
> - pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
> + pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
>   pmcfg |= PM_CFG_MAC_ASPM_CHK;
> + pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
> + pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
> +
> + if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
> + /* Disable extended sync except AR8152 B v1.0 */
> + linkcfg &= ~0x80;
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
> +    sc->alc_rev == ATHEROS_AR8152_B_V10)
> + linkcfg |= 0x80;
> + CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR,
> +    linkcfg);
> + pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
> +    PM_CFG_HOTRST);
> + pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
> +    PM_CFG_L1_ENTRY_TIMER_SHIFT);
> + pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
> + pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
> +    PM_CFG_PM_REQ_TIMER_SHIFT);
> + pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
> + }
> +
>   if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
> - pmcfg |= PM_CFG_SERDES_PLL_L1_ENB;
> - pmcfg &= ~PM_CFG_CLK_SWH_L1;
> - pmcfg &= ~PM_CFG_ASPM_L1_ENB;
> - pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
> + if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
> + pmcfg |= PM_CFG_ASPM_L0S_ENB;
> + if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
> + pmcfg |= PM_CFG_ASPM_L1_ENB;
> + if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
> + pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
> + pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
> +    PM_CFG_SERDES_PLL_L1_ENB |
> +    PM_CFG_SERDES_BUDS_RX_L1_ENB);
> + pmcfg |= PM_CFG_CLK_SWH_L1;
> + if (media == IFM_100_TX || media == IFM_1000_T) {
> + pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
> + switch (sc->sc_product) {
> + case PCI_PRODUCT_ATTANSIC_L2C_1:
> + pmcfg |= (7 <<
> +    PM_CFG_L1_ENTRY_TIMER_SHIFT);
> + break;
> + case PCI_PRODUCT_ATTANSIC_L1D_1:
> + case PCI_PRODUCT_ATTANSIC_L2C_2:
> + pmcfg |= (4 <<
> +    PM_CFG_L1_ENTRY_TIMER_SHIFT);
> + break;
> + default:
> + pmcfg |= (15 <<
> +    PM_CFG_L1_ENTRY_TIMER_SHIFT);
> + break;
> + }
> + }
> + } else {
> + pmcfg |= PM_CFG_SERDES_L1_ENB |
> +    PM_CFG_SERDES_PLL_L1_ENB |
> +    PM_CFG_SERDES_BUDS_RX_L1_ENB;
> + pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
> +    PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
> + }
>   } else {
> - pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB;
> + pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
> +    PM_CFG_SERDES_PLL_L1_ENB);
>   pmcfg |= PM_CFG_CLK_SWH_L1;
> - pmcfg &= ~PM_CFG_ASPM_L1_ENB;
> - pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
> + if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
> + pmcfg |= PM_CFG_ASPM_L1_ENB;
>   }
>   CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
>  }
> @@ -450,9 +628,9 @@ alc_attach(struct device *parent, struct
>   const char *intrstr;
>   struct ifnet *ifp;
>   pcireg_t memtype;
> - char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" };
> + char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
>   uint16_t burst;
> - int base, mii_flags, state, error = 0;
> + int base, state, error = 0;
>   uint32_t cap, ctl, val;
>  
>   /*
> @@ -499,6 +677,7 @@ alc_attach(struct device *parent, struct
>   if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
>      &base, NULL)) {
>   sc->alc_flags |= ALC_FLAG_PCIE;
> + sc->alc_expcap = base;
>   burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
>      base + PCI_PCIE_DCSR) >> 16;
>   sc->alc_dma_rd_burst = (burst & 0x7000) >> 12;
> @@ -515,6 +694,20 @@ alc_attach(struct device *parent, struct
>   val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
>   val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
>   CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
> + CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
> +    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
> + CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
> +    CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
> +    PCIE_PHYMISC_FORCE_RCV_DET);
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
> +    sc->alc_rev == ATHEROS_AR8152_B_V10) {
> + val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
> + val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
> +    PCIE_PHYMISC2_SERDES_TH_MASK);
> + val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
> + val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
> + CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
> + }
>   /* Disable ASPM L0S and L1. */
>   cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
>      base + PCI_PCIE_LCAP) >> 16;
> @@ -528,13 +721,16 @@ alc_attach(struct device *parent, struct
>      sc->sc_dev.dv_xname,
>      sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
>   state = ctl & 0x03;
> + if (state & 0x01)
> + sc->alc_flags |= ALC_FLAG_L0S;
> + if (state & 0x02)
> + sc->alc_flags |= ALC_FLAG_L1S;
>   if (alcdebug)
>   printf("%s: ASPM %s %s\n",
>      sc->sc_dev.dv_xname,
>      aspm_state[state],
>      state == 0 ? "disabled" : "enabled");
> - if (state != 0)
> - alc_disable_l0s_l1(sc);
> + alc_disable_l0s_l1(sc);
>   }
>   }
>  
> @@ -551,12 +747,39 @@ alc_attach(struct device *parent, struct
>   * used in AR8132 can't establish gigabit link even if it
>   * shows the same PHY model/revision number of AR8131.
>   */
> - if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_L2C)
> - sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO;
> - else
> - sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON;
> + sc->sc_product = PCI_PRODUCT(pa->pa_id);
> + switch (sc->sc_product) {
> + case PCI_PRODUCT_ATTANSIC_L2C_1:
> + case PCI_PRODUCT_ATTANSIC_L2C_2:
> + sc->alc_flags |= ALC_FLAG_APS;
> + /* FALLTHROUGH */
> + case PCI_PRODUCT_ATTANSIC_L2C:
> + sc->alc_flags |= ALC_FLAG_FASTETHER;
> + break;
> + case PCI_PRODUCT_ATTANSIC_L1D:
> + case PCI_PRODUCT_ATTANSIC_L1D_1:
> + sc->alc_flags |= ALC_FLAG_APS;
> + /* FALLTHROUGH */
> + default:
> + break;
> + }
> + sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO;
> +
> + switch (sc->sc_product) {
> + case PCI_PRODUCT_ATTANSIC_L1C:
> + case PCI_PRODUCT_ATTANSIC_L2C:
> + sc->alc_max_framelen = 9 * 1024;
> + break;
> + case PCI_PRODUCT_ATTANSIC_L1D:
> + case PCI_PRODUCT_ATTANSIC_L1D_1:
> + case PCI_PRODUCT_ATTANSIC_L2C_1:
> + case PCI_PRODUCT_ATTANSIC_L2C_2:
> + sc->alc_max_framelen = 6 * 1024;
> + break;
> + }
> +
>   /*
> - * It seems that AR8131/AR8132 has silicon bug for SMB. In
> + * It seems that AR813x/AR815x has silicon bug for SMB. In
>   * addition, Atheros said that enabling SMB wouldn't improve
>   * performance. However I think it's bad to access lots of
>   * registers to extract MAC statistics.
> @@ -619,11 +842,8 @@ alc_attach(struct device *parent, struct
>  
>   ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange,
>      alc_mediastatus);
> - mii_flags = 0;
> - if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0)
> - mii_flags |= MIIF_DOPAUSE;
>   mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY,
> - MII_OFFSET_ANY, mii_flags);
> + MII_OFFSET_ANY, MIIF_DOPAUSE);
>  
>   if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) {
>   printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
> @@ -1136,16 +1356,15 @@ alc_start(struct ifnet *ifp)
>  {
>   struct alc_softc *sc = ifp->if_softc;
>   struct mbuf *m_head;
> - int enq;
> -
> - if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
> - return;
> + int enq = 0;
>  
>   /* Reclaim transmitted frames. */
>   if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
>   alc_txeof(sc);
>  
> - enq = 0;
> + if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
> + return;
> +
>   for (;;) {
>   IFQ_DEQUEUE(&ifp->if_snd, m_head);
>   if (m_head == NULL)
> @@ -1162,7 +1381,7 @@ alc_start(struct ifnet *ifp)
>   ifp->if_flags |= IFF_OACTIVE;
>   break;
>   }
> - enq = 1;
> + enq++;
>  
>  #if NBPFILTER > 0
>   /*
> @@ -1174,7 +1393,7 @@ alc_start(struct ifnet *ifp)
>  #endif
>   }
>  
> - if (enq) {
> + if (enq > 0) {
>   /* Sync descriptors. */
>   bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
>      sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
> @@ -1274,6 +1493,10 @@ alc_mac_config(struct alc_softc *sc)
>   reg = CSR_READ_4(sc, ALC_MAC_CFG);
>   reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
>      MAC_CFG_SPEED_MASK);
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
> + reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
>   /* Reprogram MAC with resolved speed/duplex. */
>   switch (IFM_SUBTYPE(mii->mii_media_active)) {
>   case IFM_10_T:
> @@ -1451,24 +1674,25 @@ alc_intr(void *arg)
>   struct alc_softc *sc = arg;
>   struct ifnet *ifp = &sc->sc_arpcom.ac_if;
>   uint32_t status;
> + int claimed = 0;
>  
>   status = CSR_READ_4(sc, ALC_INTR_STATUS);
>   if ((status & ALC_INTRS) == 0)
>   return (0);
>  
> + /* Disable interrupts. */
> + CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
> +
> + status = CSR_READ_4(sc, ALC_INTR_STATUS);
> + if ((status & ALC_INTRS) == 0)
> + goto back;
> +
>   /* Acknowledge and disable interrupts. */
>   CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
>  
>   if (ifp->if_flags & IFF_RUNNING) {
> - if (status & INTR_RX_PKT) {
> - int error;
> -
> - error = alc_rxintr(sc);
> - if (error) {
> - alc_init(ifp);
> - return (0);
> - }
> - }
> + if (status & INTR_RX_PKT)
> + alc_rxintr(sc);
>  
>   if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
>      INTR_TXQ_TO_RST)) {
> @@ -1485,14 +1709,17 @@ alc_intr(void *arg)
>   return (0);
>   }
>  
> - alc_txeof(sc);
> - if (!IFQ_IS_EMPTY(&ifp->if_snd))
> + if (status & INTR_TX_PKT) {
> + alc_txeof(sc);
> +    if (!IFQ_IS_EMPTY(&ifp->if_snd))
>   alc_start(ifp);
> + }
>   }
> -
> + claimed = 1;
> +back:
>   /* Re-enable interrupts. */
>   CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
> - return (1);
> + return (claimed);
>  }
>  
>  void
> @@ -1507,7 +1734,7 @@ alc_txeof(struct alc_softc *sc)
>   return;
>   bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
>      sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
> -    BUS_DMASYNC_POSTREAD);
> +    BUS_DMASYNC_POSTWRITE);
>   if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
>   bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
>      sc->alc_cdata.alc_cmb_map->dm_mapsize,
> @@ -1591,7 +1818,7 @@ alc_newbuf(struct alc_softc *sc, struct
>   return (0);
>  }
>  
> -int
> +void
>  alc_rxintr(struct alc_softc *sc)
>  {
>   struct ifnet *ifp = &sc->sc_arpcom.ac_if;
> @@ -1615,7 +1842,7 @@ alc_rxintr(struct alc_softc *sc)
>   if (alcdebug)
>   printf("%s: unexpected segment count -- "
>      "resetting\n", sc->sc_dev.dv_xname);
> - return (EIO);
> + break;
>   }
>   alc_rxeof(sc, rrd);
>   /* Clear Rx return status. */
> @@ -1653,8 +1880,6 @@ alc_rxintr(struct alc_softc *sc)
>   CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
>      sc->alc_cdata.alc_rx_cons);
>   }
> -
> - return (0);
>  }
>  
>  /* Receive a frame. */
> @@ -1686,9 +1911,8 @@ alc_rxeof(struct alc_softc *sc, struct r
>   *  Force network stack compute checksum for
>   *  errored frames.
>   */
> - status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
> - if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC |
> -    RRD_ERR_RUNT) != 0)
> + if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN |
> +    RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0)
>   return;
>   }
>  
> @@ -1801,7 +2025,9 @@ alc_reset(struct alc_softc *sc)
>   uint32_t reg;
>   int i;
>  
> - CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET);
> + reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF;
> + reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
> + CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
>   for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
>   DELAY(10);
>   if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
> @@ -1852,6 +2078,9 @@ alc_init(struct ifnet *ifp)
>   alc_init_cmb(sc);
>   alc_init_smb(sc);
>  
> + /* Enable all clocks. */
> + CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
> +
>   /* Reprogram the station address. */
>   bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN);
>   CSR_WRITE_4(sc, ALC_PAR0,
> @@ -1913,6 +2142,18 @@ alc_init(struct ifnet *ifp)
>   CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
>   CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
>  
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
> + /* Reconfigure SRAM - Vendor magic. */
> + CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
> + CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
> + CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
> + CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
> + CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
> + CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
> + CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
> + CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
> + }
> +
>   /* Tell hardware that we're ready to load DMA blocks. */
>   CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
>  
> @@ -1922,14 +2163,11 @@ alc_init(struct ifnet *ifp)
>   reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
>   reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
>   CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
> - reg = CSR_READ_4(sc, ALC_MASTER_CFG);
> - reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
>   /*
>   * We don't want to automatic interrupt clear as task queue
>   * for the interrupt should know interrupt status.
>   */
> - reg &= ~MASTER_INTR_RD_CLR;
> - reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
> + reg = MASTER_SA_TIMER_ENB;
>   if (ALC_USECS(sc->alc_int_rx_mod) != 0)
>   reg |= MASTER_IM_RX_TIMER_ENB;
>   if (ALC_USECS(sc->alc_int_tx_mod) != 0)
> @@ -1970,7 +2208,7 @@ alc_init(struct ifnet *ifp)
>   * Be conservative in what you do, be liberal in what you
>   * accept from others - RFC 793.
>   */
> - CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN);
> + CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen);
>  
>   /* Disable header split(?) */
>   CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
> @@ -1997,11 +2235,14 @@ alc_init(struct ifnet *ifp)
>   * TSO/checksum offloading.
>   */
>   CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
> -    (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
> +    (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
>      TSO_OFFLOAD_THRESH_MASK);
>   /* Configure TxQ. */
>   reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
>      TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
> + reg >>= 1;
>   reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
>      TXQ_CFG_TD_BURST_MASK;
>   CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
> @@ -2018,14 +2259,22 @@ alc_init(struct ifnet *ifp)
>   * XON  : 80% of Rx FIFO
>   * XOFF : 30% of Rx FIFO
>   */
> - reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
> - rxf_hi = (reg * 8) / 10;
> - rxf_lo = (reg * 3)/ 10;
> - CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
> -    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
> -    RX_FIFO_PAUSE_THRESH_LO_MASK) |
> -    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
> -     RX_FIFO_PAUSE_THRESH_HI_MASK));
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) {
> + reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
> + rxf_hi = (reg * 8) / 10;
> + rxf_lo = (reg * 3) / 10;
> + CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
> +    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
> +    RX_FIFO_PAUSE_THRESH_LO_MASK) |
> +    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
> +    RX_FIFO_PAUSE_THRESH_HI_MASK));
> + }
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
> + CSR_WRITE_4(sc, ALC_SERDES_LOCK,
> +    CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
> +    SERDES_PHY_CLK_SLOWDOWN);
>  
>   /* Disable RSS until I understand L1C/L2C's RSS logic. */
>   CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
> @@ -2036,15 +2285,9 @@ alc_init(struct ifnet *ifp)
>      RXQ_CFG_RD_BURST_MASK;
>   reg |= RXQ_CFG_RSS_MODE_DIS;
>   if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
> - reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
> + reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
>   CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
>  
> - /* Configure Rx DMAW request thresold. */
> - CSR_WRITE_4(sc, ALC_RD_DMA_CFG,
> -    ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) &
> -    RD_DMA_CFG_THRESH_MASK) |
> -    ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) &
> -    RD_DMA_CFG_TIMER_MASK));
>   /* Configure DMA parameters. */
>   reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
>   reg |= sc->alc_rcb;
> @@ -2070,7 +2313,7 @@ alc_init(struct ifnet *ifp)
>   *  - Enable CRC generation.
>   *  Actual reconfiguration of MAC for resolved speed/duplex
>   *  is followed after detection of link establishment.
> - *  AR8131/AR8132 always does checksum computation regardless
> + *  AR813x/AR815x always does checksum computation regardless
>   *  of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
>   *  have bug in protocol field in Rx return structure so
>   *  these controllers can't handle fragmented frames. Disable
> @@ -2080,6 +2323,10 @@ alc_init(struct ifnet *ifp)
>   reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
>      ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
>      MAC_CFG_PREAMBLE_MASK);
> + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
> +    sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
> + reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
>   if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
>   reg |= MAC_CFG_SPEED_10_100;
>   else
> Index: sys/dev/pci/if_alcreg.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/if_alcreg.h,v
> retrieving revision 1.1
> diff -u -p -r1.1 if_alcreg.h
> --- sys/dev/pci/if_alcreg.h 8 Aug 2009 09:31:13 -0000 1.1
> +++ sys/dev/pci/if_alcreg.h 1 May 2011 18:55:25 -0000
> @@ -31,7 +31,10 @@
>  #ifndef _IF_ALCREG_H
>  #define _IF_ALCREG_H
>  
> -#define ALC_PCIR_BAR 0x10
> +#define ALC_PCIR_BAR 0x10
> +
> +#define ATHEROS_AR8152_B_V10 0xC0
> +#define ATHEROS_AR8152_B_V11 0xC1
>  
>  /* 0x0000 - 0x02FF : PCIe configuration space */
>  
> @@ -56,6 +59,12 @@
>  #define ALC_PCIE_PHYMISC 0x1000
>  #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
>  
> +#define ALC_PCIE_PHYMISC2 0x1004
> +#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
> +#define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
> +#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
> +#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
> +
>  #define ALC_TWSI_DEBUG 0x1108
>  #define TWSI_DEBUG_DEV_EXIST 0x20000000
>  
> @@ -88,7 +97,9 @@
>  #define PM_CFG_PCIE_RECV 0x00008000
>  #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
>  #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
> -#define PM_CFG_LCKDET_TIMER_MASK 0x3F000000
> +#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
> +#define PM_CFG_EN_BUFS_RX_L0S 0x10000000
> +#define PM_CFG_SA_DLY_ENB 0x20000000
>  #define PM_CFG_MAC_ASPM_CHK 0x40000000
>  #define PM_CFG_HOTRST 0x80000000
>  #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8
> @@ -96,10 +107,20 @@
>  #define PM_CFG_PM_REQ_TIMER_SHIFT 20
>  #define PM_CFG_LCKDET_TIMER_SHIFT 24
>  
> +#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
> +#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1
> +#define PM_CFG_LCKDET_TIMER_DEFAULT 12
> +#define PM_CFG_PM_REQ_TIMER_DEFAULT 12
> +
> +#define ALC_LTSSM_ID_CFG 0x12FC
> +#define LTSSM_ID_WRO_ENB 0x00001000
> +
>  #define ALC_MASTER_CFG 0x1400
>  #define MASTER_RESET 0x00000001
> +#define MASTER_TEST_MODE_MASK 0x0000000C
>  #define MASTER_BERT_START 0x00000010
> -#define MASTER_TEST_MODE_MASK 0x000000C0
> +#define MASTER_OOB_DIS_OFF 0x00000040
> +#define MASTER_SA_TIMER_ENB 0x00000080
>  #define MASTER_MTIMER_ENB 0x00000100
>  #define MASTER_MANUAL_INTR_ENB 0x00000200
>  #define MASTER_IM_TX_TIMER_ENB 0x00000400
> @@ -114,7 +135,7 @@
>  #define MASTER_CHIP_REV_SHIFT 16
>  #define MASTER_CHIP_ID_SHIFT 24
>  
> -/* Number of ticks per usec for AR8131/AR8132. */
> +/* Number of ticks per usec for AR813x/AR815x. */
>  #define ALC_TICK_USECS 2
>  #define ALC_USECS(x) ((x) / ALC_TICK_USECS)
>  
> @@ -136,7 +157,7 @@
>   * alc(4) does not rely on Tx completion interrupts, so set it
>   * somewhat large value to reduce Tx completion interrupts.
>   */
> -#define ALC_IM_TX_TIMER_DEFAULT 50000 /* 50ms */
> +#define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */
>  
>  #define ALC_GPHY_CFG 0x140C /* 16bits */
>  #define GPHY_CFG_EXT_RESET 0x0001
> @@ -212,6 +233,8 @@
>  #define ALC_SERDES_LOCK 0x1424
>  #define SERDES_LOCK_DET 0x00000001
>  #define SERDES_LOCK_DET_ENB 0x00000002
> +#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
> +#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
>  
>  #define ALC_MAC_CFG 0x1480
>  #define MAC_CFG_TX_ENB 0x00000001
> @@ -241,6 +264,8 @@
>  #define MAC_CFG_BCAST 0x04000000
>  #define MAC_CFG_DBG 0x08000000
>  #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
> +#define MAC_CFG_HASH_ALG_CRC32 0x20000000
> +#define MAC_CFG_SPEED_MODE_SW 0x40000000
>  #define MAC_CFG_PREAMBLE_SHIFT 10
>  #define MAC_CFG_PREAMBLE_DEFAULT 7
>  
> @@ -683,11 +708,19 @@
>  #define HDS_CFG_BACKFILLSIZE_SHIFT 8
>  #define HDS_CFG_MAX_HDRSIZE_SHIFT 20
>  
> -/* AR8131/AR8132 registers for MAC statistics */
> +/* AR813x/AR815x registers for MAC statistics */
>  #define ALC_RX_MIB_BASE 0x1700
>  
>  #define ALC_TX_MIB_BASE 0x1760
>  
> +#define ALC_CLK_GATING_CFG 0x1814
> +#define CLK_GATING_DMAW_ENB 0x0001
> +#define CLK_GATING_DMAR_ENB 0x0002
> +#define CLK_GATING_TXQ_ENB 0x0004
> +#define CLK_GATING_RXQ_ENB 0x0008
> +#define CLK_GATING_TXMAC_ENB 0x0010
> +#define CLK_GATING_RXMAC_ENB 0x0020
> +
>  #define ALC_DEBUG_DATA0 0x1900
>  
>  #define ALC_DEBUG_DATA1 0x1904
> @@ -1112,6 +1145,7 @@ struct alc_softc {
>   bus_dma_tag_t sc_dmat;
>   pci_chipset_tag_t sc_pct;
>   pcitag_t sc_pcitag;
> + pci_vendor_id_t sc_product;
>  
>   void *sc_irq_handle;
>  
> @@ -1120,19 +1154,23 @@ struct alc_softc {
>   int alc_chip_rev;
>   int alc_phyaddr;
>   uint8_t alc_eaddr[ETHER_ADDR_LEN];
> + uint32_t alc_max_framelen;
>   uint32_t alc_dma_rd_burst;
>   uint32_t alc_dma_wr_burst;
>   uint32_t alc_rcb;
> + int alc_expcap;
>   int alc_flags;
>  #define ALC_FLAG_PCIE 0x0001
>  #define ALC_FLAG_PCIX 0x0002
> -#define ALC_FLAG_MSI 0x0004
> -#define ALC_FLAG_MSIX 0x0008
> +#define ALC_FLAG_PM 0x0010
>  #define ALC_FLAG_FASTETHER 0x0020
>  #define ALC_FLAG_JUMBO 0x0040
>  #define ALC_FLAG_ASPM_MON 0x0080
>  #define ALC_FLAG_CMB_BUG 0x0100
>  #define ALC_FLAG_SMB_BUG 0x0200
> +#define ALC_FLAG_L0S 0x0400
> +#define ALC_FLAG_L1S 0x0800
> +#define ALC_FLAG_APS 0x1000
>  #define ALC_FLAG_DETACH 0x4000
>  #define ALC_FLAG_LINK 0x8000

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Re: alc(4) support for Atheros AR815x

matteo filippetto
In reply to this post by Stuart Henderson
2011/5/16 Stuart Henderson <[hidden email]>:
> So far, only had reports from L1C and the new devices (which is
> not the point of sending out this sort of diff). This is a fairly
> large diff and changes behaviour for existing devices.
>
> Has anyone with a currently-working L2C tested this to make sure
> it doesn't break their nic?
>

Hi,

I have a eeepc 1001pxd with "Attansic Technology L2C" working
and this patch didn't break the nic.

One problem: very slow connection....can I help?
try to make some tests?

Latest snapshot of i386.

Attached dmesg and pcidump.

Best regards.

Matteo Filippetto
Domain /dev/pci0:
 0:0:0: Intel Pineview DMI
        0x0000: Vendor ID: 8086 Product ID: a010
        0x0004: Command: 0006 Status ID: 2090
        0x0008: Class: 06 Subclass: 00 Interface: 00 Revision: 00
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR empty (00000000)
        0x0014: BAR empty (00000000)
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR empty (00000000)
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ac
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 00 Line: 00 Min Gnt: 00 Max Lat: 00
        0x00e0: Capability 0x09: Vendor Specific
 0:2:0: Intel Pineview Video
        0x0000: Vendor ID: 8086 Product ID: a011
        0x0004: Command: 0007 Status ID: 0090
        0x0008: Class: 03 Subclass: 00 Interface: 00 Revision: 00
        0x000c: BIST: 00 Header Type: 80 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR mem 32bit addr: 0xf7e00000/0x00080000
        0x0014: BAR io addr: 0x0000dc00/0x0008
        0x0018: BAR mem prefetchable 32bit addr: 0xd0000000/0x10000000
        0x001c: BAR mem 32bit addr: 0xf7d00000/0x00100000
        0x0020: BAR empty (00000000)
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ac
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 01 Line: 0f Min Gnt: 00 Max Lat: 00
        0x0090: Capability 0x05: Message Signaled Interrupts (MSI)
        0x00d0: Capability 0x01: Power Management
 0:2:1: Intel Pineview Video
        0x0000: Vendor ID: 8086 Product ID: a012
        0x0004: Command: 0007 Status ID: 0090
        0x0008: Class: 03 Subclass: 80 Interface: 00 Revision: 00
        0x000c: BIST: 00 Header Type: 80 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR mem 32bit addr: 0xf7e80000/0x00080000
        0x0014: BAR empty (00000000)
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR empty (00000000)
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ac
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 00 Line: 00 Min Gnt: 00 Max Lat: 00
        0x00d0: Capability 0x01: Power Management
 0:27:0: Intel 82801GB HD Audio
        0x0000: Vendor ID: 8086 Product ID: 27d8
        0x0004: Command: 0006 Status ID: 0010
        0x0008: Class: 04 Subclass: 03 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 08
        0x0010: BAR mem 64bit addr: 0x00000000f7cf8000/0x00004000
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR empty (00000000)
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 8442
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 01 Line: 04 Min Gnt: 00 Max Lat: 00
        0x0050: Capability 0x01: Power Management
        0x0060: Capability 0x05: Message Signaled Interrupts (MSI)
        0x0070: Capability 0x10: PCI Express
 0:28:0: Intel 82801GB PCIE
        0x0000: Vendor ID: 8086 Product ID: 27d0
        0x0004: Command: 0104 Status ID: 0010
        0x0008: Class: 06 Subclass: 04 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 81 Latency Timer: 00 Cache Line Size: 08
        0x0010: 00000000
        0x0014: 00000000
        0x0018: Primary Bus: 0 Secondary Bus: 4 Subordinate Bus: 4
                Secondary Latency Timer: 00
        0x001c: I/O Base: f0 I/O Limit: 00 Secondary Status: 2000
        0x0020: Memory Base: fff0 Memory Limit: 0000
        0x0024: Prefetch Memory Base: fff1 Prefetch Memory Limit: 0001
        0x0028: Prefetch Memory Base Upper 32 Bits: 00000000
        0x002c: Prefetch Memory Limit Upper 32 Bits: 00000000
        0x0030: I/O Base Upper 16 Bits: 0000 I/O Limit Upper 16 Bits: 0000
        0x0038: Expansion ROM Base Address: 00000000
        0x003c: Interrupt Pin: 01 Line: 0f Bridge Control: 0002
        0x0040: Capability 0x10: PCI Express
                Link Speed: 2.5 / 2.5 Gb/s Link Width: x0 / x1
        0x0080: Capability 0x05: Message Signaled Interrupts (MSI)
        0x0090: Capability 0x0d: PCI-PCI
        0x00a0: Capability 0x01: Power Management
 0:28:1: Intel 82801GB PCIE
        0x0000: Vendor ID: 8086 Product ID: 27d2
        0x0004: Command: 0106 Status ID: 0010
        0x0008: Class: 06 Subclass: 04 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 81 Latency Timer: 00 Cache Line Size: 08
        0x0010: 00000000
        0x0014: 00000000
        0x0018: Primary Bus: 0 Secondary Bus: 2 Subordinate Bus: 3
                Secondary Latency Timer: 00
        0x001c: I/O Base: f0 I/O Limit: 00 Secondary Status: 2000
        0x0020: Memory Base: f800 Memory Limit: fbf0
        0x0024: Prefetch Memory Base: f001 Prefetch Memory Limit: f6f1
        0x0028: Prefetch Memory Base Upper 32 Bits: 00000000
        0x002c: Prefetch Memory Limit Upper 32 Bits: 00000000
        0x0030: I/O Base Upper 16 Bits: 0000 I/O Limit Upper 16 Bits: 0000
        0x0038: Expansion ROM Base Address: 00000000
        0x003c: Interrupt Pin: 02 Line: 0a Bridge Control: 0002
        0x0040: Capability 0x10: PCI Express
                Link Speed: 2.5 / 2.5 Gb/s Link Width: x1 / x1
        0x0080: Capability 0x05: Message Signaled Interrupts (MSI)
        0x0090: Capability 0x0d: PCI-PCI
        0x00a0: Capability 0x01: Power Management
 0:28:3: Intel 82801GB PCIE
        0x0000: Vendor ID: 8086 Product ID: 27d6
        0x0004: Command: 0107 Status ID: 0010
        0x0008: Class: 06 Subclass: 04 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 81 Latency Timer: 00 Cache Line Size: 08
        0x0010: 00000000
        0x0014: 00000000
        0x0018: Primary Bus: 0 Secondary Bus: 1 Subordinate Bus: 1
                Secondary Latency Timer: 00
        0x001c: I/O Base: e0 I/O Limit: e0 Secondary Status: 2000
        0x0020: Memory Base: f7f0 Memory Limit: f7f0
        0x0024: Prefetch Memory Base: fff1 Prefetch Memory Limit: 0001
        0x0028: Prefetch Memory Base Upper 32 Bits: 00000000
        0x002c: Prefetch Memory Limit Upper 32 Bits: 00000000
        0x0030: I/O Base Upper 16 Bits: 0000 I/O Limit Upper 16 Bits: 0000
        0x0038: Expansion ROM Base Address: 00000000
        0x003c: Interrupt Pin: 04 Line: 0b Bridge Control: 0002
        0x0040: Capability 0x10: PCI Express
                Link Speed: 2.5 / 2.5 Gb/s Link Width: x1 / x1
        0x0080: Capability 0x05: Message Signaled Interrupts (MSI)
        0x0090: Capability 0x0d: PCI-PCI
        0x00a0: Capability 0x01: Power Management
 0:29:0: Intel 82801GB USB
        0x0000: Vendor ID: 8086 Product ID: 27c8
        0x0004: Command: 0005 Status ID: 0280
        0x0008: Class: 0c Subclass: 03 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 80 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR empty (00000000)
        0x0014: BAR empty (00000000)
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR io addr: 0x0000d400/0x0020
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ad
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 01 Line: 03 Min Gnt: 00 Max Lat: 00
 0:29:1: Intel 82801GB USB
        0x0000: Vendor ID: 8086 Product ID: 27c9
        0x0004: Command: 0005 Status ID: 0280
        0x0008: Class: 0c Subclass: 03 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR empty (00000000)
        0x0014: BAR empty (00000000)
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR io addr: 0x0000d480/0x0020
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ad
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 02 Line: 0b Min Gnt: 00 Max Lat: 00
 0:29:2: Intel 82801GB USB
        0x0000: Vendor ID: 8086 Product ID: 27ca
        0x0004: Command: 0005 Status ID: 0280
        0x0008: Class: 0c Subclass: 03 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR empty (00000000)
        0x0014: BAR empty (00000000)
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR io addr: 0x0000d800/0x0020
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ad
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 03 Line: 07 Min Gnt: 00 Max Lat: 00
 0:29:3: Intel 82801GB USB
        0x0000: Vendor ID: 8086 Product ID: 27cb
        0x0004: Command: 0005 Status ID: 0280
        0x0008: Class: 0c Subclass: 03 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR empty (00000000)
        0x0014: BAR empty (00000000)
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR io addr: 0x0000d880/0x0020
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ad
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 04 Line: 0f Min Gnt: 00 Max Lat: 00
 0:29:7: Intel 82801GB USB
        0x0000: Vendor ID: 8086 Product ID: 27cc
        0x0004: Command: 0006 Status ID: 0290
        0x0008: Class: 0c Subclass: 03 Interface: 20 Revision: 02
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR mem 32bit addr: 0xf7cf7c00/0x00000400
        0x0014: BAR empty (00000000)
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR empty (00000000)
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ad
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 01 Line: 03 Min Gnt: 00 Max Lat: 00
        0x0050: Capability 0x01: Power Management
        0x0058: Capability 0x0a: Debug Port
 0:30:0: Intel 82801BAM Hub-to-PCI
        0x0000: Vendor ID: 8086 Product ID: 2448
        0x0004: Command: 0104 Status ID: 0010
        0x0008: Class: 06 Subclass: 04 Interface: 01 Revision: e2
        0x000c: BIST: 00 Header Type: 01 Latency Timer: 00 Cache Line Size: 00
        0x0010: 00000000
        0x0014: 00000000
        0x0018: Primary Bus: 0 Secondary Bus: 5 Subordinate Bus: 5
                Secondary Latency Timer: 20
        0x001c: I/O Base: f0 I/O Limit: 00 Secondary Status: 2280
        0x0020: Memory Base: fff0 Memory Limit: 0000
        0x0024: Prefetch Memory Base: fff1 Prefetch Memory Limit: 0001
        0x0028: Prefetch Memory Base Upper 32 Bits: 00000000
        0x002c: Prefetch Memory Limit Upper 32 Bits: 00000000
        0x0030: I/O Base Upper 16 Bits: 0000 I/O Limit Upper 16 Bits: 0000
        0x0038: Expansion ROM Base Address: 00000000
        0x003c: Interrupt Pin: 00 Line: ff Bridge Control: 0002
        0x0050: Capability 0x0d: PCI-PCI
 0:31:0: Intel Tigerpoint LPC
        0x0000: Vendor ID: 8086 Product ID: 27bc
        0x0004: Command: 0007 Status ID: 0210
        0x0008: Class: 06 Subclass: 01 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 80 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR empty (00000000)
        0x0014: BAR empty (00000000)
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR empty (00000000)
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ad
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 00 Line: 00 Min Gnt: 00 Max Lat: 00
        0x00e0: Capability 0x09: Vendor Specific
 0:31:2: Intel 82801GR AHCI
        0x0000: Vendor ID: 8086 Product ID: 27c1
        0x0004: Command: 0007 Status ID: 02b0
        0x0008: Class: 01 Subclass: 06 Interface: 01 Revision: 02
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR io addr: 0x0000d080/0x0008
        0x0014: BAR io addr: 0x0000d000/0x0004
        0x0018: BAR io addr: 0x0000cc00/0x0008
        0x001c: BAR io addr: 0x0000c880/0x0004
        0x0020: BAR io addr: 0x0000c800/0x0020
        0x0024: BAR mem 32bit addr: 0xf7cf7800/0x00000400
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ad
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 02 Line: 05 Min Gnt: 00 Max Lat: 00
        0x0080: Capability 0x05: Message Signaled Interrupts (MSI)
        0x0070: Capability 0x01: Power Management
        0x00a8: Capability 0x12: SATA
 0:31:3: Intel 82801GB SMBus
        0x0000: Vendor ID: 8086 Product ID: 27da
        0x0004: Command: 0001 Status ID: 0280
        0x0008: Class: 0c Subclass: 05 Interface: 00 Revision: 02
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
        0x0010: BAR empty (00000000)
        0x0014: BAR empty (00000000)
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR io addr: 0x00000400/0x0020
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 83ad
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 02 Line: 0b Min Gnt: 00 Max Lat: 00
 1:0:0: Attansic Technology L2C
        0x0000: Vendor ID: 1969 Product ID: 2062
        0x0004: Command: 0007 Status ID: 0010
        0x0008: Class: 02 Subclass: 00 Interface: 00 Revision: c1
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 08
        0x0010: BAR mem 64bit addr: 0x00000000f7fc0000/0x00040000
        0x0018: BAR io addr: 0x0000ec00/0x0080
        0x001c: BAR empty (00000000)
        0x0020: BAR empty (00000000)
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1043 Product ID: 8468
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 01 Line: 0b Min Gnt: 00 Max Lat: 00
        0x0040: Capability 0x01: Power Management
        0x0048: Capability 0x05: Message Signaled Interrupts (MSI)
        0x0058: Capability 0x10: PCI Express
                Link Speed: 2.5 / 2.5 Gb/s Link Width: x1 / x1
        0x006c: Capability 0x03: Vital Product Data (VPD)
 2:0:0: Atheros AR9285
        0x0000: Vendor ID: 168c Product ID: 002b
        0x0004: Command: 0007 Status ID: 0010
        0x0008: Class: 02 Subclass: 80 Interface: 00 Revision: 01
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 08
        0x0010: BAR mem 64bit addr: 0x00000000fbff0000/0x00010000
        0x0018: BAR empty (00000000)
        0x001c: BAR empty (00000000)
        0x0020: BAR empty (00000000)
        0x0024: BAR empty (00000000)
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1a3b Product ID: 1089
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 01 Line: 0a Min Gnt: 00 Max Lat: 00
        0x0040: Capability 0x01: Power Management
        0x0050: Capability 0x05: Message Signaled Interrupts (MSI)
        0x0060: Capability 0x10: PCI Express
                Link Speed: 2.5 / 2.5 Gb/s Link Width: x1 / x1

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Re: alc(4) support for Atheros AR815x

matteo filippetto
> Hi,
>
> I have a eeepc 1001pxd with "Attansic Technology L2C" working
> and this patch didn't break the nic.
>
> One problem: very slow connection....can I help?
> try to make some tests?
>

Just an update: slow connection was a problem with my AP wifi.

So my device is working well.

Thank you, best regards

--
Matteo Filippetto
http://op83.blogspot.com

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