Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

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adr
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Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

adr
Hello,

I'm going nuts trying to find out why h5 is unstable... but that's
another story. The case is that studying the code it seems to me that
it would be more consistent to add H3_CLK_PLL_CPUX to sun8i_h3_gates[]
and use sxiccmu_ccu_enable (or even SXICLR4(sc, sun8i_h3_gates[idx].reg,
(1U << sun8i_h3_gates[idx].bit));) than what I proposed before.

Regards,
adr.

=======================================================================
--- sys/dev/fdt/sxiccmu.c.orig Thu Oct 29 17:41:05 2020
+++ sys/dev/fdt/sxiccmu.c Mon Nov  2 16:45:02 2020
@@ -1158,7 +1158,6 @@
 
 /* Allwinner H3/H5 */
 #define H3_PLL_CPUX_CTRL_REG 0x0000
-#define H3_PLL_CPUX_ENABLE (1 << 31)
 #define H3_PLL_CPUX_LOCK (1 << 28)
 #define H3_PLL_CPUX_OUT_EXT_DIVP(x) (((x) >> 16) & 0x3)
 #define H3_PLL_CPUX_OUT_EXT_DIVP_MASK (0x3 << 16)
@@ -1648,9 +1647,7 @@
  n--;
 
  /* Gate the PLL first */
- reg = SXIREAD4(sc, H3_PLL_CPUX_CTRL_REG);
- reg &= ~H3_PLL_CPUX_ENABLE;
- SXIWRITE4(sc, H3_PLL_CPUX_CTRL_REG, reg);
+ sxiccmu_ccu_enable(sc, &idx, 0);
 
  /* Set factors and external divider. */
  reg &= ~H3_PLL_CPUX_OUT_EXT_DIVP_MASK;
@@ -1662,8 +1659,7 @@
  SXIWRITE4(sc, H3_PLL_CPUX_CTRL_REG, reg);
 
  /* Ungate the PLL */
- reg |= H3_PLL_CPUX_ENABLE;
- SXIWRITE4(sc, H3_PLL_CPUX_CTRL_REG, reg);
+ sxiccmu_ccu_enable(sc, &idx, 1);
 
  /* Wait for PLL to lock. (LOCK flag is unreliable) */
  lock_time = SXIREAD4(sc, H3_PLL_STABLE_TIME_REG1);
=======================================================================
--- sys/dev/fdt/sxiccmu_clocks.h.orig Thu Oct 29 17:37:07 2020
+++ sys/dev/fdt/sxiccmu_clocks.h Thu Oct 29 17:40:18 2020
@@ -354,6 +354,7 @@
 #define H3_CLK_HOSC 253
 
 struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
+ [H3_CLK_PLL_CPUX] = { 0x0000, 31 },
  [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 },
  [H3_CLK_BUS_MMC0] = { 0x0060, 8 },
  [H3_CLK_BUS_MMC1] = { 0x0060, 9 },
=======================================================================