I'm going nuts trying to find out why h5 is unstable... but that's
another story. The case is that studying the code it seems to me that
it would be more consistent to add H3_CLK_PLL_CPUX to sun8i_h3_gates
and use sxiccmu_ccu_enable (or even SXICLR4(sc, sun8i_h3_gates[idx].reg,
(1U << sun8i_h3_gates[idx].bit));) than what I proposed before.
--- sys/dev/fdt/sxiccmu.c.orig Thu Oct 29 17:41:05 2020
+++ sys/dev/fdt/sxiccmu.c Mon Nov 2 16:45:02 2020
@@ -1158,7 +1158,6 @@