[PATCH] re: disable PCIe ASPM and ECPM (CLKREQ)

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[PATCH] re: disable PCIe ASPM and ECPM (CLKREQ)

Kevin Lo
From FreeBSD (r227593, r307982):
More and more RealTek controllers started to implement EEE feature.
Vendor driver seems to load a kind of firmware for EEE with
additional PHY fixups.  It is known that the EEE feature may need
ASPM support.  Unfortunately there is no documentation for EEE of
the controller so enabling ASPM may cause more problems.

The Realtek vendor driver [1] also disables ASPM and clock request.
While here, add a define for the ECPM (Enable Clock Power Management) bit.

Tested with:
re0 at pci3 dev 0 function 0 "Realtek 8168" rev 0x0c: RTL8168G/8111G (0x4c00), msi, address 44:8a:5b:39:0a:25
rgephy0 at re0 phy 7: RTL8251 PHY, rev. 0

re0 at pci2 dev 0 function 0 "Realtek 8168" rev 0x03: RTL8168D/8111D (0x2800), msi, address bc:ae:c5:d6:ac:a3
rgephy0 at re0 phy 7: RTL8169S/8110S/8211 PHY, rev. 2

[1] http://www.realtek.com.tw/downloads/downloadsView.aspx?Langid=1&PNid=13&PFid=5&Level=5&Conn=4&DownTypeID=3&GetDown=false#2

Index: sys/dev/ic/rtl81x9reg.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/rtl81x9reg.h,v
retrieving revision 1.100
diff -u -p -u -p -r1.100 rtl81x9reg.h
--- sys/dev/ic/rtl81x9reg.h 16 Nov 2016 01:27:45 -0000 1.100
+++ sys/dev/ic/rtl81x9reg.h 17 May 2017 07:36:29 -0000
@@ -863,6 +863,7 @@ struct rl_softc {
  bus_space_handle_t rl_bhandle; /* bus space handle */
  bus_space_tag_t rl_btag; /* bus space tag */
  bus_dma_tag_t sc_dmat;
+ u_int32_t rl_expcap;
  bus_dma_segment_t sc_rx_seg;
  bus_dmamap_t sc_rx_dmamap;
  struct arpcom sc_arpcom; /* interface info */
Index: sys/dev/pci/if_re_pci.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_re_pci.c,v
retrieving revision 1.50
diff -u -p -u -p -r1.50 if_re_pci.c
--- sys/dev/pci/if_re_pci.c 28 Dec 2015 05:49:15 -0000 1.50
+++ sys/dev/pci/if_re_pci.c 17 May 2017 07:36:29 -0000
@@ -128,6 +128,7 @@ re_pci_attach(struct device *parent, str
  pci_chipset_tag_t pc = pa->pa_pc;
  pci_intr_handle_t ih;
  const char *intrstr = NULL;
+ pcireg_t reg;
 
  pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
 
@@ -172,8 +173,16 @@ re_pci_attach(struct device *parent, str
  * PCI Express check.
  */
  if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
-    NULL, NULL))
+    &sc->rl_expcap, NULL)) {
+ /* Disable PCIe ASPM and ECPM. */
+ reg = pci_conf_read(pc, pa->pa_tag,
+    sc->rl_expcap + PCI_PCIE_LCSR);
+ reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 |
+    PCI_PCIE_LCSR_ECPM);
+ pci_conf_write(pc, pa->pa_tag,
+    sc->rl_expcap + PCI_PCIE_LCSR, reg);
  sc->rl_flags |= RL_FLAG_PCIE;
+ }
 
  if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK &&
     PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139)) {
Index: sys/dev/pci/pcireg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/pcireg.h,v
retrieving revision 1.53
diff -u -p -u -p -r1.53 pcireg.h
--- sys/dev/pci/pcireg.h 25 Mar 2017 07:33:46 -0000 1.53
+++ sys/dev/pci/pcireg.h 17 May 2017 07:36:29 -0000
@@ -574,6 +574,7 @@ typedef u_int8_t pci_revision_t;
 #define PCI_PCIE_LCSR_ASPM_L0S 0x00000001
 #define PCI_PCIE_LCSR_ASPM_L1 0x00000002
 #define PCI_PCIE_LCSR_ES 0x00000080
+#define PCI_PCIE_LCSR_ECPM 0x00000100
 #define PCI_PCIE_SLCAP 0x14
 #define PCI_PCIE_SLCAP_ABP 0x00000001
 #define PCI_PCIE_SLCAP_PCP 0x00000002

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Re: [PATCH] re: disable PCIe ASPM and ECPM (CLKREQ)

Kevin Lo-3
On Wed, May 17, 2017 at 03:58:16PM +0800, Kevin Lo wrote:

>
> >From FreeBSD (r227593, r307982):
> More and more RealTek controllers started to implement EEE feature.
> Vendor driver seems to load a kind of firmware for EEE with
> additional PHY fixups.  It is known that the EEE feature may need
> ASPM support.  Unfortunately there is no documentation for EEE of
> the controller so enabling ASPM may cause more problems.
>
> The Realtek vendor driver [1] also disables ASPM and clock request.
> While here, add a define for the ECPM (Enable Clock Power Management) bit.
>
> Tested with:
> re0 at pci3 dev 0 function 0 "Realtek 8168" rev 0x0c: RTL8168G/8111G (0x4c00), msi, address 44:8a:5b:39:0a:25
> rgephy0 at re0 phy 7: RTL8251 PHY, rev. 0
>
> re0 at pci2 dev 0 function 0 "Realtek 8168" rev 0x03: RTL8168D/8111D (0x2800), msi, address bc:ae:c5:d6:ac:a3
> rgephy0 at re0 phy 7: RTL8169S/8110S/8211 PHY, rev. 2
>
> [1] http://www.realtek.com.tw/downloads/downloadsView.aspx?Langid=1&PNid=13&PFid=5&Level=5&Conn=4&DownTypeID=3&GetDown=false#2

Updated diff which removes rl_expcap from the softc; spotted by stsp@

Index: sys/dev/pci/if_re_pci.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_re_pci.c,v
retrieving revision 1.50
diff -u -p -u -p -r1.50 if_re_pci.c
--- sys/dev/pci/if_re_pci.c 28 Dec 2015 05:49:15 -0000 1.50
+++ sys/dev/pci/if_re_pci.c 10 Jun 2017 15:03:39 -0000
@@ -128,6 +128,8 @@ re_pci_attach(struct device *parent, str
  pci_chipset_tag_t pc = pa->pa_pc;
  pci_intr_handle_t ih;
  const char *intrstr = NULL;
+ pcireg_t reg;
+ int offset;
 
  pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
 
@@ -172,8 +174,14 @@ re_pci_attach(struct device *parent, str
  * PCI Express check.
  */
  if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
-    NULL, NULL))
+    &offset, NULL)) {
+ /* Disable PCIe ASPM and ECPM. */
+ reg = pci_conf_read(pc, pa->pa_tag, offset + PCI_PCIE_LCSR);
+ reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 |
+    PCI_PCIE_LCSR_ECPM);
+ pci_conf_write(pc, pa->pa_tag, offset + PCI_PCIE_LCSR, reg);
  sc->rl_flags |= RL_FLAG_PCIE;
+ }
 
  if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK &&
     PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139)) {
Index: sys/dev/pci/pcireg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/pcireg.h,v
retrieving revision 1.53
diff -u -p -u -p -r1.53 pcireg.h
--- sys/dev/pci/pcireg.h 25 Mar 2017 07:33:46 -0000 1.53
+++ sys/dev/pci/pcireg.h 10 Jun 2017 15:03:39 -0000
@@ -574,6 +574,7 @@ typedef u_int8_t pci_revision_t;
 #define PCI_PCIE_LCSR_ASPM_L0S 0x00000001
 #define PCI_PCIE_LCSR_ASPM_L1 0x00000002
 #define PCI_PCIE_LCSR_ES 0x00000080
+#define PCI_PCIE_LCSR_ECPM 0x00000100
 #define PCI_PCIE_SLCAP 0x14
 #define PCI_PCIE_SLCAP_ABP 0x00000001
 #define PCI_PCIE_SLCAP_PCP 0x00000002

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Re: [PATCH] re: disable PCIe ASPM and ECPM (CLKREQ)

Stefan Sperling-5
On Sat, Jun 10, 2017 at 11:06:43PM +0800, Kevin Lo wrote:

> On Wed, May 17, 2017 at 03:58:16PM +0800, Kevin Lo wrote:
> >
> > >From FreeBSD (r227593, r307982):
> > More and more RealTek controllers started to implement EEE feature.
> > Vendor driver seems to load a kind of firmware for EEE with
> > additional PHY fixups.  It is known that the EEE feature may need
> > ASPM support.  Unfortunately there is no documentation for EEE of
> > the controller so enabling ASPM may cause more problems.
> >
> > The Realtek vendor driver [1] also disables ASPM and clock request.
> > While here, add a define for the ECPM (Enable Clock Power Management) bit.
> >
> > Tested with:
> > re0 at pci3 dev 0 function 0 "Realtek 8168" rev 0x0c: RTL8168G/8111G (0x4c00), msi, address 44:8a:5b:39:0a:25
> > rgephy0 at re0 phy 7: RTL8251 PHY, rev. 0
> >
> > re0 at pci2 dev 0 function 0 "Realtek 8168" rev 0x03: RTL8168D/8111D (0x2800), msi, address bc:ae:c5:d6:ac:a3
> > rgephy0 at re0 phy 7: RTL8169S/8110S/8211 PHY, rev. 2
> >
> > [1] http://www.realtek.com.tw/downloads/downloadsView.aspx?Langid=1&PNid=13&PFid=5&Level=5&Conn=4&DownTypeID=3&GetDown=false#2
>
> Updated diff which removes rl_expcap from the softc; spotted by stsp@

Also works on:

re0 at pci1 dev 0 function 0 "Realtek 8101E" rev 0x05: RTL8105E (0x4080), msi, address 04:7d:7b:21:ad:9d
rlphy0 at re0 phy 7: RTL8201E 10/100 PHY, rev. 2

 1:0:0: Realtek 8101E
        0x0000: Vendor ID: 10ec Product ID: 8136
        0x0004: Command: 0007 Status: 0010
        0x0008: Class: 02 Subclass: 00 Interface: 00 Revision: 05
        0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 10
        0x0010: BAR io addr: 0x00003000/0x0100
        0x0014: BAR empty (00000000)
        0x0018: BAR mem prefetchable 64bit addr: 0x0000000090004000/0x00001000
        0x0020: BAR mem prefetchable 64bit addr: 0x0000000090000000/0x00004000
        0x0028: Cardbus CIS: 00000000
        0x002c: Subsystem Vendor ID: 1025 Product ID: 058f
        0x0030: Expansion ROM Base Address: 00000000
        0x0038: 00000000
        0x003c: Interrupt Pin: 01 Line: 0b Min Gnt: 00 Max Lat: 00
        0x0040: Capability 0x01: Power Management
                State: D0 PME# enabled
        0x0050: Capability 0x05: Message Signalled Interrupts (MSI)
        0x0070: Capability 0x10: PCI Express
                Link Speed: 2.5 / 2.5 GT/s Link Width: x1 / x1
        0x0100: Enhanced Capability 0x01: Advanced Error Reporting
        0x0140: Enhanced Capability 0x02: Virtual Channel Capability
        0x0160: Enhanced Capability 0x03: Device Serial Number
        0x00b0: Capability 0x11: Extended Message Signalled Interrupts (MSI-X)
        0x00d0: Capability 0x03: Vital Product Data (VPD)

OK by me.

> Index: sys/dev/pci/if_re_pci.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/if_re_pci.c,v
> retrieving revision 1.50
> diff -u -p -u -p -r1.50 if_re_pci.c
> --- sys/dev/pci/if_re_pci.c 28 Dec 2015 05:49:15 -0000 1.50
> +++ sys/dev/pci/if_re_pci.c 10 Jun 2017 15:03:39 -0000
> @@ -128,6 +128,8 @@ re_pci_attach(struct device *parent, str
>   pci_chipset_tag_t pc = pa->pa_pc;
>   pci_intr_handle_t ih;
>   const char *intrstr = NULL;
> + pcireg_t reg;
> + int offset;
>  
>   pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
>  
> @@ -172,8 +174,14 @@ re_pci_attach(struct device *parent, str
>   * PCI Express check.
>   */
>   if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
> -    NULL, NULL))
> +    &offset, NULL)) {
> + /* Disable PCIe ASPM and ECPM. */
> + reg = pci_conf_read(pc, pa->pa_tag, offset + PCI_PCIE_LCSR);
> + reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 |
> +    PCI_PCIE_LCSR_ECPM);
> + pci_conf_write(pc, pa->pa_tag, offset + PCI_PCIE_LCSR, reg);
>   sc->rl_flags |= RL_FLAG_PCIE;
> + }
>  
>   if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK &&
>      PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139)) {
> Index: sys/dev/pci/pcireg.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/pcireg.h,v
> retrieving revision 1.53
> diff -u -p -u -p -r1.53 pcireg.h
> --- sys/dev/pci/pcireg.h 25 Mar 2017 07:33:46 -0000 1.53
> +++ sys/dev/pci/pcireg.h 10 Jun 2017 15:03:39 -0000
> @@ -574,6 +574,7 @@ typedef u_int8_t pci_revision_t;
>  #define PCI_PCIE_LCSR_ASPM_L0S 0x00000001
>  #define PCI_PCIE_LCSR_ASPM_L1 0x00000002
>  #define PCI_PCIE_LCSR_ES 0x00000080
> +#define PCI_PCIE_LCSR_ECPM 0x00000100
>  #define PCI_PCIE_SLCAP 0x14
>  #define PCI_PCIE_SLCAP_ABP 0x00000001
>  #define PCI_PCIE_SLCAP_PCP 0x00000002
>