LLVM update (again)

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LLVM update (again)

Pascal Stumpf
So here's an updated diff for LLVM 3.7.1.  With landry@'s recent commit,
xulrunner is no longer a showstopper.


Index: Makefile
===================================================================
RCS file: /cvs/ports/devel/llvm/Makefile,v
retrieving revision 1.108
diff -u -p -r1.108 Makefile
--- Makefile 24 Aug 2015 07:45:56 -0000 1.108
+++ Makefile 23 Jan 2016 18:38:51 -0000
@@ -8,14 +8,17 @@ DPB_PROPERTIES = parallel
 
 COMMENT = modular, fast C/C++/ObjC compiler, static analyzer and tools
 
-LLVM_V = 3.5
-DISTNAME = llvm-${LLVM_V}.20140228
-REVISION = 35
+LLVM_V = 3.7.1
+DISTNAME = llvm-${LLVM_V}.src
+PKGNAME = llvm-${LLVM_V}
 CATEGORIES = devel
-MASTER_SITES = http://comstyle.com/source/
+DISTFILES = llvm-${LLVM_V}.src${EXTRACT_SUFX} \
+ cfe-${LLVM_V}.src${EXTRACT_SUFX}
+MASTER_SITES = http://www.llvm.org/releases/${LLVM_V}/
 EXTRACT_SUFX = .tar.xz
 
-SHARED_LIBS = clang 1.0
+SHARED_LIBS = clang 2.0 \
+ LTO 0.0
 
 # packager notes in http://llvm.org/docs/Packaging.html
 HOMEPAGE = http://www.llvm.org/
@@ -25,15 +28,21 @@ MAINTAINER= Brad Smith <[hidden email]
 # BSD
 PERMIT_PACKAGE_CDROM = Yes
 
-WANTLIB = c m pthread stdc++ z
+WANTLIB = c m pthread z
 
 MODULES = devel/cmake \
- lang/python
+ lang/python \
+ gcc4
 
-TEST_DEPENDS = devel/dejagnu \
- shells/bash
+MODGCC4_LANGS = c c++
+MODGCC4_ARCHS = *
+
+TEST_DEPENDS = devel/dejagnu \
+ shells/bash \
+ lang/gcc/${MODGCC4_VERSION},-c++
 BUILD_DEPENDS += textproc/py-sphinx
-RUN_DEPENDS += devel/gtest
+RUN_DEPENDS += devel/gtest \
+ lang/gcc/${MODGCC4_VERSION},-c++
 
 SEPARATE_BUILD = Yes
 CONFIGURE_ARGS = -DLLVM_ENABLE_FFI:Bool=False \
@@ -47,22 +56,34 @@ CONFIGURE_ARGS = -DLLVM_ENABLE_FFI:Bool=
 # introduced when PIE was enabled
 .if ${MACHINE_ARCH} == "powerpc"
 CONFIGURE_ARGS += -DCMAKE_EXE_LINKER_FLAGS="-Wl,--relax -nopie"
+CONFIGURE_ARGS += -DCMAKE_SHARED_LINKER_FLAGS="-Wl,--relax -nopie"
 .endif
 
 TEST_TARGET = check
 
+# XXX sync
+GCC_VER = 4.9.3
+.if ${MACHINE_ARCH} == "amd64"
+GCC_CONFIG = x86_64-unknown-openbsd${OSREV}
+.else
+GCC_CONFIG = ${MACHINE_ARCH}-unknown-openbsd${OSREV}
+.endif
 CLANG_INCLUDE_PATH = lib/clang/${LLVM_V}/include
-SUBST_VARS += CLANG_INCLUDE_PATH LLVM_V
+SUBST_VARS += CLANG_INCLUDE_PATH LLVM_V GCC_VER GCC_CONFIG
+
+post-extract:
+ mv ${WRKDIR}/cfe-${LLVM_V}.src ${WRKSRC}/tools/clang
 
 pre-configure:
- @${SUBST_CMD} ${WRKSRC}/tools/clang/tools/scan-build/scan-build
+ @${SUBST_CMD} ${WRKSRC}/tools/clang/tools/scan-build/scan-build \
+ ${WRKSRC}/tools/clang/lib/Driver/ToolChains.cpp
+ @${SUBST_CMD} ${WRKSRC}/tools/clang/tools/scan-build/scan-build \
+ ${WRKSRC}/tools/clang/lib/Driver/Tools.cpp
  -@ln -s ${MODPY_BIN} ${WRKDIR}/bin/python
 
 post-build:
  cd ${WRKSRC}/docs && make -f Makefile.sphinx man
- pod2man --release=CVS --center="LLVM" \
-    ${WRKSRC}/tools/clang/docs/tools/clang.pod \
-    ${WRKSRC}/docs/_build/man/clang.1
+ cd ${WRKSRC}/tools/clang/docs && make -f Makefile.sphinx man
 
 post-install:
  ${INSTALL_SCRIPT} ${WRKSRC}/tools/clang/tools/scan-build/ccc-analyzer \
@@ -75,7 +96,10 @@ post-install:
     ${PREFIX}/man/man1
  ${INSTALL_DATA} ${WRKSRC}/tools/clang/tools/scan-build/scan-build.1 \
     ${PREFIX}/man/man1
- # lit is not installed anymore
+ ${INSTALL_DATA} ${WRKSRC}/tools/clang/docs/_build/man/clang.1 \
+    ${PREFIX}/man/man1
+ # lit and FileCheck are not installed
  @rm ${PREFIX}/man/man1/lit.1
+ @rm ${PREFIX}/man/man1/FileCheck.1
 
 .include <bsd.port.mk>
Index: distinfo
===================================================================
RCS file: /cvs/ports/devel/llvm/distinfo,v
retrieving revision 1.13
diff -u -p -r1.13 distinfo
--- distinfo 18 Apr 2014 09:30:48 -0000 1.13
+++ distinfo 23 Jan 2016 18:38:51 -0000
@@ -1,2 +1,4 @@
-SHA256 (llvm-3.5.20140228.tar.xz) = vBFmbVEiY2CQZf7Boqcebh+s+ejpfpoZ8vY5c3cxgXw=
-SIZE (llvm-3.5.20140228.tar.xz) = 17945548
+SHA256 (cfe-3.7.1.src.tar.xz) = VuIWTHwqF3LV7So+V0hf9z/wbJff8S7b7qGsxEErBnQ=
+SHA256 (llvm-3.7.1.src.tar.xz) = vneU7QzsQtbGgsqONRdTW1RVWj3vq+yDVU28dNtUWtU=
+SIZE (cfe-3.7.1.src.tar.xz) = 9110616
+SIZE (llvm-3.7.1.src.tar.xz) = 14592544
Index: patches/patch-CMakeLists_txt
===================================================================
RCS file: patches/patch-CMakeLists_txt
diff -N patches/patch-CMakeLists_txt
--- patches/patch-CMakeLists_txt 18 Apr 2014 09:30:48 -0000 1.4
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,15 +0,0 @@
-$OpenBSD: patch-CMakeLists_txt,v 1.4 2014/04/18 09:30:48 brad Exp $
-
-Don't confuse scripts who want the version with appended 'svn' goo.
-
---- CMakeLists.txt.orig Sun Mar  2 21:57:43 2014
-+++ CMakeLists.txt Sun Mar  2 22:13:02 2014
-@@ -29,7 +29,7 @@ set(LLVM_VERSION_MAJOR 3)
- set(LLVM_VERSION_MINOR 5)
-
- if (NOT PACKAGE_VERSION)
--  set(PACKAGE_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}svn")
-+  set(PACKAGE_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}")
- endif()
-
- option(LLVM_INSTALL_TOOLCHAIN_ONLY "Only include toolchain files in the 'install' target." OFF)
Index: patches/patch-Makefile_config_in
===================================================================
RCS file: /cvs/ports/devel/llvm/patches/patch-Makefile_config_in,v
retrieving revision 1.8
diff -u -p -r1.8 patch-Makefile_config_in
--- patches/patch-Makefile_config_in 18 Apr 2014 09:30:48 -0000 1.8
+++ patches/patch-Makefile_config_in 23 Jan 2016 18:38:51 -0000
@@ -1,7 +1,7 @@
 $OpenBSD: patch-Makefile_config_in,v 1.8 2014/04/18 09:30:48 brad Exp $
---- Makefile.config.in.orig Sun Feb 16 19:19:46 2014
-+++ Makefile.config.in Sun Feb 16 19:28:35 2014
-@@ -99,11 +99,11 @@ endif
+--- Makefile.config.in.orig Wed Aug 12 19:12:16 2015
++++ Makefile.config.in Tue Sep  8 21:53:49 2015
+@@ -106,11 +106,11 @@ endif
  PROJ_bindir     := $(PROJ_prefix)/bin
  PROJ_libdir     := $(PROJ_prefix)/lib
  PROJ_datadir    := $(PROJ_prefix)/share
Index: patches/patch-cmake_modules_AddLLVM_cmake
===================================================================
RCS file: patches/patch-cmake_modules_AddLLVM_cmake
diff -N patches/patch-cmake_modules_AddLLVM_cmake
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ patches/patch-cmake_modules_AddLLVM_cmake 23 Jan 2016 18:38:51 -0000
@@ -0,0 +1,12 @@
+$OpenBSD$
+--- cmake/modules/AddLLVM.cmake.orig Fri Sep 11 17:38:23 2015
++++ cmake/modules/AddLLVM.cmake Fri Sep 11 17:39:48 2015
+@@ -178,7 +178,7 @@ function(add_link_opts target_name)
+       elseif(${CMAKE_SYSTEM_NAME} MATCHES "SunOS")
+         set_property(TARGET ${target_name} APPEND_STRING PROPERTY
+                      LINK_FLAGS " -Wl,-z -Wl,discard-unused=sections")
+-      elseif(NOT WIN32 AND NOT LLVM_LINKER_IS_GOLD)
++      elseif(NOT WIN32 AND NOT LLVM_LINKER_IS_GOLD AND NOT ${CMAKE_SYSTEM_NAME} MATCHES "OpenBSD")
+         # Object files are compiled with -ffunction-data-sections.
+         # Versions of bfd ld < 2.23.1 have a bug in --gc-sections that breaks
+         # tools that use plugins. Always pass --gc-sections once we require
Index: patches/patch-cmake_modules_HandleLLVMOptions_cmake
===================================================================
RCS file: /cvs/ports/devel/llvm/patches/patch-cmake_modules_HandleLLVMOptions_cmake,v
retrieving revision 1.1
diff -u -p -r1.1 patch-cmake_modules_HandleLLVMOptions_cmake
--- patches/patch-cmake_modules_HandleLLVMOptions_cmake 18 Apr 2014 09:30:48 -0000 1.1
+++ patches/patch-cmake_modules_HandleLLVMOptions_cmake 23 Jan 2016 18:38:51 -0000
@@ -1,49 +1,13 @@
-$OpenBSD: patch-cmake_modules_HandleLLVMOptions_cmake,v 1.1 2014/04/18 09:30:48 brad Exp $
---- cmake/modules/HandleLLVMOptions.cmake.orig Sat Feb  8 15:05:05 2014
-+++ cmake/modules/HandleLLVMOptions.cmake Sat Feb  8 15:05:17 2014
-@@ -7,45 +7,6 @@ include(AddLLVMDefinitions)
- include(CheckCCompilerFlag)
- include(CheckCXXCompilerFlag)
-
--if(NOT LLVM_FORCE_USE_OLD_TOOLCHAIN)
--  if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
--    if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 4.7)
--      message(FATAL_ERROR "Host GCC version must be at least 4.7!")
--    endif()
--  elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Clang")
--    if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 3.1)
--      message(FATAL_ERROR "Host Clang version must be at least 3.1!")
--    endif()
--
--    # Also test that we aren't using too old of a version of libstdc++ with the
--    # Clang compiler. This is tricky as there is no real way to check the
--    # version of libstdc++ directly. Instead we test for a known bug in
--    # libstdc++4.6 that is fixed in libstdc++4.7.
--    if(NOT LLVM_ENABLE_LIBCXX)
--      set(OLD_CMAKE_REQUIRED_FLAGS ${CMAKE_REQUIRED_FLAGS})
--      set(OLD_CMAKE_REQUIRED_LIBRARIES ${CMAKE_REQUIRED_LIBRARIES})
--      set(CMAKE_REQUIRED_FLAGS "-std=c++0x")
--      if (ANDROID)
--        set(CMAKE_REQUIRED_LIBRARIES "atomic")
--      endif()
--      check_cxx_source_compiles("
--#include <atomic>
--std::atomic<float> x(0.0f);
--int main() { return (float)x; }"
--        LLVM_NO_OLD_LIBSTDCXX)
--      if(NOT LLVM_NO_OLD_LIBSTDCXX)
--        message(FATAL_ERROR "Host Clang must be able to find libstdc++4.7 or newer!")
--      endif()
--      set(CMAKE_REQUIRED_FLAGS ${OLD_CMAKE_REQUIRED_FLAGS})
--      set(CMAKE_REQUIRED_LIBRARIES ${OLD_CMAKE_REQUIRED_LIBRARIES})
--    endif()
--  elseif(CMAKE_CXX_COMPILER_ID MATCHES "MSVC")
--    if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 17.0)
--      message(FATAL_ERROR "Host Visual Studio must be at least 2012 (MSVC 17.0)")
--    endif()
--  endif()
--endif()
--
- if( LLVM_ENABLE_ASSERTIONS )
-   # MSVC doesn't like _DEBUG on release builds. See PR 4379.
-   if( NOT MSVC )
+$OpenBSD$
+--- cmake/modules/HandleLLVMOptions.cmake.orig Wed Sep  9 14:34:05 2015
++++ cmake/modules/HandleLLVMOptions.cmake Wed Sep  9 14:34:55 2015
+@@ -132,7 +132,8 @@ endif()
+ # Pass -Wl,-z,defs. This makes sure all symbols are defined. Otherwise a DSO
+ # build might work on ELF but fail on MachO/COFF.
+ if(NOT (${CMAKE_SYSTEM_NAME} MATCHES "Darwin" OR WIN32 OR CYGWIN OR
+-        ${CMAKE_SYSTEM_NAME} MATCHES "FreeBSD") AND
++        ${CMAKE_SYSTEM_NAME} MATCHES "FreeBSD" OR
++ ${CMAKE_SYSTEM_NAME} MATCHES "OpenBSD") AND
+    NOT LLVM_USE_SANITIZER)
+   set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -Wl,-z,defs")
+ endif()
Index: patches/patch-include_llvm_CodeGen_SelectionDAGISel_h
===================================================================
RCS file: patches/patch-include_llvm_CodeGen_SelectionDAGISel_h
diff -N patches/patch-include_llvm_CodeGen_SelectionDAGISel_h
--- patches/patch-include_llvm_CodeGen_SelectionDAGISel_h 24 Aug 2015 07:45:56 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,59 +0,0 @@
-$OpenBSD: patch-include_llvm_CodeGen_SelectionDAGISel_h,v 1.1 2015/08/24 07:45:56 ajacoutot Exp $
-
-r219009
-[ISel] Keep matching state consistent when folding during X86 address match
-
-In the X86 backend, matching an address is initiated by the 'addr' complex
-pattern and its friends.  During this process we may reassociate and-of-shift
-into shift-of-and (FoldMaskedShiftToScaledMask) to allow folding of the
-shift into the scale of the address.
-
-However as demonstrated by the testcase, this can trigger CSE of not only the
-shift and the AND which the code is prepared for but also the underlying load
-node.  In the testcase this node is sitting in the RecordedNode and MatchScope
-data structures of the matcher and becomes a deleted node upon CSE.  Returning
-from the complex pattern function, we try to access it again hitting an assert
-because the node is no longer a load even though this was checked before.
-
-Now obviously changing the DAG this late is bending the rules but I think it
-makes sense somewhat.  Outside of addresses we prefer and-of-shift because it
-may lead to smaller immediates (FoldMaskAndShiftToScale is an even better
-example because it create a non-canonical node).  We currently don't recognize
-addresses during DAGCombiner where arguably this canonicalization should be
-performed.  On the other hand, having this in the matcher allows us to cover
-all the cases where an address can be used in an instruction.
-
-I've also talked a little bit to Dan Gohman on llvm-dev who added the RAUW for
-the new shift node in FoldMaskedShiftToScaledMask.  This RAUW is responsible
-for initiating the recursive CSE on users
-(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-September/076903.html) but it
-is not strictly necessary since the shift is hooked into the visited user.  Of
-course it's safer to keep the DAG consistent at all times (e.g. for accurate
-number of uses, etc.).
-
-So rather than changing the fundamentals, I've decided to continue along the
-previous patches and detect the CSE.  This patch installs a very targeted
-DAGUpdateListener for the duration of a complex-pattern match and updates the
-matching state accordingly.  (Previous patches used HandleSDNode to detect the
-CSE but that's not practical here).  The listener is only installed on X86.
-
-I tested that there is no measurable overhead due to this while running
-through the spec2k BC files with llc.  The only thing we pay for is the
-creation of the listener.  The callback never ever triggers in spec2k since
-this is a corner case.
-
---- include/llvm/CodeGen/SelectionDAGISel.h.orig Tue Aug  4 22:44:44 2015
-+++ include/llvm/CodeGen/SelectionDAGISel.h Tue Aug  4 22:46:22 2015
-@@ -238,6 +238,12 @@ class SelectionDAGISel : public MachineFunctionPass {
-                            const unsigned char *MatcherTable,
-                            unsigned TableSize);
-
-+  /// \brief Return true if complex patterns for this target can mutate the
-+  /// DAG.
-+  virtual bool ComplexPatternFuncMutatesDAG() const {
-+    return false;
-+  }
-+
- private:
-
-   // Calls to these functions are generated by tblgen.
Index: patches/patch-include_llvm_CodeGen_SelectionDAG_h
===================================================================
RCS file: patches/patch-include_llvm_CodeGen_SelectionDAG_h
diff -N patches/patch-include_llvm_CodeGen_SelectionDAG_h
--- patches/patch-include_llvm_CodeGen_SelectionDAG_h 15 Nov 2014 03:26:40 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,30 +0,0 @@
-$OpenBSD: patch-include_llvm_CodeGen_SelectionDAG_h,v 1.1 2014/11/15 03:26:40 brad Exp $
-
-r221709  
-Totally forget deallocated SDNodes in SDDbgInfo.
-
-What would happen before that commit is that the SDDbgValues associated with
-a deallocated SDNode would be marked Invalidated, but SDDbgInfo would keep
-a map entry keyed by the SDNode pointer pointing to this list of invalidated
-SDDbgNodes. As the memory gets reused, the list might get wrongly associated
-with another new SDNode. As the SDDbgValues are cloned when they are transfered,
-this can lead to an exponential number of SDDbgValues being produced during
-DAGCombine like in http://llvm.org/bugs/show_bug.cgi?id=20893
-
-Note that the previous behavior wasn't really buggy as the invalidation made
-sure that the SDDbgValues won't be used. This commit can be considered a
-memory optimization and as such is really hard to validate in a unit-test.
-
---- include/llvm/CodeGen/SelectionDAG.h.orig Fri Nov 14 21:08:36 2014
-+++ include/llvm/CodeGen/SelectionDAG.h Fri Nov 14 21:09:49 2014
-@@ -126,6 +126,10 @@ class SDDbgInfo { (public)
-       DbgValMap[Node].push_back(V);
-   }
-
-+  /// \brief Invalidate all DbgValues attached to the node and remove
-+  /// it from the Node-to-DbgValues map.
-+  void erase(const SDNode *Node);
-+
-   void clear() {
-     DbgValMap.clear();
-     DbgValues.clear();
Index: patches/patch-include_llvm_Config_config_h_cmake
===================================================================
RCS file: patches/patch-include_llvm_Config_config_h_cmake
diff -N patches/patch-include_llvm_Config_config_h_cmake
--- patches/patch-include_llvm_Config_config_h_cmake 26 Jul 2014 09:27:29 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,16 +0,0 @@
-$OpenBSD: patch-include_llvm_Config_config_h_cmake,v 1.1 2014/07/26 09:27:29 pascal Exp $
-
-r213966
-Fix arc4random detection.
-
---- include/llvm/Config/config.h.cmake.orig Wed Jul  9 15:45:23 2014
-+++ include/llvm/Config/config.h.cmake Wed Jul  9 15:59:51 2014
-@@ -34,7 +34,7 @@
- #undef GCC_INSTALL_PREFIX
-
- /* Define to 1 if you have the `arc4random' function. */
--#cmakedefine HAVE_ARC4RANDOM
-+#cmakedefine HAVE_DECL_ARC4RANDOM ${HAVE_DECL_ARC4RANDOM}
-
- /* Define to 1 if you have the `backtrace' function. */
- #cmakedefine HAVE_BACKTRACE ${HAVE_BACKTRACE}
Index: patches/patch-include_llvm_Support_ELF_h
===================================================================
RCS file: patches/patch-include_llvm_Support_ELF_h
diff -N patches/patch-include_llvm_Support_ELF_h
--- patches/patch-include_llvm_Support_ELF_h 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,19 +0,0 @@
-$OpenBSD: patch-include_llvm_Support_ELF_h,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- include/llvm/Support/ELF.h.orig Sun Jul 27 00:01:21 2014
-+++ include/llvm/Support/ELF.h Sun Jul 27 00:02:18 2014
-@@ -437,6 +437,7 @@ enum {
-   R_PPC_GOT16_LO              = 15,
-   R_PPC_GOT16_HI              = 16,
-   R_PPC_GOT16_HA              = 17,
-+  R_PPC_PLTREL24              = 18,
-   R_PPC_REL32                 = 26,
-   R_PPC_TLS                   = 67,
-   R_PPC_DTPMOD32              = 68,
Index: patches/patch-include_llvm_Target_TargetInstrInfo_h
===================================================================
RCS file: patches/patch-include_llvm_Target_TargetInstrInfo_h
diff -N patches/patch-include_llvm_Target_TargetInstrInfo_h
--- patches/patch-include_llvm_Target_TargetInstrInfo_h 18 Sep 2014 20:19:27 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,32 +0,0 @@
-$OpenBSD: patch-include_llvm_Target_TargetInstrInfo_h,v 1.1 2014/09/18 20:19:27 brad Exp $
-
-r217801
-Fix a lot of confusion around inserting nops on empty functions.
-
-On MachO, and MachO only, we cannot have a truly empty function since that
-breaks the linker logic for atomizing the section.
-
-When we are emitting a frame pointer, the presence of an unreachable will
-create a cfi instruction pointing past the last instruction. This is perfectly
-fine. The FDE information encodes the pc range it applies to. If some tool
-cannot handle this, we should explicitly say which bug we are working around
-and only work around it when it is actually relevant (not for ELF for example).
-
-Given the unreachable we could omit the .cfi_def_cfa_register, but then
-again, we could also omit the entire function prologue if we wanted to.
-
---- include/llvm/Target/TargetInstrInfo.h.orig Mon Sep 15 16:00:35 2014
-+++ include/llvm/Target/TargetInstrInfo.h Mon Sep 15 16:01:15 2014
-@@ -661,10 +661,8 @@ class TargetInstrInfo : public MCInstrInfo { (public)
-                           MachineBasicBlock::iterator MI) const;
-
-
--  /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
--  virtual void getNoopForMachoTarget(MCInst &NopInst) const {
--    // Default to just using 'nop' string.
--  }
-+  /// Return the noop instruction to use for a noop.
-+  virtual void getNoopForMachoTarget(MCInst &NopInst) const;
-
-
-   /// isPredicated - Returns true if the instruction is already predicated.
Index: patches/patch-lib_Analysis_IVUsers_cpp
===================================================================
RCS file: patches/patch-lib_Analysis_IVUsers_cpp
diff -N patches/patch-lib_Analysis_IVUsers_cpp
--- patches/patch-lib_Analysis_IVUsers_cpp 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,45 +0,0 @@
-$OpenBSD: patch-lib_Analysis_IVUsers_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r203719
-PR17473: Don't normalize an expression during postinc transformation unless it's
-invertible.
-
---- lib/Analysis/IVUsers.cpp.orig Sun Mar  2 21:57:38 2014
-+++ lib/Analysis/IVUsers.cpp Sat Jun 14 03:56:54 2014
-@@ -186,15 +186,34 @@ bool IVUsers::AddUsersImpl(Instruction *I,
-
-     if (AddUserToIVUsers) {
-       // Okay, we found a user that we cannot reduce.
--      IVUses.push_back(new IVStrideUse(this, User, I));
--      IVStrideUse &NewUse = IVUses.back();
-+      IVStrideUse &NewUse = AddUser(User, I);
-       // Autodetect the post-inc loop set, populating NewUse.PostIncLoops.
-       // The regular return value here is discarded; instead of recording
-       // it, we just recompute it when we need it.
-+      const SCEV *OriginalISE = ISE;
-       ISE = TransformForPostIncUse(NormalizeAutodetect,
-                                    ISE, User, I,
-                                    NewUse.PostIncLoops,
-                                    *SE, *DT);
-+
-+      // PostIncNormalization effectively simplifies the expression under
-+      // pre-increment assumptions. Those assumptions (no wrapping) might not
-+      // hold for the post-inc value. Catch such cases by making sure the
-+      // transformation is invertible.
-+      if (OriginalISE != ISE) {
-+        const SCEV *DenormalizedISE =
-+          TransformForPostIncUse(Denormalize, ISE, User, I,
-+              NewUse.PostIncLoops, *SE, *DT);
-+
-+        // If we normalized the expression, but denormalization doesn't give the
-+        // original one, discard this user.
-+        if (OriginalISE != DenormalizedISE) {
-+          DEBUG(dbgs() << "   DISCARDING (NORMALIZATION ISN'T INVERTIBLE): "
-+                       << *ISE << '\n');
-+          IVUses.pop_back();
-+          return false;
-+        }
-+      }
-       DEBUG(if (SE->getSCEV(I) != ISE)
-               dbgs() << "   NORMALIZED TO: " << *ISE << '\n');
-     }
Index: patches/patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp
===================================================================
RCS file: patches/patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp
diff -N patches/patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp
--- patches/patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp 18 Sep 2014 20:19:27 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,68 +0,0 @@
-$OpenBSD: patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp,v 1.1 2014/09/18 20:19:27 brad Exp $
-
-r217801
-Fix a lot of confusion around inserting nops on empty functions.
-
-On MachO, and MachO only, we cannot have a truly empty function since that
-breaks the linker logic for atomizing the section.
-
-When we are emitting a frame pointer, the presence of an unreachable will
-create a cfi instruction pointing past the last instruction. This is perfectly
-fine. The FDE information encodes the pc range it applies to. If some tool
-cannot handle this, we should explicitly say which bug we are working around
-and only work around it when it is actually relevant (not for ELF for example).
-
-Given the unreachable we could omit the .cfi_def_cfa_register, but then
-again, we could also omit the entire function prologue if we wanted to.
-
-r217899
-Add back a fallback case for targets that do not or cannot implement getNoopForMachoTarget().
-
---- lib/CodeGen/AsmPrinter/AsmPrinter.cpp.orig Sun Mar  2 21:57:42 2014
-+++ lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Sep 16 22:33:35 2014
-@@ -739,14 +739,12 @@ void AsmPrinter::EmitFunctionBody() {
-
-   // Print out code for the function.
-   bool HasAnyRealCode = false;
--  const MachineInstr *LastMI = 0;
-   for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
-        I != E; ++I) {
-     // Print a label for the basic block.
-     EmitBasicBlockStart(I);
-     for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
-          II != IE; ++II) {
--      LastMI = II;
-
-       // Print the assembly for the instruction.
-       if (!II->isLabel() && !II->isImplicitDef() && !II->isKill() &&
-@@ -807,24 +805,18 @@ void AsmPrinter::EmitFunctionBody() {
-     }
-   }
-
--  // If the last instruction was a prolog label, then we have a situation where
--  // we emitted a prolog but no function body. This results in the ending prolog
--  // label equaling the end of function label and an invalid "row" in the
--  // FDE. We need to emit a noop in this situation so that the FDE's rows are
--  // valid.
--  bool RequiresNoop = LastMI && LastMI->isPrologLabel();
--
-   // If the function is empty and the object file uses .subsections_via_symbols,
-   // then we need to emit *something* to the function body to prevent the
-   // labels from collapsing together.  Just emit a noop.
--  if ((MAI->hasSubsectionsViaSymbols() && !HasAnyRealCode) || RequiresNoop) {
-+  if ((MAI->hasSubsectionsViaSymbols() && !HasAnyRealCode)) {
-     MCInst Noop;
-     TM.getInstrInfo()->getNoopForMachoTarget(Noop);
--    if (Noop.getOpcode()) {
--      OutStreamer.AddComment("avoids zero-length function");
-+    OutStreamer.AddComment("avoids zero-length function");
-+
-+    // Targets can opt-out of emitting the noop here by leaving the opcode
-+    // unspecified.
-+    if (Noop.getOpcode())
-       OutStreamer.EmitInstruction(Noop, getSubtargetInfo());
--    } else  // Target not mc-ized yet.
--      OutStreamer.EmitRawText(StringRef("\tnop\n"));
-   }
-
-   const Function *F = MF->getFunction();
Index: patches/patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h
===================================================================
RCS file: patches/patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h
diff -N patches/patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h
--- patches/patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h 14 Aug 2014 01:08:09 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,21 +0,0 @@
-$OpenBSD: patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h,v 1.1 2014/08/14 01:08:09 brad Exp $
-
-r211435
-Legalizer: Add support for splitting insert_subvectors.
-
-We handle this by spilling the whole thing to the stack and doing the
-insertion as a store.
-
-PR19492. This happens in real code because the vectorizer creates v2i128 when AVX is
-enabled.
-
---- lib/CodeGen/SelectionDAG/LegalizeTypes.h.orig Thu Jul 17 01:03:52 2014
-+++ lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Jul 17 01:04:56 2014
-@@ -570,6 +570,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer { (priv
-   void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
-   void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
-   void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
-+  void SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
-   void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
-   void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
-   void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
Index: patches/patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp
===================================================================
RCS file: patches/patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp
diff -N patches/patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp
--- patches/patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp 14 Aug 2014 01:08:09 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,92 +0,0 @@
-$OpenBSD: patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp,v 1.2 2014/08/14 01:08:09 brad Exp $
-
-r211435
-Legalizer: Add support for splitting insert_subvectors.
-
-We handle this by spilling the whole thing to the stack and doing the
-insertion as a store.
-
-PR19492. This happens in real code because the vectorizer creates v2i128 when AVX is
-enabled.
-
-r203311
-ISel: Make VSELECT selection terminate in cases where the condition type has to
-be split and the result type widened.
-
-When the condition of a vselect has to be split it makes no sense widening the
-vselect and thereby widening the condition. We end up in an endless loop of
-widening (vselect result type) and splitting (condition mask type) doing this.
-Instead, split both the condition and the vselect and widen the result.
-
---- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp.orig Sun Mar  2 21:57:42 2014
-+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Jul 17 01:10:16 2014
-@@ -518,6 +518,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, un
-   case ISD::BUILD_VECTOR:      SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
-   case ISD::CONCAT_VECTORS:    SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
-   case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
-+  case ISD::INSERT_SUBVECTOR:  SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
-   case ISD::FP_ROUND_INREG:    SplitVecRes_InregOp(N, Lo, Hi); break;
-   case ISD::FPOWI:             SplitVecRes_FPOWI(N, Lo, Hi); break;
-   case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
-@@ -737,6 +738,43 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(S
-                                    TLI.getVectorIdxTy()));
- }
-
-+void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
-+                                                    SDValue &Hi) {
-+  SDValue Vec = N->getOperand(0);
-+  SDValue SubVec = N->getOperand(1);
-+  SDValue Idx = N->getOperand(2);
-+  SDLoc dl(N);
-+  GetSplitVector(Vec, Lo, Hi);
-+
-+  // Spill the vector to the stack.
-+  EVT VecVT = Vec.getValueType();
-+  EVT SubVecVT = VecVT.getVectorElementType();
-+  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
-+  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
-+                               MachinePointerInfo(), false, false, 0);
-+
-+  // Store the new subvector into the specified index.
-+  SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
-+  Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
-+  unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
-+  Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
-+                       false, false, 0);
-+
-+  // Load the Lo part from the stack slot.
-+  Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
-+                   false, false, false, 0);
-+
-+  // Increment the pointer to the other part.
-+  unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
-+  StackPtr =
-+      DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
-+                  DAG.getConstant(IncrementSize, StackPtr.getValueType()));
-+
-+  // Load the Hi part from the stack slot.
-+  Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
-+                   false, false, false, MinAlign(Alignment, IncrementSize));
-+}
-+
- void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
-                                          SDValue &Hi) {
-   SDLoc dl(N);
-@@ -2191,6 +2229,17 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N
-                                         CondEltVT, WidenNumElts);
-     if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
-       Cond1 = GetWidenedVector(Cond1);
-+
-+    // If we have to split the condition there is no point in widening the
-+    // select. This would result in an cycle of widening the select ->
-+    // widening the condition operand -> splitting the condition operand ->
-+    // splitting the select -> widening the select. Instead split this select
-+    // further and widen the resulting type.
-+    if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
-+      SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
-+      SDValue Res = ModifyToType(SplitSelect, WidenVT);
-+      return Res;
-+    }
-
-     if (Cond1.getValueType() != CondWidenVT)
-       Cond1 = ModifyToType(Cond1, CondWidenVT);
Index: patches/patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp
===================================================================
RCS file: patches/patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp
diff -N patches/patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp
--- patches/patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,43 +0,0 @@
-$OpenBSD: patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r205738
-Put a limit on ScheduleDAGSDNodes::ClusterNeighboringLoads to avoid blowing up compile time.
-
-Fixes PR16365 - Extremely slow compilation in -O1 and -O2.
-
-The SD scheduler has a quadratic implementation of load clustering
-which absolutely blows up compile time for large blocks with constant
-pool loads. The MI scheduler has a better implementation of load
-clustering. However, we have not done the work yet to completely
-eliminate the SD scheduler. Some benchmarks still seem to benefit from
-early load clustering, although maybe by chance.
-
-As an intermediate term fix, I just put a nice limit on the number of
-DAG users to search before finding a match. With this limit there are no
-binary differences in the LLVM test suite, and the PR16365 test case
-does not suffer any compile time impact from this routine.
-
---- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp.orig Sun Mar  2 21:57:42 2014
-+++ lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Sat Jun 14 04:01:39 2014
-@@ -219,8 +219,11 @@ void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNod
-   DenseMap<long long, SDNode*> O2SMap;  // Map from offset to SDNode.
-   bool Cluster = false;
-   SDNode *Base = Node;
-+  // This algorithm requires a reasonably low use count before finding a match
-+  // to avoid uselessly blowing up compile time in large blocks.
-+  unsigned UseCount = 0;
-   for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
--       I != E; ++I) {
-+       I != E && UseCount < 100; ++I, ++UseCount) {
-     SDNode *User = *I;
-     if (User == Node || !Visited.insert(User))
-       continue;
-@@ -237,6 +240,8 @@ void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNod
-     if (Offset2 < Offset1)
-       Base = User;
-     Cluster = true;
-+    // Reset UseCount to allow more matches.
-+    UseCount = 0;
-   }
-
-   if (!Cluster)
Index: patches/patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp
===================================================================
RCS file: patches/patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp
diff -N patches/patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp
--- patches/patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp 24 Aug 2015 07:45:56 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,107 +0,0 @@
-$OpenBSD: patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp,v 1.1 2015/08/24 07:45:56 ajacoutot Exp $
-
-r219009
-[ISel] Keep matching state consistent when folding during X86 address match
-
-In the X86 backend, matching an address is initiated by the 'addr' complex
-pattern and its friends.  During this process we may reassociate and-of-shift
-into shift-of-and (FoldMaskedShiftToScaledMask) to allow folding of the
-shift into the scale of the address.
-
-However as demonstrated by the testcase, this can trigger CSE of not only the
-shift and the AND which the code is prepared for but also the underlying load
-node.  In the testcase this node is sitting in the RecordedNode and MatchScope
-data structures of the matcher and becomes a deleted node upon CSE.  Returning
-from the complex pattern function, we try to access it again hitting an assert
-because the node is no longer a load even though this was checked before.
-
-Now obviously changing the DAG this late is bending the rules but I think it
-makes sense somewhat.  Outside of addresses we prefer and-of-shift because it
-may lead to smaller immediates (FoldMaskAndShiftToScale is an even better
-example because it create a non-canonical node).  We currently don't recognize
-addresses during DAGCombiner where arguably this canonicalization should be
-performed.  On the other hand, having this in the matcher allows us to cover
-all the cases where an address can be used in an instruction.
-
-I've also talked a little bit to Dan Gohman on llvm-dev who added the RAUW for
-the new shift node in FoldMaskedShiftToScaledMask.  This RAUW is responsible
-for initiating the recursive CSE on users
-(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-September/076903.html) but it
-is not strictly necessary since the shift is hooked into the visited user.  Of
-course it's safer to keep the DAG consistent at all times (e.g. for accurate
-number of uses, etc.).
-
-So rather than changing the fundamentals, I've decided to continue along the
-previous patches and detect the CSE.  This patch installs a very targeted
-DAGUpdateListener for the duration of a complex-pattern match and updates the
-matching state accordingly.  (Previous patches used HandleSDNode to detect the
-CSE but that's not practical here).  The listener is only installed on X86.
-
-I tested that there is no measurable overhead due to this while running
-through the spec2k BC files with llc.  The only thing we pay for is the
-creation of the listener.  The callback never ever triggers in spec2k since
-this is a corner case.
-
---- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp.orig Tue Aug  4 22:47:10 2015
-+++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug  4 22:52:46 2015
-@@ -2363,6 +2363,45 @@ struct MatchScope {
-   bool HasChainNodesMatched, HasGlueResultNodesMatched;
- };
-
-+/// \\brief A DAG update listener to keep the matching state
-+/// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
-+/// change the DAG while matching.  X86 addressing mode matcher is an example
-+/// for this.
-+class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
-+{
-+      SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
-+      SmallVectorImpl<MatchScope> &MatchScopes;
-+public:
-+  MatchStateUpdater(SelectionDAG &DAG,
-+                    SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
-+                    SmallVectorImpl<MatchScope> &MS) :
-+    SelectionDAG::DAGUpdateListener(DAG),
-+    RecordedNodes(RN), MatchScopes(MS) { }
-+
-+  void NodeDeleted(SDNode *N, SDNode *E) {
-+    // Some early-returns here to avoid the search if we deleted the node or
-+    // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
-+    // do, so it's unnecessary to update matching state at that point).
-+    // Neither of these can occur currently because we only install this
-+    // update listener during matching a complex patterns.
-+    if (!E || E->isMachineOpcode())
-+      return;
-+    // Performing linear search here does not matter because we almost never
-+    // run this code.  You'd have to have a CSE during complex pattern
-+    // matching.
-+    for (SmallVectorImpl<std::pair<SDValue, SDNode*> >::iterator I =
-+         RecordedNodes.begin(), IE = RecordedNodes.end(); I != IE; ++I)
-+      if (I->first.getNode() == N)
-+        I->first.setNode(E);
-+
-+    for (SmallVectorImpl<MatchScope>::iterator I = MatchScopes.begin(),
-+         IE = MatchScopes.end(); I != IE; ++I)
-+      for (SmallVector<SDValue, 4>::iterator J = I->NodeStack.begin(),
-+           JE = I->NodeStack.end(); J != JE; ++J)
-+        if (J->getNode() == N)
-+          J->setNode(E);
-+  }
-+};
- }
-
- SDNode *SelectionDAGISel::
-@@ -2617,6 +2656,14 @@ SelectCodeCommon(SDNode *NodeToMatch, const unsigned c
-       unsigned CPNum = MatcherTable[MatcherIndex++];
-       unsigned RecNo = MatcherTable[MatcherIndex++];
-       assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
-+
-+      // If target can modify DAG during matching, keep the matching state
-+      // consistent.
-+      OwningPtr<MatchStateUpdater> MSU;
-+      if (ComplexPatternFuncMutatesDAG())
-+        MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
-+                                        MatchScopes));
-+
-       if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
-                                RecordedNodes[RecNo].first, CPNum,
-                                RecordedNodes))
Index: patches/patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp
===================================================================
RCS file: patches/patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp
diff -N patches/patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp
--- patches/patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp 15 Nov 2014 03:26:40 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,49 +0,0 @@
-$OpenBSD: patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp,v 1.1 2014/11/15 03:26:40 brad Exp $
-
-r221709
-Totally forget deallocated SDNodes in SDDbgInfo.
-
-What would happen before that commit is that the SDDbgValues associated with
-a deallocated SDNode would be marked Invalidated, but SDDbgInfo would keep
-a map entry keyed by the SDNode pointer pointing to this list of invalidated
-SDDbgNodes. As the memory gets reused, the list might get wrongly associated
-with another new SDNode. As the SDDbgValues are cloned when they are transfered,
-this can lead to an exponential number of SDDbgValues being produced during
-DAGCombine like in http://llvm.org/bugs/show_bug.cgi?id=20893
-
-Note that the previous behavior wasn't really buggy as the invalidation made
-sure that the SDDbgValues won't be used. This commit can be considered a
-memory optimization and as such is really hard to validate in a unit-test.
-
---- lib/CodeGen/SelectionDAG/SelectionDAG.cpp.orig Fri Nov 14 21:02:43 2014
-+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Nov 14 21:08:05 2014
-@@ -642,6 +642,15 @@ void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) {
-   DeallocateNode(N);
- }
-
-+void SDDbgInfo::erase(const SDNode *Node) {
-+  DbgValMapType::iterator I = DbgValMap.find(Node);
-+  if (I == DbgValMap.end())
-+    return;
-+  for (unsigned J = 0, N = I->second.size(); J != N; ++J)
-+    I->second[J]->setIsInvalidated();
-+  DbgValMap.erase(I);
-+}
-+
- void SelectionDAG::DeallocateNode(SDNode *N) {
-   if (N->OperandsNeedDelete)
-     delete[] N->OperandList;
-@@ -652,10 +661,9 @@ void SelectionDAG::DeallocateNode(SDNode *N) {
-
-   NodeAllocator.Deallocate(AllNodes.remove(N));
-
--  // If any of the SDDbgValue nodes refer to this SDNode, invalidate them.
--  ArrayRef<SDDbgValue*> DbgVals = DbgInfo->getSDDbgValues(N);
--  for (unsigned i = 0, e = DbgVals.size(); i != e; ++i)
--    DbgVals[i]->setIsInvalidated();
-+  // If any of the SDDbgValue nodes refer to this SDNode, invalidate
-+  // them and forget about that node.
-+  DbgInfo->erase(N);
- }
-
- /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
Index: patches/patch-lib_CodeGen_StackProtector_cpp
===================================================================
RCS file: patches/patch-lib_CodeGen_StackProtector_cpp
diff -N patches/patch-lib_CodeGen_StackProtector_cpp
--- patches/patch-lib_CodeGen_StackProtector_cpp 17 May 2014 11:41:15 -0000 1.5
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,25 +0,0 @@
-$OpenBSD: patch-lib_CodeGen_StackProtector_cpp,v 1.5 2014/05/17 11:41:15 brad Exp $
-
-r206486
-Make the StackProtector pass respect ssp-buffer-size.
-
---- lib/CodeGen/StackProtector.cpp.orig Fri Apr 18 17:19:15 2014
-+++ lib/CodeGen/StackProtector.cpp Fri Apr 18 17:20:13 2014
-@@ -86,14 +86,14 @@ bool StackProtector::runOnFunction(Function &Fn) {
-   DT = DTWP ? &DTWP->getDomTree() : 0;
-   TLI = TM->getTargetLowering();
-
--  if (!RequiresStackProtector())
--    return false;
--
-   Attribute Attr = Fn.getAttributes().getAttribute(
-       AttributeSet::FunctionIndex, "stack-protector-buffer-size");
-   if (Attr.isStringAttribute() &&
-       Attr.getValueAsString().getAsInteger(10, SSPBufferSize))
-       return false; // Invalid integer string
-+
-+  if (!RequiresStackProtector())
-+    return false;
-
-   ++NumFunProtected;
-   return InsertStackProtectors();
Index: patches/patch-lib_CodeGen_TargetInstrInfo_cpp
===================================================================
RCS file: patches/patch-lib_CodeGen_TargetInstrInfo_cpp
diff -N patches/patch-lib_CodeGen_TargetInstrInfo_cpp
--- patches/patch-lib_CodeGen_TargetInstrInfo_cpp 18 Sep 2014 20:19:27 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,30 +0,0 @@
-$OpenBSD: patch-lib_CodeGen_TargetInstrInfo_cpp,v 1.1 2014/09/18 20:19:27 brad Exp $
-
-r217801
-Fix a lot of confusion around inserting nops on empty functions.
-
-On MachO, and MachO only, we cannot have a truly empty function since that
-breaks the linker logic for atomizing the section.
-
-When we are emitting a frame pointer, the presence of an unreachable will
-create a cfi instruction pointing past the last instruction. This is perfectly
-fine. The FDE information encodes the pc range it applies to. If some tool
-cannot handle this, we should explicitly say which bug we are working around
-and only work around it when it is actually relevant (not for ELF for example).
-
-Given the unreachable we could omit the .cfi_def_cfa_register, but then
-again, we could also omit the entire function prologue if we wanted to.
-
---- lib/CodeGen/TargetInstrInfo.cpp.orig Mon Sep 15 16:04:07 2014
-+++ lib/CodeGen/TargetInstrInfo.cpp Mon Sep 15 16:04:33 2014
-@@ -368,6 +368,10 @@ static const TargetRegisterClass *canFoldCopy(const Ma
-   return 0;
- }
-
-+void TargetInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
-+  llvm_unreachable("Not a MachO target");
-+}
-+
- bool TargetInstrInfo::
- canFoldMemoryOperand(const MachineInstr *MI,
-                      const SmallVectorImpl<unsigned> &Ops) const {
Index: patches/patch-lib_MC_MCObjectFileInfo_cpp
===================================================================
RCS file: patches/patch-lib_MC_MCObjectFileInfo_cpp
diff -N patches/patch-lib_MC_MCObjectFileInfo_cpp
--- patches/patch-lib_MC_MCObjectFileInfo_cpp 30 Dec 2014 05:23:32 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,16 +0,0 @@
-$OpenBSD: patch-lib_MC_MCObjectFileInfo_cpp,v 1.1 2014/12/30 05:23:32 brad Exp $
-
-r213890
-Use the same .eh_frame encoding for 32bit PPC as on i386.
-
---- lib/MC/MCObjectFileInfo.cpp.orig Tue Dec 30 00:10:03 2014
-+++ lib/MC/MCObjectFileInfo.cpp Tue Dec 30 00:19:28 2014
-@@ -248,7 +248,7 @@ void MCObjectFileInfo::InitELFMCObjectFileInfo(Triple
-   else
-     FDECFIEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
-
--  if (T.getArch() == Triple::x86) {
-+  if (T.getArch() == Triple::ppc || T.getArch() == Triple::x86) {
-     PersonalityEncoding = (RelocM == Reloc::PIC_)
-      ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
-      : dwarf::DW_EH_PE_absptr;
Index: patches/patch-lib_MC_MCParser_AsmParser_cpp
===================================================================
RCS file: patches/patch-lib_MC_MCParser_AsmParser_cpp
diff -N patches/patch-lib_MC_MCParser_AsmParser_cpp
--- patches/patch-lib_MC_MCParser_AsmParser_cpp 4 Jun 2015 05:58:43 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,44 +0,0 @@
-$OpenBSD: patch-lib_MC_MCParser_AsmParser_cpp,v 1.1 2015/06/04 05:58:43 ajacoutot Exp $
-
-r229911
-MC: Allow multiple comma-separated expressions on the .uleb128 directive.
-
---- lib/MC/MCParser/AsmParser.cpp.orig Thu Jun  4 00:34:57 2015
-+++ lib/MC/MCParser/AsmParser.cpp Thu Jun  4 00:40:09 2015
-@@ -3574,21 +3574,27 @@ bool AsmParser::parseDirectiveSpace(StringRef IDVal) {
- }
-
- /// parseDirectiveLEB128
--/// ::= (.sleb128 | .uleb128) expression
-+/// ::= (.sleb128 | .uleb128) [ expression (, expression)* ]
- bool AsmParser::parseDirectiveLEB128(bool Signed) {
-   checkForValidSection();
-   const MCExpr *Value;
-
--  if (parseExpression(Value))
--    return true;
-+  for (;;) {
-+    if (parseExpression(Value))
-+      return true;
-
--  if (getLexer().isNot(AsmToken::EndOfStatement))
--    return TokError("unexpected token in directive");
-+    if (Signed)
-+      getStreamer().EmitSLEB128Value(Value);
-+    else
-+      getStreamer().EmitULEB128Value(Value);
-
--  if (Signed)
--    getStreamer().EmitSLEB128Value(Value);
--  else
--    getStreamer().EmitULEB128Value(Value);
-+    if (getLexer().is(AsmToken::EndOfStatement))
-+      break;
-+
-+    if (getLexer().isNot(AsmToken::Comma))
-+      return TokError("unexpected token in directive");
-+    Lex();
-+  }
-
-   return false;
- }
Index: patches/patch-lib_Object_ELF_cpp
===================================================================
RCS file: patches/patch-lib_Object_ELF_cpp
diff -N patches/patch-lib_Object_ELF_cpp
--- patches/patch-lib_Object_ELF_cpp 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,19 +0,0 @@
-$OpenBSD: patch-lib_Object_ELF_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- lib/Object/ELF.cpp.orig Sun Jul 27 00:02:32 2014
-+++ lib/Object/ELF.cpp Sun Jul 27 00:02:56 2014
-@@ -509,6 +509,7 @@ StringRef getELFRelocationTypeName(uint32_t Machine, u
-       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_LO);
-       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_HI);
-       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_HA);
-+      LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_PLTREL24);
-       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL32);
-       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_TLS);
-       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_DTPMOD32);
Index: patches/patch-lib_Support_regcomp_c
===================================================================
RCS file: patches/patch-lib_Support_regcomp_c
diff -N patches/patch-lib_Support_regcomp_c
--- patches/patch-lib_Support_regcomp_c 11 Feb 2015 00:29:05 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,57 +0,0 @@
-$OpenBSD: patch-lib_Support_regcomp_c,v 1.1 2015/02/11 00:29:05 brad Exp $
-
-r228507
-Avoid integer overflows around realloc calls resulting in potential
-heap. Problem identified by Guido Vranken.
-
---- lib/Support/regcomp.c.orig Mon Feb  9 17:08:17 2015
-+++ lib/Support/regcomp.c Mon Feb  9 17:10:41 2015
-@@ -49,6 +49,14 @@
- #include "regcclass.h"
- #include "regcname.h"
-
-+#include "llvm/Config/config.h"
-+#if HAVE_STDINT_H
-+#include <stdint.h>
-+#else
-+/* Pessimistically bound memory use */
-+#define SIZE_MAX UINT_MAX
-+#endif
-+
- /*
-  * parse structure, passed up and down to avoid global variables and
-  * other clumsinesses
-@@ -1069,6 +1077,8 @@ allocset(struct parse *p)
-
- p->ncsalloc += CHAR_BIT;
- nc = p->ncsalloc;
-+ if (nc > SIZE_MAX / sizeof(cset))
-+ goto nomem;
- assert(nc % CHAR_BIT == 0);
- nbytes = nc / CHAR_BIT * css;
-
-@@ -1412,6 +1422,11 @@ enlarge(struct parse *p, sopno size)
- if (p->ssize >= size)
- return;
-
-+ if ((unsigned long)size > SIZE_MAX / sizeof(sop)) {
-+ SETERROR(REG_ESPACE);
-+ return;
-+ }
-+
- sp = (sop *)realloc(p->strip, size*sizeof(sop));
- if (sp == NULL) {
- SETERROR(REG_ESPACE);
-@@ -1428,6 +1443,12 @@ static void
- stripsnug(struct parse *p, struct re_guts *g)
- {
- g->nstates = p->slen;
-+ if ((unsigned long)p->slen > SIZE_MAX / sizeof(sop)) {
-+ g->strip = p->strip;
-+ SETERROR(REG_ESPACE);
-+ return;
-+ }
-+
- g->strip = (sop *)realloc((char *)p->strip, p->slen * sizeof(sop));
- if (g->strip == NULL) {
- SETERROR(REG_ESPACE);
Index: patches/patch-lib_Target_ARM_A15SDOptimizer_cpp
===================================================================
RCS file: patches/patch-lib_Target_ARM_A15SDOptimizer_cpp
diff -N patches/patch-lib_Target_ARM_A15SDOptimizer_cpp
--- patches/patch-lib_Target_ARM_A15SDOptimizer_cpp 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,40 +0,0 @@
-$OpenBSD: patch-lib_Target_ARM_A15SDOptimizer_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r204304
-Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR.
-
---- lib/Target/ARM/A15SDOptimizer.cpp.orig Sun Mar  2 21:57:40 2014
-+++ lib/Target/ARM/A15SDOptimizer.cpp Sat Jun 14 04:09:54 2014
-@@ -416,7 +416,8 @@ SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(M
-     if (!MO.isReg() || !MO.isUse())
-       continue;
-     if (!usesRegClass(MO, &ARM::DPRRegClass) &&
--        !usesRegClass(MO, &ARM::QPRRegClass))
-+        !usesRegClass(MO, &ARM::QPRRegClass) &&
-+        !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
-       continue;
-
-     Defs.push_back(MO.getReg());
-@@ -536,7 +537,10 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *
-   InsertPt++;
-   unsigned Out;
-
--  if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) {
-+  // DPair has the same length as QPR and also has two DPRs as subreg.
-+  // Treat DPair as QPR.
-+  if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
-+      MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
-     unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
-                                          ARM::dsub_0, &ARM::DPRRegClass);
-     unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
-@@ -569,7 +573,9 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *
-       default: llvm_unreachable("Unknown preferred lane!");
-     }
-
--    bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass);
-+    // Treat DPair as QPR
-+    bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
-+                   usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
-
-     Out = createImplicitDef(MBB, InsertPt, DL);
-     Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
Index: patches/patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp
diff -N patches/patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp
--- patches/patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp 28 Dec 2014 00:30:17 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,16 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp,v 1.1 2014/12/28 00:30:17 brad Exp $
-
-r203699
-Allow exclamation and tilde to be parsed as a part of the ppc asm operand.
-
---- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp.orig Fri Dec 26 14:50:10 2014
-+++ lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Fri Dec 26 14:50:56 2014
-@@ -1205,6 +1205,8 @@ ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
-   case AsmToken::Integer:
-   case AsmToken::Dot:
-   case AsmToken::Dollar:
-+  case AsmToken::Exclaim:
-+  case AsmToken::Tilde:
-     if (!ParseExpression(EVal))
-       break;
-     /* fall through */
Index: patches/patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp
diff -N patches/patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp
--- patches/patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,33 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213960
-[PowerPC] Support TLS on PPC32/ELF
-
---- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp.orig Sun Jul 27 03:53:55 2014
-+++ lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Sun Jul 27 03:56:03 2014
-@@ -18,6 +18,7 @@
- #include "llvm/MC/MCExpr.h"
- #include "llvm/MC/MCInst.h"
- #include "llvm/MC/MCInstrInfo.h"
-+#include "llvm/MC/MCSymbol.h"
- #include "llvm/Support/CommandLine.h"
- #include "llvm/Support/raw_ostream.h"
- #include "llvm/Target/TargetOpcodes.h"
-@@ -300,10 +301,16 @@ void PPCInstPrinter::printMemRegReg(const MCInst *MI,
-
- void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
-                                   raw_ostream &O) {
--  printBranchOperand(MI, OpNo, O);
-+  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
-+  // come at the _end_ of the expression.
-+  const MCOperand &Op = MI->getOperand(OpNo);
-+  const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
-+  O << refExp.getSymbol().getName();
-   O << '(';
-   printOperand(MI, OpNo+1, O);
-   O << ')';
-+  if (refExp.getKind() != MCSymbolRefExpr::VK_None)
-+    O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
- }
-
-
Index: patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp
diff -N patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp
--- patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,81 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
-r213960
-[PowerPC] Support TLS on PPC32/ELF
-
---- lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Sun Jul 27 04:00:37 2014
-@@ -64,7 +64,15 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const M
-       llvm_unreachable("Unimplemented");
-     case PPC::fixup_ppc_br24:
-     case PPC::fixup_ppc_br24abs:
--      Type = ELF::R_PPC_REL24;
-+      switch (Modifier) {
-+      default: llvm_unreachable("Unsupported Modifier");
-+      case MCSymbolRefExpr::VK_None:
-+        Type = ELF::R_PPC_REL24;
-+        break;
-+      case MCSymbolRefExpr::VK_PLT:
-+        Type = ELF::R_PPC_PLTREL24;
-+        break;
-+      }
-       break;
-     case PPC::fixup_ppc_brcond14:
-     case PPC::fixup_ppc_brcond14abs:
-@@ -205,7 +213,10 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const M
-         Type = ELF::R_PPC64_DTPREL16_HIGHESTA;
-         break;
-       case MCSymbolRefExpr::VK_PPC_GOT_TLSGD:
--        Type = ELF::R_PPC64_GOT_TLSGD16;
-+        if (is64Bit())
-+          Type = ELF::R_PPC64_GOT_TLSGD16;
-+        else
-+          Type = ELF::R_PPC_GOT_TLSGD16;
-         break;
-       case MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO:
-         Type = ELF::R_PPC64_GOT_TLSGD16_LO;
-@@ -217,7 +228,10 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const M
-         Type = ELF::R_PPC64_GOT_TLSGD16_HA;
-         break;
-       case MCSymbolRefExpr::VK_PPC_GOT_TLSLD:
--        Type = ELF::R_PPC64_GOT_TLSLD16;
-+        if (is64Bit())
-+          Type = ELF::R_PPC64_GOT_TLSLD16;
-+        else
-+          Type = ELF::R_PPC_GOT_TLSLD16;
-         break;
-       case MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO:
-         Type = ELF::R_PPC64_GOT_TLSLD16_LO;
-@@ -313,13 +327,22 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const M
-       switch (Modifier) {
-       default: llvm_unreachable("Unsupported Modifier");
-       case MCSymbolRefExpr::VK_PPC_TLSGD:
--        Type = ELF::R_PPC64_TLSGD;
-+        if (is64Bit())
-+          Type = ELF::R_PPC64_TLSGD;
-+        else
-+          Type = ELF::R_PPC_TLSGD;
-         break;
-       case MCSymbolRefExpr::VK_PPC_TLSLD:
--        Type = ELF::R_PPC64_TLSLD;
-+        if (is64Bit())
-+          Type = ELF::R_PPC64_TLSLD;
-+        else
-+          Type = ELF::R_PPC_TLSLD;
-         break;
-       case MCSymbolRefExpr::VK_PPC_TLS:
--        Type = ELF::R_PPC64_TLS;
-+        if (is64Bit())
-+          Type = ELF::R_PPC64_TLS;
-+        else
-+          Type = ELF::R_PPC_TLS;
-         break;
-       }
-       break;
Index: patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp
diff -N patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp
--- patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp 11 Feb 2015 00:29:05 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,17 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp,v 1.2 2015/02/11 00:29:05 brad Exp $
-
-r225819
-Use the integrated assembler as default on PowerPC
-
---- lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp Mon Feb  2 11:12:15 2015
-@@ -74,8 +74,6 @@ PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit, con
-   Data64bitsDirective = is64Bit ? "\t.quad\t" : 0;
-   AssemblerDialect = 1;           // New-Style mnemonics.
-
--  if (T.getOS() == llvm::Triple::FreeBSD ||
--      (T.getOS() == llvm::Triple::NetBSD && !is64Bit))
--    UseIntegratedAssembler = true;
-+  UseIntegratedAssembler = true;
- }
-
Index: patches/patch-lib_Target_PowerPC_PPCAsmPrinter_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCAsmPrinter_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCAsmPrinter_cpp
--- patches/patch-lib_Target_PowerPC_PPCAsmPrinter_cpp 28 Dec 2014 00:30:18 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,487 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCAsmPrinter_cpp,v 1.2 2014/12/28 00:30:18 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
-r213960
-[PowerPC] Support TLS on PPC32/ELF
-
-r209821
-[PPC] Use alias symbols in address computation.
-
-This seems to match what gcc does for ppc and what every other llvm
-backend does.
-
---- lib/Target/PowerPC/PPCAsmPrinter.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Dec 26 15:31:43 2014
-@@ -19,6 +19,7 @@
- #define DEBUG_TYPE "asmprinter"
- #include "PPC.h"
- #include "InstPrinter/PPCInstPrinter.h"
-+#include "PPCMachineFunctionInfo.h"
- #include "MCTargetDesc/PPCMCExpr.h"
- #include "MCTargetDesc/PPCPredicates.h"
- #include "PPCSubtarget.h"
-@@ -28,6 +29,7 @@
- #include "llvm/ADT/SmallString.h"
- #include "llvm/ADT/StringExtras.h"
- #include "llvm/CodeGen/AsmPrinter.h"
-+#include "llvm/CodeGen/MachineConstantPool.h"
- #include "llvm/CodeGen/MachineFunctionPass.h"
- #include "llvm/CodeGen/MachineInstr.h"
- #include "llvm/CodeGen/MachineInstrBuilder.h"
-@@ -99,6 +101,7 @@ namespace {
-     }
-
-     bool doFinalization(Module &M);
-+    void EmitStartOfAsmFile(Module &M);
-
-     virtual void EmitFunctionEntryLabel();
-
-@@ -326,6 +329,66 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
-     OutStreamer.EmitLabel(PICBase);
-     return;
-   }
-+  case PPC::GetGBRO: {
-+    // Get the offset from the GOT Base Register to the GOT
-+    LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
-+    MCSymbol *PICOffset = MF->getInfo<PPCFunctionInfo>()->getPICOffsetSymbol();
-+    TmpInst.setOpcode(PPC::LWZ);
-+    const MCExpr *Exp =
-+      MCSymbolRefExpr::Create(PICOffset, MCSymbolRefExpr::VK_None, OutContext);
-+    const MCExpr *PB =
-+      MCSymbolRefExpr::Create(MF->getPICBaseSymbol(),
-+                              MCSymbolRefExpr::VK_None,
-+                              OutContext);
-+    const MCOperand MO = TmpInst.getOperand(1);
-+    TmpInst.getOperand(1) = MCOperand::CreateExpr(MCBinaryExpr::CreateSub(Exp,
-+                                                                          PB,
-+                                                                          OutContext));
-+    TmpInst.addOperand(MO);
-+    EmitToStreamer(OutStreamer, TmpInst);
-+    return;
-+  }
-+  case PPC::UpdateGBR: {
-+    // Update the GOT Base Register to point to the GOT. It may be possible to
-+    // merge this with the PPC::GetGBRO, doing it all in one step.
-+    LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
-+    TmpInst.setOpcode(PPC::ADD4);
-+    TmpInst.addOperand(TmpInst.getOperand(0));
-+    EmitToStreamer(OutStreamer, TmpInst);
-+    return;
-+  }
-+  case PPC::LWZtoc: {
-+    // Transform %X3 = LWZtoc <ga:@min1>, %X2
-+    LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
-+
-+    // Change the opcode to LWZ, and the global address operand to be a
-+    // reference to the GOT entry we will synthesize later.
-+    TmpInst.setOpcode(PPC::LWZ);
-+    const MachineOperand &MO = MI->getOperand(1);
-+
-+    // Map symbol -> label of TOC entry
-+    assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
-+    MCSymbol *MOSymbol = 0;
-+    if (MO.isGlobal())
-+      MOSymbol = getSymbol(MO.getGlobal());
-+    else if (MO.isCPI())
-+      MOSymbol = GetCPISymbol(MO.getIndex());
-+    else if (MO.isJTI())
-+      MOSymbol = GetJTISymbol(MO.getIndex());
-+
-+    MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol);
-+
-+    const MCExpr *Exp =
-+      MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_None,
-+                              OutContext);
-+    const MCExpr *PB =
-+      MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")),
-+                                                           OutContext);
-+    Exp = MCBinaryExpr::CreateSub(Exp, PB, OutContext);
-+    TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
-+    EmitToStreamer(OutStreamer, TmpInst);
-+    return;
-+  }
-   case PPC::LDtocJTI:
-   case PPC::LDtocCPT:
-   case PPC::LDtoc: {
-@@ -376,16 +439,12 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
-     bool IsAvailExt = false;
-
-     if (MO.isGlobal()) {
--      const GlobalValue *GValue = MO.getGlobal();
--      const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
--      const GlobalValue *RealGValue = GAlias ?
--        GAlias->resolveAliasedGlobal(false) : GValue;
--      MOSymbol = getSymbol(RealGValue);
--      const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
--      IsExternal = GVar && !GVar->hasInitializer();
--      IsCommon = GVar && RealGValue->hasCommonLinkage();
--      IsFunction = !GVar;
--      IsAvailExt = GVar && RealGValue->hasAvailableExternallyLinkage();
-+      const GlobalValue *GV = MO.getGlobal();
-+      MOSymbol = getSymbol(GV);
-+      IsExternal = GV->isDeclaration();
-+      IsCommon = GV->hasCommonLinkage();
-+      IsFunction = GV->getType()->getElementType()->isFunctionTy();
-+      IsAvailExt = GV->hasAvailableExternallyLinkage();
-     } else if (MO.isCPI())
-       MOSymbol = GetCPISymbol(MO.getIndex());
-     else if (MO.isJTI())
-@@ -424,14 +483,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
-     }
-     else if (MO.isGlobal()) {
-       const GlobalValue *GValue = MO.getGlobal();
--      const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
--      const GlobalValue *RealGValue = GAlias ?
--        GAlias->resolveAliasedGlobal(false) : GValue;
--      MOSymbol = getSymbol(RealGValue);
--      const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
--    
--      if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() ||
--          RealGValue->hasAvailableExternallyLinkage() ||
-+      MOSymbol = getSymbol(GValue);
-+      if (GValue->getType()->getElementType()->isFunctionTy() ||
-+          GValue->isDeclaration() || GValue->hasCommonLinkage() ||
-+          GValue->hasAvailableExternallyLinkage() ||
-           TM.getCodeModel() == CodeModel::Large)
-         MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
-     }
-@@ -458,14 +513,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
-     bool IsFunction = false;
-
-     if (MO.isGlobal()) {
--      const GlobalValue *GValue = MO.getGlobal();
--      const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
--      const GlobalValue *RealGValue = GAlias ?
--        GAlias->resolveAliasedGlobal(false) : GValue;
--      MOSymbol = getSymbol(RealGValue);
--      const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
--      IsExternal = GVar && !GVar->hasInitializer();
--      IsFunction = !GVar;
-+      const GlobalValue *GV = MO.getGlobal();
-+      MOSymbol = getSymbol(GV);
-+      IsExternal = GV->isDeclaration();
-+      IsFunction = GV->getType()->getElementType()->isFunctionTy();
-     } else if (MO.isCPI())
-       MOSymbol = GetCPISymbol(MO.getIndex());
-
-@@ -513,6 +564,34 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
-     return;
-   }
-
-+  case PPC::PPC32PICGOT: {
-+    MCSymbol *GOTSymbol = OutContext.GetOrCreateSymbol(StringRef("_GLOBAL_OFFSET_TABLE_"));
-+    MCSymbol *GOTRef = OutContext.CreateTempSymbol();
-+    MCSymbol *NextInstr = OutContext.CreateTempSymbol();
-+
-+    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL)
-+      // FIXME: We would like an efficient form for this, so we don't have to do
-+      // a lot of extra uniquing.
-+      .addExpr(MCSymbolRefExpr::Create(NextInstr, OutContext)));
-+    const MCExpr *OffsExpr =
-+      MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(GOTSymbol, OutContext),
-+                                MCSymbolRefExpr::Create(GOTRef, OutContext),
-+        OutContext);
-+    OutStreamer.EmitLabel(GOTRef);
-+    OutStreamer.EmitValue(OffsExpr, 4);
-+    OutStreamer.EmitLabel(NextInstr);
-+    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MFLR)
-+                                .addReg(MI->getOperand(0).getReg()));
-+    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::LWZ)
-+                                .addReg(MI->getOperand(1).getReg())
-+                                .addImm(0)
-+                                .addReg(MI->getOperand(0).getReg()));
-+    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADD4)
-+                                .addReg(MI->getOperand(0).getReg())
-+                                .addReg(MI->getOperand(1).getReg())
-+                                .addReg(MI->getOperand(0).getReg()));
-+    return;
-+  }
-   case PPC::PPC32GOT: {
-     MCSymbol *GOTSymbol = OutContext.GetOrCreateSymbol(StringRef("_GLOBAL_OFFSET_TABLE_"));
-     const MCExpr *SymGotTlsL =
-@@ -546,40 +625,54 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
-                                 .addExpr(SymGotTlsGD));
-     return;
-   }
--  case PPC::ADDItlsgdL: {
-+  case PPC::ADDItlsgdL:
-     // Transform: %Xd = ADDItlsgdL %Xs, <ga:@sym>
-     // Into:      %Xd = ADDI8 %Xs, sym@got@tlsgd@l
--    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
-+  case PPC::ADDItlsgdL32: {
-+    // Transform: %Rd = ADDItlsgdL32 %Rs, <ga:@sym>
-+    // Into:      %Rd = ADDI %Rs, sym@got@tlsgd
-     const MachineOperand &MO = MI->getOperand(2);
-     const GlobalValue *GValue = MO.getGlobal();
-     MCSymbol *MOSymbol = getSymbol(GValue);
-     const MCExpr *SymGotTlsGD =
--      MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO,
-+      MCSymbolRefExpr::Create(MOSymbol, Subtarget.isPPC64() ?
-+                                         MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO :
-+                                         MCSymbolRefExpr::VK_PPC_GOT_TLSGD,
-                               OutContext);
--    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8)
--                                .addReg(MI->getOperand(0).getReg())
--                                .addReg(MI->getOperand(1).getReg())
--                                .addExpr(SymGotTlsGD));
-+    EmitToStreamer(OutStreamer,
-+                   MCInstBuilder(Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI)
-+                   .addReg(MI->getOperand(0).getReg())
-+                   .addReg(MI->getOperand(1).getReg())
-+                   .addExpr(SymGotTlsGD));
-     return;
-   }
--  case PPC::GETtlsADDR: {
-+  case PPC::GETtlsADDR:
-     // Transform: %X3 = GETtlsADDR %X3, <ga:@sym>
-     // Into:      BL8_NOP_TLS __tls_get_addr(sym@tlsgd)
--    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
-+  case PPC::GETtlsADDR32: {
-+    // Transform: %R3 = GETtlsADDR32 %R3, <ga:@sym>
-+    // Into:      BL_TLS __tls_get_addr(sym@tlsgd)@PLT
-
-     StringRef Name = "__tls_get_addr";
-     MCSymbol *TlsGetAddr = OutContext.GetOrCreateSymbol(Name);
-+    MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
-+
-+    if (!Subtarget.isPPC64() && !Subtarget.isDarwin() &&
-+        TM.getRelocationModel() == Reloc::PIC_)
-+      Kind = MCSymbolRefExpr::VK_PLT;
-     const MCSymbolRefExpr *TlsRef =
--      MCSymbolRefExpr::Create(TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
-+      MCSymbolRefExpr::Create(TlsGetAddr, Kind, OutContext);
-     const MachineOperand &MO = MI->getOperand(2);
-     const GlobalValue *GValue = MO.getGlobal();
-     MCSymbol *MOSymbol = getSymbol(GValue);
-     const MCExpr *SymVar =
-       MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSGD,
-                               OutContext);
--    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL8_NOP_TLS)
--                                .addExpr(TlsRef)
--                                .addExpr(SymVar));
-+    EmitToStreamer(OutStreamer,
-+                   MCInstBuilder(Subtarget.isPPC64() ?
-+                                  PPC::BL8_NOP_TLS : PPC::BL_TLS)
-+                   .addExpr(TlsRef)
-+                   .addExpr(SymVar));
-     return;
-   }
-   case PPC::ADDIStlsldHA: {
-@@ -598,72 +691,93 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
-                                 .addExpr(SymGotTlsLD));
-     return;
-   }
--  case PPC::ADDItlsldL: {
-+  case PPC::ADDItlsldL:
-     // Transform: %Xd = ADDItlsldL %Xs, <ga:@sym>
-     // Into:      %Xd = ADDI8 %Xs, sym@got@tlsld@l
--    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
-+  case PPC::ADDItlsldL32: {
-+    // Transform: %Rd = ADDItlsldL32 %Rs, <ga:@sym>
-+    // Into:      %Rd = ADDI %Rs, sym@got@tlsld
-     const MachineOperand &MO = MI->getOperand(2);
-     const GlobalValue *GValue = MO.getGlobal();
-     MCSymbol *MOSymbol = getSymbol(GValue);
-     const MCExpr *SymGotTlsLD =
--      MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO,
-+      MCSymbolRefExpr::Create(MOSymbol, Subtarget.isPPC64() ?
-+                                         MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO :
-+                                         MCSymbolRefExpr::VK_PPC_GOT_TLSLD,
-                               OutContext);
--    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8)
--                                .addReg(MI->getOperand(0).getReg())
--                                .addReg(MI->getOperand(1).getReg())
--                                .addExpr(SymGotTlsLD));
-+    EmitToStreamer(OutStreamer,
-+                   MCInstBuilder(Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI)
-+                   .addReg(MI->getOperand(0).getReg())
-+                   .addReg(MI->getOperand(1).getReg())
-+                   .addExpr(SymGotTlsLD));
-     return;
-   }
--  case PPC::GETtlsldADDR: {
-+  case PPC::GETtlsldADDR:
-     // Transform: %X3 = GETtlsldADDR %X3, <ga:@sym>
-     // Into:      BL8_NOP_TLS __tls_get_addr(sym@tlsld)
--    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
-+  case PPC::GETtlsldADDR32: {
-+    // Transform: %R3 = GETtlsldADDR32 %R3, <ga:@sym>
-+    // Into:      BL_TLS __tls_get_addr(sym@tlsld)@PLT
-
-     StringRef Name = "__tls_get_addr";
-     MCSymbol *TlsGetAddr = OutContext.GetOrCreateSymbol(Name);
-+    MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
-+
-+    if (!Subtarget.isPPC64() && !Subtarget.isDarwin() &&
-+        TM.getRelocationModel() == Reloc::PIC_)
-+      Kind = MCSymbolRefExpr::VK_PLT;
-+
-     const MCSymbolRefExpr *TlsRef =
--      MCSymbolRefExpr::Create(TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
-+      MCSymbolRefExpr::Create(TlsGetAddr, Kind, OutContext);
-     const MachineOperand &MO = MI->getOperand(2);
-     const GlobalValue *GValue = MO.getGlobal();
-     MCSymbol *MOSymbol = getSymbol(GValue);
-     const MCExpr *SymVar =
-       MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSLD,
-                               OutContext);
--    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL8_NOP_TLS)
--                                .addExpr(TlsRef)
--                                .addExpr(SymVar));
-+    EmitToStreamer(OutStreamer,
-+                   MCInstBuilder(Subtarget.isPPC64() ?
-+                                  PPC::BL8_NOP_TLS : PPC::BL_TLS)
-+                   .addExpr(TlsRef)
-+                   .addExpr(SymVar));
-     return;
-   }
--  case PPC::ADDISdtprelHA: {
-+  case PPC::ADDISdtprelHA:
-     // Transform: %Xd = ADDISdtprelHA %X3, <ga:@sym>
-     // Into:      %Xd = ADDIS8 %X3, sym@dtprel@ha
--    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
-+  case PPC::ADDISdtprelHA32: {
-+    // Transform: %Rd = ADDISdtprelHA32 %R3, <ga:@sym>
-+    // Into:      %Rd = ADDIS %R3, sym@dtprel@ha
-     const MachineOperand &MO = MI->getOperand(2);
-     const GlobalValue *GValue = MO.getGlobal();
-     MCSymbol *MOSymbol = getSymbol(GValue);
-     const MCExpr *SymDtprel =
-       MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_HA,
-                               OutContext);
--    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8)
--                                .addReg(MI->getOperand(0).getReg())
--                                .addReg(PPC::X3)
--                                .addExpr(SymDtprel));
-+    EmitToStreamer(OutStreamer,
-+                   MCInstBuilder(Subtarget.isPPC64() ? PPC::ADDIS8 : PPC::ADDIS)
-+                   .addReg(MI->getOperand(0).getReg())
-+                   .addReg(Subtarget.isPPC64() ? PPC::X3 : PPC::R3)
-+                   .addExpr(SymDtprel));
-     return;
-   }
--  case PPC::ADDIdtprelL: {
-+  case PPC::ADDIdtprelL:
-     // Transform: %Xd = ADDIdtprelL %Xs, <ga:@sym>
-     // Into:      %Xd = ADDI8 %Xs, sym@dtprel@l
--    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
-+  case PPC::ADDIdtprelL32: {
-+    // Transform: %Rd = ADDIdtprelL32 %Rs, <ga:@sym>
-+    // Into:      %Rd = ADDI %Rs, sym@dtprel@l
-     const MachineOperand &MO = MI->getOperand(2);
-     const GlobalValue *GValue = MO.getGlobal();
-     MCSymbol *MOSymbol = getSymbol(GValue);
-     const MCExpr *SymDtprel =
-       MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_LO,
-                               OutContext);
--    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8)
--                                .addReg(MI->getOperand(0).getReg())
--                                .addReg(MI->getOperand(1).getReg())
--                                .addExpr(SymDtprel));
-+    EmitToStreamer(OutStreamer,
-+                   MCInstBuilder(Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI)
-+                   .addReg(MI->getOperand(0).getReg())
-+                   .addReg(MI->getOperand(1).getReg())
-+                   .addExpr(SymDtprel));
-     return;
-   }
-   case PPC::MFOCRF:
-@@ -722,9 +836,60 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
-   EmitToStreamer(OutStreamer, TmpInst);
- }
-
-+void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module &M) {
-+  if (Subtarget.isPPC64() || TM.getRelocationModel() != Reloc::PIC_)
-+    return AsmPrinter::EmitStartOfAsmFile(M);
-+
-+  // FIXME: The use of .got2 assumes large GOT model (-fPIC), which is not
-+  // optimal for some cases. We should consider supporting small model (-fpic)
-+  // as well in the future.
-+  assert(TM.getCodeModel() != CodeModel::Small &&
-+         "Small code model PIC is currently unsupported.");
-+  OutStreamer.SwitchSection(OutContext.getELFSection(".got2",
-+         ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,
-+         SectionKind::getReadOnly()));
-+
-+  MCSymbol *TOCSym = OutContext.GetOrCreateSymbol(Twine(".L.TOC."));
-+  MCSymbol *CurrentPos = OutContext.CreateTempSymbol();
-+
-+  OutStreamer.EmitLabel(CurrentPos);
-+
-+  // The GOT pointer points to the middle of the GOT, in order to reference the
-+  // entire 64kB range. 0x8000 is the midpoint.
-+  const MCExpr *tocExpr =
-+    MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(CurrentPos, OutContext),
-+                            MCConstantExpr::Create(0x8000, OutContext),
-+                            OutContext);
-+
-+  OutStreamer.EmitAssignment(TOCSym, tocExpr);
-+
-+  OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
-+}
-+
- void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() {
--  if (!Subtarget.isPPC64())  // linux/ppc32 - Normal entry label.
-+  // linux/ppc32 - Normal entry label.
-+  if (!Subtarget.isPPC64() && TM.getRelocationModel() != Reloc::PIC_)
-     return AsmPrinter::EmitFunctionEntryLabel();
-+
-+  if (!Subtarget.isPPC64()) {
-+    const PPCFunctionInfo *PPCFI = MF->getInfo<PPCFunctionInfo>();
-+   if (PPCFI->usesPICBase()) {
-+      MCSymbol *RelocSymbol = PPCFI->getPICOffsetSymbol();
-+      MCSymbol *PICBase = MF->getPICBaseSymbol();
-+      OutStreamer.EmitLabel(RelocSymbol);
-+
-+      const MCExpr *OffsExpr =
-+        MCBinaryExpr::CreateSub(
-+          MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")),
-+                                                               OutContext),
-+                                  MCSymbolRefExpr::Create(PICBase, OutContext),
-+          OutContext);
-+        OutStreamer.EmitValue(OffsExpr, 4);
-+        OutStreamer.EmitLabel(CurrentFnSym);
-+        return;
-+      } else
-+        return AsmPrinter::EmitFunctionEntryLabel();
-+  }
-    
-   // Emit an official procedure descriptor.
-   MCSectionSubPair Current = OutStreamer.getCurrentSection();
-@@ -764,17 +929,27 @@ bool PPCLinuxAsmPrinter::doFinalization(Module &M) {
-   PPCTargetStreamer &TS =
-       static_cast<PPCTargetStreamer &>(*OutStreamer.getTargetStreamer());
-
--  if (isPPC64 && !TOC.empty()) {
--    const MCSectionELF *Section = OutStreamer.getContext().getELFSection(".toc",
-+  if (!TOC.empty()) {
-+    const MCSectionELF *Section;
-+
-+    if (isPPC64)
-+      Section = OutStreamer.getContext().getELFSection(".toc",
-         ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,
-         SectionKind::getReadOnly());
-+       else
-+      Section = OutStreamer.getContext().getELFSection(".got2",
-+        ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,
-+        SectionKind::getReadOnly());
-     OutStreamer.SwitchSection(Section);
-
-     for (MapVector<MCSymbol*, MCSymbol*>::iterator I = TOC.begin(),
-          E = TOC.end(); I != E; ++I) {
-       OutStreamer.EmitLabel(I->second);
-       MCSymbol *S = OutContext.GetOrCreateSymbol(I->first->getName());
--      TS.emitTCEntry(*S);
-+      if (isPPC64)
-+        TS.emitTCEntry(*S);
-+      else
-+        OutStreamer.EmitSymbolValue(S, 4);
-     }
-   }
-
Index: patches/patch-lib_Target_PowerPC_PPCCTRLoops_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCCTRLoops_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCCTRLoops_cpp
--- patches/patch-lib_Target_PowerPC_PPCCTRLoops_cpp 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,29 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCCTRLoops_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r208501
-On PPC32, 128-bit shifts might be runtime calls
-
-The counter-loops formation pass needs to know what operations might be
-function calls (because they can't appear in counter-based loops). On PPC32,
-128-bit shifts might be runtime calls (even though you can't use __int128 on
-PPC32, it seems that SROA might form them).
-
-Fixes PR19709.
-
---- lib/Target/PowerPC/PPCCTRLoops.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/PowerPC/PPCCTRLoops.cpp Sat Jun 14 04:38:11 2014
-@@ -370,6 +370,14 @@ bool PPCCTRLoops::mightUseCTR(const Triple &TT, BasicB
-                 J->getOpcode() == Instruction::URem ||
-                 J->getOpcode() == Instruction::SRem)) {
-       return true;
-+    } else if (TT.isArch32Bit() &&
-+               isLargeIntegerTy(false, J->getType()->getScalarType()) &&
-+               (J->getOpcode() == Instruction::Shl ||
-+                J->getOpcode() == Instruction::AShr ||
-+                J->getOpcode() == Instruction::LShr)) {
-+      // Only on PPC32, for 128-bit integers (specifically not 64-bit
-+      // integers), these might be runtime calls.
-+      return true;
-     } else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) {
-       // On PowerPC, indirect jumps use the counter register.
-       return true;
Index: patches/patch-lib_Target_PowerPC_PPCFastISel_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCFastISel_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCFastISel_cpp
--- patches/patch-lib_Target_PowerPC_PPCFastISel_cpp 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,38 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCFastISel_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r204155
-Fix PR19144: Incorrect offset generated for int-to-fp conversion at -O0.
-
-When converting a signed 32-bit integer to double-precision floating point on
-hardware without a lfiwax instruction, we have to instead use a lfd followed
-by fcfid.  We were erroneously offsetting the address by 4 bytes in
-preparation for either a lfiwax or lfiwzx when generating the lfd.  This fixes
-that silly error.
-
-This was not caught in the test suite since the conversion tests were run with
--mcpu=pwr7, which implies availability of lfiwax.  I've added another test
-case for older hardware that checks the code we expect in the absence of
-lfiwax and other flavors of fcfid.  There are fewer tests in this test case
-because we punt to DAG selection in more cases on older hardware.  (We must
-generate complex fiddly sequences in those cases, and there is marginal
-benefit in duplicating that logic in fast-isel.)
-
---- lib/Target/PowerPC/PPCFastISel.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/PowerPC/PPCFastISel.cpp Sat Jun 14 04:07:38 2014
-@@ -898,11 +898,13 @@ unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsign
-   unsigned LoadOpc = PPC::LFD;
-
-   if (SrcVT == MVT::i32) {
--    Addr.Offset = 4;
--    if (!IsSigned)
-+    if (!IsSigned) {
-       LoadOpc = PPC::LFIWZX;
--    else if (PPCSubTarget.hasLFIWAX())
-+      Addr.Offset = 4;
-+    } else if (PPCSubTarget.hasLFIWAX()) {
-       LoadOpc = PPC::LFIWAX;
-+      Addr.Offset = 4;
-+    }
-   }
-
-   const TargetRegisterClass *RC = &PPC::F8RCRegClass;
Index: patches/patch-lib_Target_PowerPC_PPCFrameLowering_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCFrameLowering_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCFrameLowering_cpp
--- patches/patch-lib_Target_PowerPC_PPCFrameLowering_cpp 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,93 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCFrameLowering_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- lib/Target/PowerPC/PPCFrameLowering.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/PowerPC/PPCFrameLowering.cpp Sun Jul 27 03:29:47 2014
-@@ -299,7 +299,7 @@ void PPCFrameLowering::replaceFPWithRealFP(MachineFunc
-   const PPCRegisterInfo *RegInfo =
-     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
-   bool HasBP = RegInfo->hasBasePointer(MF);
--  unsigned BPReg  = HasBP ? (unsigned) PPC::R30 : FPReg;
-+  unsigned BPReg  = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
-   unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
-
-   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
-@@ -344,6 +344,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &M
-   DebugLoc dl;
-   bool needsFrameMoves = MMI.hasDebugInfo() ||
-     MF.getFunction()->needsUnwindTableEntry();
-+  bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
-
-   // Get processor type.
-   bool isPPC64 = Subtarget.isPPC64();
-@@ -387,7 +388,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &M
-   bool HasBP = RegInfo->hasBasePointer(MF);
-
-   unsigned SPReg       = isPPC64 ? PPC::X1  : PPC::R1;
--  unsigned BPReg       = isPPC64 ? PPC::X30 : PPC::R30;
-+  unsigned BPReg       = RegInfo->getBaseRegister(MF);
-   unsigned FPReg       = isPPC64 ? PPC::X31 : PPC::R31;
-   unsigned LRReg       = isPPC64 ? PPC::LR8 : PPC::LR;
-   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
-@@ -442,7 +443,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &M
-       BPOffset = FFI->getObjectOffset(BPIndex);
-     } else {
-       BPOffset =
--        PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
-+        PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
-+                                                   isDarwinABI,
-+                                                   isPIC);
-     }
-   }
-
-@@ -675,6 +678,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &M
-   // Get the ABI.
-   bool isDarwinABI = Subtarget.isDarwinABI();
-   bool isSVR4ABI = Subtarget.isSVR4ABI();
-+  bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
-
-   // Check if the link register (LR) has been saved.
-   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
-@@ -685,7 +689,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &M
-   bool HasBP = RegInfo->hasBasePointer(MF);
-
-   unsigned SPReg      = isPPC64 ? PPC::X1  : PPC::R1;
--  unsigned BPReg      = isPPC64 ? PPC::X30 : PPC::R30;
-+  unsigned BPReg      = RegInfo->getBaseRegister(MF);
-   unsigned FPReg      = isPPC64 ? PPC::X31 : PPC::R31;
-   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
-   unsigned TempReg     = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
-@@ -725,7 +729,9 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &M
-       BPOffset = FFI->getObjectOffset(BPIndex);
-     } else {
-       BPOffset =
--        PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
-+        PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
-+                                                   isDarwinABI,
-+                                                   isPIC);
-     }
-   }
-
-@@ -902,6 +908,7 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan
-   int FPSI = FI->getFramePointerSaveIndex();
-   bool isPPC64 = Subtarget.isPPC64();
-   bool isDarwinABI  = Subtarget.isDarwinABI();
-+  bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
-   MachineFrameInfo *MFI = MF.getFrameInfo();
-
-   // If the frame pointer save index hasn't been defined yet.
-@@ -916,7 +923,7 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan
-
-   int BPSI = FI->getBasePointerSaveIndex();
-   if (!BPSI && RegInfo->hasBasePointer(MF)) {
--    int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI);
-+    int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
-     // Allocate the frame index for the base pointer save area.
-     BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
-     // Save the result.
Index: patches/patch-lib_Target_PowerPC_PPCFrameLowering_h
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCFrameLowering_h
diff -N patches/patch-lib_Target_PowerPC_PPCFrameLowering_h
--- patches/patch-lib_Target_PowerPC_PPCFrameLowering_h 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,28 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCFrameLowering_h,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- lib/Target/PowerPC/PPCFrameLowering.h.orig Sun Jul 27 00:40:47 2014
-+++ lib/Target/PowerPC/PPCFrameLowering.h Sun Jul 27 00:42:07 2014
-@@ -96,12 +96,14 @@ class PPCFrameLowering: public TargetFrameLowering { (
-
-   /// getBasePointerSaveOffset - Return the previous frame offset to save the
-   /// base pointer.
--  static unsigned getBasePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
-+  static unsigned getBasePointerSaveOffset(bool isPPC64,
-+                                           bool isDarwinABI,
-+                                           bool isPIC) {
-     if (isDarwinABI)
-       return isPPC64 ? -16U : -8U;
-
-     // SVR4 ABI: First slot in the general register save area.
--    return isPPC64 ? -16U : -8U;
-+    return isPPC64 ? -16U : isPIC ? -12U : -8U;
-   }
-
-   /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
Index: patches/patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp
--- patches/patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp 28 Dec 2014 00:30:18 -0000 1.3
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,109 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp,v 1.3 2014/12/28 00:30:18 brad Exp $
-
-r203054
-The PPC global base register cannot be r0
-
-The global base register cannot be r0 because it might end up as the first
-argument to addi or addis. Fixes PR18316.
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
-r213960
-[PowerPC] Support TLS on PPC32/ELF
-
-r209821
-[PPC] Use alias symbols in address computation.
-
-This seems to match what gcc does for ppc and what every other llvm
-backend does.
-
---- lib/Target/PowerPC/PPCISelDAGToDAG.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Dec 26 15:33:12 2014
-@@ -15,6 +15,7 @@
- #define DEBUG_TYPE "ppc-codegen"
- #include "PPC.h"
- #include "MCTargetDesc/PPCPredicates.h"
-+#include "PPCMachineFunctionInfo.h"
- #include "PPCTargetMachine.h"
- #include "llvm/CodeGen/MachineFunction.h"
- #include "llvm/CodeGen/MachineInstrBuilder.h"
-@@ -272,11 +273,23 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
-     DebugLoc dl;
-
-     if (PPCLowering.getPointerTy() == MVT::i32) {
--      GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
-+      if (PPCSubTarget.isTargetELF())
-+        GlobalBaseReg = PPC::R30;
-+      else
-+        GlobalBaseReg =
-+          RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
-       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
-       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
-+      if (PPCSubTarget.isTargetELF()) {
-+        unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
-+        BuildMI(FirstMBB, MBBI, dl,
-+                TII.get(PPC::GetGBRO), TempReg).addReg(GlobalBaseReg);
-+        BuildMI(FirstMBB, MBBI, dl,
-+                TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg).addReg(TempReg);
-+        MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
-+      }
-     } else {
--      GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass);
-+      GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
-       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
-       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
-     }
-@@ -1373,7 +1386,13 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
-     return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
-   }
-   case PPCISD::TOC_ENTRY: {
--    assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI");
-+    if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
-+      SDValue GA = N->getOperand(0);
-+      return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
-+                                    N->getOperand(1));
-+       }
-+    assert (PPCSubTarget.isPPC64() &&
-+            "Only supported for 64-bit ABI and 32-bit SVR4");
-
-     // For medium and large code model, we generate two instructions as
-     // described below.  Otherwise we allow SelectCodeCommon to handle this,
-@@ -1400,24 +1419,21 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
-
-     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
-       const GlobalValue *GValue = G->getGlobal();
--      const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
--      const GlobalValue *RealGValue = GAlias ?
--        GAlias->resolveAliasedGlobal(false) : GValue;
--      const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
--      assert((GVar || isa<Function>(RealGValue)) &&
--             "Unexpected global value subclass!");
--
--      // An external variable is one without an initializer.  For these,
--      // for variables with common linkage, and for Functions, generate
--      // the LDtocL form.
--      if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() ||
--          RealGValue->hasAvailableExternallyLinkage())
-+      if (GValue->getType()->getElementType()->isFunctionTy() ||
-+          GValue->isDeclaration() || GValue->hasCommonLinkage() ||
-+          GValue->hasAvailableExternallyLinkage())
-         return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
-                                       SDValue(Tmp, 0));
-     }
-
-     return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
-                                   SDValue(Tmp, 0), GA);
-+  }
-+  case PPCISD::PPC32_PICGOT: {
-+    // Generate a PIC-safe GOT reference.
-+    assert(!PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI() &&
-+      "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
-+    return CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT, PPCLowering.getPointerTy(), MVT::i32);
-   }
-   case PPCISD::VADD_SPLAT: {
-     // This expands into one of three sequences, depending on whether
Index: patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp
--- patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp 30 Dec 2014 22:41:09 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,251 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCISelLowering_cpp,v 1.2 2014/12/30 22:41:09 brad Exp $
-
-r213899
-Don't use 128bit functions on PPC32.
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
-r213960
-[PowerPC] Support TLS on PPC32/ELF
-
-r223708
-[PowerPC] Don't use a non-allocatable register to implement the 'cc' alias
-
-GCC accepts 'cc' as an alias for 'cr0', and we need to do the same when
-processing inline asm constraints. This had previously been implemented using a
-non-allocatable register, named 'cc', that was listed as an alias of 'cr0', but
-the infrastructure does not seem to support this properly (neither the register
-allocator nor the scheduler properly accounts for the alias). Instead, we can
-just process this as a naming alias inside of the inline asm
-constraint-processing code, so we'll do that instead.
-
-There are two regression tests, one where the post-RA scheduler did the wrong
-thing with the non-allocatable alias, and one where the register allocator did
-the wrong thing. Fixes PR21742.
-
---- lib/Target/PowerPC/PPCISelLowering.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/PowerPC/PPCISelLowering.cpp Tue Dec 30 17:32:03 2014
-@@ -543,6 +543,13 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine
-   // Altivec instructions set fields to all zeros or all ones.
-   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
-
-+  if (!isPPC64) {
-+    // These libcalls are not available in 32-bit.
-+    setLibcallName(RTLIB::SHL_I128, 0);
-+    setLibcallName(RTLIB::SRL_I128, 0);
-+    setLibcallName(RTLIB::SRA_I128, 0);
-+  }
-+
-   if (isPPC64) {
-     setStackPointerRegisterToSaveRestore(PPC::X1);
-     setExceptionPointerRegister(PPC::X3);
-@@ -1360,10 +1367,9 @@ static bool GetLabelAccessInfo(const TargetMachine &TM
-   HiOpFlags = PPCII::MO_HA;
-   LoOpFlags = PPCII::MO_LO;
-
--  // Don't use the pic base if not in PIC relocation model.  Or if we are on a
--  // non-darwin platform.  We don't support PIC on other platforms yet.
--  bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
--               TM.getSubtarget<PPCSubtarget>().isDarwin();
-+  // Don't use the pic base if not in PIC relocation model.
-+  bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
-+
-   if (isPIC) {
-     HiOpFlags |= PPCII::MO_PIC_FLAG;
-     LoOpFlags |= PPCII::MO_PIC_FLAG;
-@@ -1419,6 +1425,15 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue O
-
-   unsigned MOHiFlag, MOLoFlag;
-   bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
-+
-+  if (isPIC && PPCSubTarget.isSVR4ABI()) {
-+    SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
-+                                           PPCII::MO_PIC_FLAG);
-+    SDLoc DL(CP);
-+    return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
-+                       DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
-+  }
-+
-   SDValue CPIHi =
-     DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
-   SDValue CPILo =
-@@ -1440,6 +1455,15 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op,
-
-   unsigned MOHiFlag, MOLoFlag;
-   bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
-+
-+  if (isPIC && PPCSubTarget.isSVR4ABI()) {
-+    SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
-+                                        PPCII::MO_PIC_FLAG);
-+    SDLoc DL(GA);
-+    return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
-+                       DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
-+  }
-+
-   SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
-   SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
-   return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
-@@ -1502,47 +1526,61 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDVal
-
-   if (Model == TLSModel::GeneralDynamic) {
-     SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
--    SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
--    SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
--                                     GOTReg, TGA);
-+    SDValue GOTPtr;
-+    if (is64bit) {
-+      SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
-+      GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
-+                                   GOTReg, TGA);
-+    } else {
-+      GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
-+    }
-     SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
--                                   GOTEntryHi, TGA);
-+                                   GOTPtr, TGA);
-
-     // We need a chain node, and don't have one handy.  The underlying
-     // call has no side effects, so using the function entry node
-     // suffices.
-     SDValue Chain = DAG.getEntryNode();
--    Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
--    SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
-+    Chain = DAG.getCopyToReg(Chain, dl,
-+                             is64bit ? PPC::X3 : PPC::R3, GOTEntry);
-+    SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
-+                                      is64bit ? MVT::i64 : MVT::i32);
-     SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
-                                   PtrVT, ParmReg, TGA);
-     // The return value from GET_TLS_ADDR really is in X3 already, but
-     // some hacks are needed here to tie everything together.  The extra
-     // copies dissolve during subsequent transforms.
--    Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
--    return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
-+    Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
-+    return DAG.getCopyFromReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, PtrVT);
-   }
-
-   if (Model == TLSModel::LocalDynamic) {
-     SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
--    SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
--    SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
--                                     GOTReg, TGA);
-+    SDValue GOTPtr;
-+    if (is64bit) {
-+      SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
-+      GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
-+                           GOTReg, TGA);
-+    } else {
-+      GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
-+    }
-     SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
--                                   GOTEntryHi, TGA);
-+                                   GOTPtr, TGA);
-
-     // We need a chain node, and don't have one handy.  The underlying
-     // call has no side effects, so using the function entry node
-     // suffices.
-     SDValue Chain = DAG.getEntryNode();
--    Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
--    SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
-+    Chain = DAG.getCopyToReg(Chain, dl,
-+                             is64bit ? PPC::X3 : PPC::R3, GOTEntry);
-+    SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
-+                                      is64bit ? MVT::i64 : MVT::i32);
-     SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
-                                   PtrVT, ParmReg, TGA);
-     // The return value from GET_TLSLD_ADDR really is in X3 already, but
-     // some hacks are needed here to tie everything together.  The extra
-     // copies dissolve during subsequent transforms.
--    Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
-+    Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
-     SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
-                                       Chain, ParmReg, TGA);
-     return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
-@@ -1569,6 +1607,14 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue
-   unsigned MOHiFlag, MOLoFlag;
-   bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
-
-+  if (isPIC && PPCSubTarget.isSVR4ABI()) {
-+    SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
-+                                            GSDN->getOffset(),
-+                                            PPCII::MO_PIC_FLAG);
-+    return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
-+                       DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
-+  }
-+
-   SDValue GAHi =
-     DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
-   SDValue GALo =
-@@ -3276,15 +3322,18 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Calle
-     // far-call stubs may be outside relocation limits for a BL instruction.
-     if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
-       unsigned OpFlags = 0;
--      if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
-+      if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
-           (PPCSubTarget.getTargetTriple().isMacOSX() &&
-            PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
-           (G->getGlobal()->isDeclaration() ||
--           G->getGlobal()->isWeakForLinker())) {
-+           G->getGlobal()->isWeakForLinker())) ||
-+          (PPCSubTarget.isTargetELF() && !isPPC64 &&
-+           !G->getGlobal()->hasLocalLinkage() &&
-+           DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
-         // PC-relative references to external symbols should go through $stub,
-         // unless we're building with the leopard linker or later, which
-         // automatically synthesizes these stubs.
--        OpFlags = PPCII::MO_DARWIN_STUB;
-+        OpFlags = PPCII::MO_PLT_OR_STUB;
-       }
-
-       // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
-@@ -3300,13 +3349,15 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Calle
-   if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
-     unsigned char OpFlags = 0;
-
--    if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
--        (PPCSubTarget.getTargetTriple().isMacOSX() &&
--         PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
-+    if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
-+         (PPCSubTarget.getTargetTriple().isMacOSX() &&
-+          PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
-+        (PPCSubTarget.isTargetELF() && !isPPC64 &&
-+         DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
-       // PC-relative references to external symbols should go through $stub,
-       // unless we're building with the leopard linker or later, which
-       // automatically synthesizes these stubs.
--      OpFlags = PPCII::MO_DARWIN_STUB;
-+      OpFlags = PPCII::MO_PLT_OR_STUB;
-     }
-
-     Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
-@@ -6371,7 +6422,10 @@ PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
-   // Since FP is only updated here but NOT referenced, it's treated as GPR.
-   unsigned FP  = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
-   unsigned SP  = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
--  unsigned BP  = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
-+  unsigned BP  = (PVT == MVT::i64) ? PPC::X30 :
-+                  (PPCSubTarget.isSVR4ABI() &&
-+                   MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
-+                     PPC::R29 : PPC::R30);
-
-   MachineInstrBuilder MIB;
-
-@@ -8317,6 +8371,12 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const
-     return std::make_pair(TRI->getMatchingSuperReg(R.first,
-                             PPC::sub_32, &PPC::G8RCRegClass),
-                           &PPC::G8RCRegClass);
-+  }
-+
-+  // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
-+  if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
-+    R.first = PPC::CR0;
-+    R.second = &PPC::CRRCRegClass;
-   }
-
-   return R;
Index: patches/patch-lib_Target_PowerPC_PPCISelLowering_h
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCISelLowering_h
diff -N patches/patch-lib_Target_PowerPC_PPCISelLowering_h
--- patches/patch-lib_Target_PowerPC_PPCISelLowering_h 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,18 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCISelLowering_h,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213960
-[PowerPC] Support TLS on PPC32/ELF
-
---- lib/Target/PowerPC/PPCISelLowering.h.orig Sun Jul 27 04:08:54 2014
-+++ lib/Target/PowerPC/PPCISelLowering.h Sun Jul 27 04:09:34 2014
-@@ -187,6 +187,10 @@ namespace llvm {
-       /// on PPC32.
-       PPC32_GOT,
-
-+      /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
-+      /// local dynamic TLS on PPC32.
-+      PPC32_PICGOT,
-+
-       /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
-       /// TLS model, produces an ADDIS8 instruction that adds the GOT
-       /// base to sym\@got\@tprel\@ha.
Index: patches/patch-lib_Target_PowerPC_PPCInstrInfo_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCInstrInfo_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCInstrInfo_cpp
--- patches/patch-lib_Target_PowerPC_PPCInstrInfo_cpp 11 Sep 2014 17:59:51 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,20 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCInstrInfo_cpp,v 1.1 2014/09/11 17:59:51 brad Exp $
-
-r215238
-Provide an implementation of getNoopForMachoTarget for PPC, otherwise
-empty functions will assert in the MC object writer.
-
---- lib/Target/PowerPC/PPCInstrInfo.cpp.orig Fri Aug 29 23:39:36 2014
-+++ lib/Target/PowerPC/PPCInstrInfo.cpp Fri Aug 29 23:41:26 2014
-@@ -296,6 +296,11 @@ void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
-   BuildMI(MBB, MI, DL, get(Opcode));
- }
-
-+/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
-+void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
-+  NopInst.setOpcode(PPC::NOP);
-+}
-+
- // Branch analysis.
- // Note: If the condition register is set to CTR or CTR8 then this is a
- // BDNZ (imm == 1) or BDZ (imm == 0) branch.
Index: patches/patch-lib_Target_PowerPC_PPCInstrInfo_h
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCInstrInfo_h
diff -N patches/patch-lib_Target_PowerPC_PPCInstrInfo_h
--- patches/patch-lib_Target_PowerPC_PPCInstrInfo_h 11 Sep 2014 17:59:51 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,17 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCInstrInfo_h,v 1.1 2014/09/11 17:59:51 brad Exp $
-
-r215238
-Provide an implementation of getNoopForMachoTarget for PPC, otherwise
-empty functions will assert in the MC object writer.
-
---- lib/Target/PowerPC/PPCInstrInfo.h.orig Fri Aug 29 23:39:27 2014
-+++ lib/Target/PowerPC/PPCInstrInfo.h Fri Aug 29 23:40:50 2014
-@@ -228,6 +228,8 @@ class PPCInstrInfo : public PPCGenInstrInfo { (public)
-   /// instruction may be.  This returns the maximum number of bytes.
-   ///
-   virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
-+
-+  void getNoopForMachoTarget(MCInst &NopInst) const;
- };
-
- }
Index: patches/patch-lib_Target_PowerPC_PPCInstrInfo_td
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCInstrInfo_td
diff -N patches/patch-lib_Target_PowerPC_PPCInstrInfo_td
--- patches/patch-lib_Target_PowerPC_PPCInstrInfo_td 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,106 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCInstrInfo_td,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
-r213960
-[PowerPC] Support TLS on PPC32/ELF
-
---- lib/Target/PowerPC/PPCInstrInfo.td.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/PowerPC/PPCInstrInfo.td Sun Jul 27 04:42:32 2014
-@@ -57,6 +57,9 @@ def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
-   SDTCisPtrTy<0>, SDTCisVT<1, i32>
- ]>;
-
-+def tocentry32 : Operand<iPTR> {
-+  let MIOperandInfo = (ops i32imm:$imm);
-+}
-
- //===----------------------------------------------------------------------===//
- // PowerPC specific DAG Nodes.
-@@ -580,6 +583,12 @@ def tlsreg32 : Operand<i32> {
-   let EncoderMethod = "getTLSRegEncoding";
-   let ParserMatchClass = PPCTLSRegOperand;
- }
-+def tlsgd32 : Operand<i32> {}
-+def tlscall32 : Operand<i32> {
-+  let PrintMethod = "printTLSCall";
-+  let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
-+  let EncoderMethod = "getTLSCallEncoding";
-+}
-
- // PowerPC Predicate operand.
- def pred : Operand<OtherVT> {
-@@ -1063,6 +1072,8 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
-                     "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
-
-     let isCodeGenOnly = 1 in {
-+      def BL_TLS  : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
-+                          "bl $func", IIC_BrB, []>;
-       def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
-                        "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
-       def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
-@@ -2369,12 +2380,56 @@ def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
- def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
-                 [(set i32:$rD, (PPCppc32GOT))]>;
-
-+// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
-+// This uses two output registers, the first as the real output, the second as a
-+// temporary register, used internally in code generation.
-+def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
-+                []>, NoEncode<"$rT">;
-+
- def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
--                        "#LDgotTprelL32",
--                        [(set i32:$rD,
--                          (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
-+                           "#LDgotTprelL32",
-+                           [(set i32:$rD,
-+                             (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
- def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
-           (ADD4TLS $in, tglobaltlsaddr:$g)>;
-+
-+def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
-+                         "#ADDItlsgdL32",
-+                         [(set i32:$rD,
-+                           (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
-+def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
-+                          "#GETtlsADDR32",
-+                          [(set i32:$rD,
-+                            (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
-+def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
-+                          "#ADDItlsldL32",
-+                          [(set i32:$rD,
-+                            (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
-+def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
-+                            "#GETtlsldADDR32",
-+                            [(set i32:$rD,
-+                              (PPCgetTlsldAddr i32:$reg, tglobaltlsaddr:$sym))]>;
-+def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
-+                           "#ADDIdtprelL32",
-+                           [(set i32:$rD,
-+                             (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
-+def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
-+                            "#ADDISdtprelHA32",
-+                            [(set i32:$rD,
-+                              (PPCaddisDtprelHA i32:$reg,
-+                                                tglobaltlsaddr:$disp))]>;
-+
-+// Support for Position-independent code
-+def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
-+                  "#LWZtoc",
-+                  [(set i32:$rD,
-+                     (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
-+// Get Global (GOT) Base Register offset, from the word immediately preceding
-+// the function label.
-+def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
-+// Update the Global(GOT) Base Register with the above offset.
-+def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
-+
-
- // Standard shifts.  These are represented separately from the real shifts above
- // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
Index: patches/patch-lib_Target_PowerPC_PPCMCInstLower_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCMCInstLower_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCMCInstLower_cpp
--- patches/patch-lib_Target_PowerPC_PPCMCInstLower_cpp 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,56 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCMCInstLower_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- lib/Target/PowerPC/PPCMCInstLower.cpp.orig Sun Jul 27 01:32:18 2014
-+++ lib/Target/PowerPC/PPCMCInstLower.cpp Sun Jul 27 01:34:48 2014
-@@ -13,6 +13,7 @@
- //===----------------------------------------------------------------------===//
-
- #include "PPC.h"
-+#include "PPCSubtarget.h"
- #include "MCTargetDesc/PPCMCExpr.h"
- #include "llvm/ADT/SmallString.h"
- #include "llvm/ADT/Twine.h"
-@@ -39,12 +40,14 @@ static MCSymbol *GetSymbolFromOperand(const MachineOpe
-   Mangler *Mang = AP.Mang;
-   const DataLayout *DL = TM.getDataLayout();
-   MCContext &Ctx = AP.OutContext;
-+  bool isDarwin = TM.getSubtarget<PPCSubtarget>().isDarwin();
-
-   SmallString<128> Name;
-   StringRef Suffix;
--  if (MO.getTargetFlags() == PPCII::MO_DARWIN_STUB)
--    Suffix = "$stub";
--  else if (MO.getTargetFlags() & PPCII::MO_NLP_FLAG)
-+  if (MO.getTargetFlags() == PPCII::MO_PLT_OR_STUB) {
-+    if (isDarwin)
-+      Suffix = "$stub";
-+  } else if (MO.getTargetFlags() & PPCII::MO_NLP_FLAG)
-     Suffix = "$non_lazy_ptr";
-
-   if (!Suffix.empty())
-@@ -68,7 +71,7 @@ static MCSymbol *GetSymbolFromOperand(const MachineOpe
-
-   // If the target flags on the operand changes the name of the symbol, do that
-   // before we return the symbol.
--  if (MO.getTargetFlags() == PPCII::MO_DARWIN_STUB) {
-+  if (MO.getTargetFlags() == PPCII::MO_PLT_OR_STUB && isDarwin) {
-     MachineModuleInfoImpl::StubValueTy &StubSym =
-       getMachOMMI(AP).getFnStubEntry(Sym);
-     if (StubSym.getPointer())
-@@ -135,6 +138,9 @@ static MCOperand GetSymbolRef(const MachineOperand &MO
-       RefKind = MCSymbolRefExpr::VK_PPC_TLS;
-       break;
-   }
-+
-+  if (MO.getTargetFlags() == PPCII::MO_PLT_OR_STUB && !isDarwin)
-+    RefKind = MCSymbolRefExpr::VK_PLT;
-
-   const MCExpr *Expr = MCSymbolRefExpr::Create(Symbol, RefKind, Ctx);
-
Index: patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp
--- patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,28 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- lib/Target/PowerPC/PPCMachineFunctionInfo.cpp.orig Sun Jul 27 01:35:45 2014
-+++ lib/Target/PowerPC/PPCMachineFunctionInfo.cpp Sun Jul 27 01:37:10 2014
-@@ -8,8 +8,16 @@
- //===----------------------------------------------------------------------===//
-
- #include "PPCMachineFunctionInfo.h"
-+#include "llvm/IR/DataLayout.h"
-+#include "llvm/MC/MCContext.h"
-+#include "llvm/Target/TargetMachine.h"
-
- using namespace llvm;
-
- void PPCFunctionInfo::anchor() { }
-
-+MCSymbol *PPCFunctionInfo::getPICOffsetSymbol() const {
-+  const DataLayout *DL = MF.getTarget().getDataLayout();
-+  return MF.getContext().GetOrCreateSymbol(Twine(DL->getPrivateGlobalPrefix())+
-+    Twine(MF.getFunctionNumber())+"$poff");
-+}
Index: patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h
diff -N patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h
--- patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,47 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- lib/Target/PowerPC/PPCMachineFunctionInfo.h.orig Sun Jul 27 01:37:54 2014
-+++ lib/Target/PowerPC/PPCMachineFunctionInfo.h Sun Jul 27 01:40:18 2014
-@@ -92,6 +92,12 @@ class PPCFunctionInfo : public MachineFunctionInfo {
-   /// 64-bit SVR4 ABI.
-   SmallVector<unsigned, 3> MustSaveCRs;
-
-+  /// Hold onto our MachineFunction context.
-+  MachineFunction &MF;
-+
-+  /// Whether this uses the PIC Base register or not.
-+  bool UsesPICBase;
-+
- public:
-   explicit PPCFunctionInfo(MachineFunction &MF)
-     : FramePointerSaveIndex(0),
-@@ -109,7 +115,9 @@ class PPCFunctionInfo : public MachineFunctionInfo {
-       VarArgsStackOffset(0),
-       VarArgsNumGPR(0),
-       VarArgsNumFPR(0),
--      CRSpillFrameIndex(0) {}
-+      CRSpillFrameIndex(0),
-+      MF(MF),
-+      UsesPICBase(0) {}
-
-   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
-   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
-@@ -170,6 +178,11 @@ class PPCFunctionInfo : public MachineFunctionInfo {
-   const SmallVectorImpl<unsigned> &
-     getMustSaveCRs() const { return MustSaveCRs; }
-   void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); }
-+
-+  void setUsesPICBase(bool uses) { UsesPICBase = uses; }
-+  bool usesPICBase() const { return UsesPICBase; }
-+
-+  MCSymbol *getPICOffsetSymbol() const;
- };
-
- } // end of namespace llvm
Index: patches/patch-lib_Target_PowerPC_PPCRegisterInfo_cpp
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCRegisterInfo_cpp
diff -N patches/patch-lib_Target_PowerPC_PPCRegisterInfo_cpp
--- patches/patch-lib_Target_PowerPC_PPCRegisterInfo_cpp 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,45 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCRegisterInfo_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- lib/Target/PowerPC/PPCRegisterInfo.cpp.orig Sun Jul 27 01:40:38 2014
-+++ lib/Target/PowerPC/PPCRegisterInfo.cpp Sun Jul 27 01:45:41 2014
-@@ -199,7 +199,16 @@ BitVector PPCRegisterInfo::getReservedRegs(const Machi
-   if (PPCFI->needsFP(MF))
-     Reserved.set(PPC::R31);
-
--  if (hasBasePointer(MF))
-+  if (hasBasePointer(MF)) {
-+       if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
-+        MF.getTarget().getRelocationModel() == Reloc::PIC_)
-+      Reserved.set(PPC::R29);
-+    else
-+      Reserved.set(PPC::R30);
-+  }
-+
-+  if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
-+      MF.getTarget().getRelocationModel() == Reloc::PIC_)
-     Reserved.set(PPC::R30);
-
-   // Reserve Altivec registers when Altivec is unavailable.
-@@ -822,7 +831,14 @@ unsigned PPCRegisterInfo::getBaseRegister(const Machin
-   if (!hasBasePointer(MF))
-     return getFrameRegister(MF);
-
--  return Subtarget.isPPC64() ? PPC::X30 : PPC::R30;
-+  if (Subtarget.isPPC64())
-+    return PPC::X30;
-+
-+  if (Subtarget.isSVR4ABI() &&
-+      MF.getTarget().getRelocationModel() == Reloc::PIC_)
-+    return PPC::R29;
-+
-+  return PPC::R30;
- }
-
- bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
Index: patches/patch-lib_Target_PowerPC_PPCSubtarget_h
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPCSubtarget_h
diff -N patches/patch-lib_Target_PowerPC_PPCSubtarget_h
--- patches/patch-lib_Target_PowerPC_PPCSubtarget_h 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,21 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPCSubtarget_h,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- lib/Target/PowerPC/PPCSubtarget.h.orig Sun Jul 27 01:47:26 2014
-+++ lib/Target/PowerPC/PPCSubtarget.h Sun Jul 27 01:47:59 2014
-@@ -195,6 +195,9 @@ class PPCSubtarget : public PPCGenSubtargetInfo { (pub
-   /// isBGQ - True if this is a BG/Q platform.
-   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
-
-+  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
-+  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
-+
-   bool isDarwinABI() const { return isDarwin(); }
-   bool isSVR4ABI() const { return !isDarwin(); }
-
Index: patches/patch-lib_Target_PowerPC_PPC_h
===================================================================
RCS file: patches/patch-lib_Target_PowerPC_PPC_h
diff -N patches/patch-lib_Target_PowerPC_PPC_h
--- patches/patch-lib_Target_PowerPC_PPC_h 11 Sep 2014 17:54:13 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,27 +0,0 @@
-$OpenBSD: patch-lib_Target_PowerPC_PPC_h,v 1.1 2014/09/11 17:54:13 brad Exp $
-
-r213427
-[PowerPC] 32-bit ELF PIC support
-
-This adds initial support for PPC32 ELF PIC (Position Independent Code; the
--fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
-backend.
-
---- lib/Target/PowerPC/PPC.h.orig Sun Jul 27 00:05:08 2014
-+++ lib/Target/PowerPC/PPC.h Sun Jul 27 00:06:13 2014
-@@ -53,10 +53,11 @@ namespace llvm {
-     // PPC Specific MachineOperand flags.
-     MO_NO_FLAG,
-    
--    /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
--    /// reference is actually to the "FOO$stub" symbol.  This is used for calls
--    /// and jumps to external functions on Tiger and earlier.
--    MO_DARWIN_STUB = 1,
-+    /// MO_PLT_OR_STUB - On a symbol operand "FOO", this indicates that the
-+    /// reference is actually to the "FOO$stub" or "FOO@plt" symbol. This is
-+    /// used for calls and jumps to external functions on Tiger and earlier, and
-+    /// for PIC calls on Linux and ELF systems.
-+    MO_PLT_OR_STUB = 1,
-    
-     /// MO_PIC_FLAG - If this bit is set, the symbol reference is relative to
-     /// the function's picbase, e.g. lo16(symbol-picbase).
Index: patches/patch-lib_Target_R600_AMDGPUCallingConv_td
===================================================================
RCS file: patches/patch-lib_Target_R600_AMDGPUCallingConv_td
diff -N patches/patch-lib_Target_R600_AMDGPUCallingConv_td
--- patches/patch-lib_Target_R600_AMDGPUCallingConv_td 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,18 +0,0 @@
-$OpenBSD: patch-lib_Target_R600_AMDGPUCallingConv_td,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r207990
-R600/SI: allow 5 more input SGPRs to a shader
-
-Our OpenGL driver needs 22 SGPRs (16 user SGPRs + 6 streamout non-user SGPRs).
-
---- lib/Target/R600/AMDGPUCallingConv.td.orig Sun Mar  2 21:57:40 2014
-+++ lib/Target/R600/AMDGPUCallingConv.td Sat Jun 14 04:35:50 2014
-@@ -20,7 +20,7 @@ def CC_SI : CallingConv<[
-   CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[
-     SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
-     SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
--    SGPR16
-+    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21
-   ]>>>,
-
-   CCIfInReg<CCIfType<[i64] , CCAssignToRegWithShadow<
Index: patches/patch-lib_Target_R600_R600Instructions_td
===================================================================
RCS file: patches/patch-lib_Target_R600_R600Instructions_td
diff -N patches/patch-lib_Target_R600_R600Instructions_td
--- patches/patch-lib_Target_R600_R600Instructions_td 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,26 +0,0 @@
-$OpenBSD: patch-lib_Target_R600_R600Instructions_td,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r203818
-R600: LDS instructions shouldn't implicitly define OQAP
-
-LDS instructions are pseudo instructions which model
-the OQAP defs and uses within a single instruction.
-
---- lib/Target/R600/R600Instructions.td.orig Sat Jun 14 03:48:50 2014
-+++ lib/Target/R600/R600Instructions.td Sat Jun 14 03:50:30 2014
-@@ -1648,7 +1648,6 @@ class R600_LDS_1A <bits<6> lds_op, string name, list<d
-   let src2 = 0;
-   let src2_rel = 0;
-
--  let Defs = [OQAP];
-   let usesCustomInserter = 1;
-   let LDS_1A = 1;
-   let DisableEncoding = "$dst";
-@@ -1684,7 +1683,6 @@ class R600_LDS_1A1D_RET <bits<6> lds_op, string name,
-   let BaseOp = name;
-   let usesCustomInserter = 1;
-   let DisableEncoding = "$dst";
--  let Defs = [OQAP];
- }
-
- class R600_LDS_1A2D <bits<6> lds_op, string name, list<dag> pattern> :
Index: patches/patch-lib_Target_R600_SIInstrInfo_td
===================================================================
RCS file: patches/patch-lib_Target_R600_SIInstrInfo_td
diff -N patches/patch-lib_Target_R600_SIInstrInfo_td
--- patches/patch-lib_Target_R600_SIInstrInfo_td 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,21 +0,0 @@
-$OpenBSD: patch-lib_Target_R600_SIInstrInfo_td,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r203281
-R600/SI: Using SGPRs is illegal for instructions that read carry-out
-from VCC
-
---- lib/Target/R600/SIInstrInfo.td.orig Sat Jun 14 03:42:53 2014
-+++ lib/Target/R600/SIInstrInfo.td Sat Jun 14 03:44:40 2014
-@@ -298,10 +298,10 @@ multiclass VOP2_64 <bits<6> op, string opName, list<da
-   : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern, revOp>;
-
- multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
--                     string revOp = opName> {
-+                     RegisterClass src0_rc, string revOp = opName> {
-
-   def _e32 : VOP2 <
--    op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
-+    op, (outs VReg_32:$dst), (ins src0_rc:$src0, VReg_32:$src1),
-     opName#"_e32 $dst, $src0, $src1", pattern
-   >, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
-
Index: patches/patch-lib_Target_R600_SIInstructions_td
===================================================================
RCS file: patches/patch-lib_Target_R600_SIInstructions_td
diff -N patches/patch-lib_Target_R600_SIInstructions_td
--- patches/patch-lib_Target_R600_SIInstructions_td 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,31 +0,0 @@
-$OpenBSD: patch-lib_Target_R600_SIInstructions_td,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r203281
-R600/SI: Using SGPRs is illegal for instructions that read carry-out
-from VCC
-
---- lib/Target/R600/SIInstructions.td.orig Sat Jun 14 03:44:53 2014
-+++ lib/Target/R600/SIInstructions.td Sat Jun 14 03:46:43 2014
-@@ -1007,14 +1007,16 @@ defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCN
- let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
- // No patterns so that the scalar instructions are always selected.
- // The scalar versions will be replaced with vector when needed later.
--defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", []>;
--defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", []>;
--defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">;
-+defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", [], VSrc_32>;
-+defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", [], VSrc_32>;
-+defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
-+                              "V_SUB_I32">;
-
- let Uses = [VCC] in { // Carry-in comes from VCC
--defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
--defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
--defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">;
-+defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", [], VReg_32>;
-+defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", [], VReg_32>;
-+defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
-+                               "V_SUBB_U32">;
- } // End Uses = [VCC]
- } // End isCommutable = 1, Defs = [VCC]
-
Index: patches/patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp
===================================================================
RCS file: patches/patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp
diff -N patches/patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp
--- patches/patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp 19 May 2015 05:33:39 -0000 1.3
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,449 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp,v 1.3 2015/05/19 05:33:39 ajacoutot Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
-r236107
-Sparc: Prefer reg+reg address encoding when only one register used.
-
-Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces.
-
-Futhermore, reg+imm is invalid for the (not yet supported) "alternate
-address space" instructions.
-
-r236137
-Make Sparc assembler accept parenthesized constant expressions.
-
-r237580
-Add support for the Sparc implementation-defined "ASR" registers.
-
-r237581
-Sparc: Add the "alternate address space" load/store instructions.
-
-- Adds support for the asm syntax, which has an immediate integer
-  "ASI" (address space identifier) appearing after an address, before
-  a comma.
-
-- Adds the various-width load, store, and swap in alternate address
-  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
-  sta, swapa)
-
-r237582
-Sparc: Support PSR, TBR, WIM read/write instructions.
-
---- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Mon May 18 19:47:25 2015
-@@ -12,9 +12,11 @@
- #include "llvm/ADT/STLExtras.h"
- #include "llvm/MC/MCContext.h"
- #include "llvm/MC/MCInst.h"
-+#include "llvm/MC/MCObjectFileInfo.h"
- #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
- #include "llvm/MC/MCStreamer.h"
- #include "llvm/MC/MCSubtargetInfo.h"
-+#include "llvm/MC/MCSymbol.h"
- #include "llvm/MC/MCTargetAsmParser.h"
- #include "llvm/Support/TargetRegistry.h"
-
-@@ -66,14 +68,19 @@ class SparcAsmParser : public MCTargetAsmParser {
-                StringRef Name);
-
-   OperandMatchResultTy
--  parseSparcAsmOperand(SparcOperand *&Operand);
-+  parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false);
-
-+  OperandMatchResultTy
-+  parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
-+
-   // returns true if Tok is matched to a register and returns register in RegNo.
-   bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
-                          unsigned &RegKind);
-
-   bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
-+  bool parseDirectiveWord(unsigned Size, SMLoc L);
-
-+  bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
- public:
-   SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
-                 const MCInstrInfo &MII)
-@@ -120,6 +127,15 @@ class SparcAsmParser : public MCTargetAsmParser {
-     Sparc::Q8,  Sparc::Q9,  Sparc::Q10, Sparc::Q11,
-     Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
-
-+  static unsigned ASRRegs[32] = {
-+    SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
-+    SP::ASR4,  SP::ASR5,  SP::ASR6, SP::ASR7,
-+    SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
-+    SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
-+    SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
-+    SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
-+    SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
-+    SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
-
- /// SparcOperand - Instances of this class represent a parsed Sparc machine
- /// instruction.
-@@ -131,9 +147,9 @@ class SparcOperand : public MCParsedAsmOperand { (publ
-     rk_FloatReg,
-     rk_DoubleReg,
-     rk_QuadReg,
--    rk_CCReg,
--    rk_Y
-+    rk_Special
-   };
-+
- private:
-   enum KindTy {
-     k_Token,
-@@ -354,13 +370,11 @@ class SparcOperand : public MCParsedAsmOperand { (publ
-     return Op;
-   }
-
--  static SparcOperand *CreateMEMri(unsigned Base,
--                                 const MCExpr *Off,
--                                 SMLoc S, SMLoc E) {
--    SparcOperand *Op = new SparcOperand(k_MemoryImm);
-+  static SparcOperand *CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
-+    SparcOperand *Op = new SparcOperand(k_MemoryReg);
-     Op->Mem.Base = Base;
--    Op->Mem.OffsetReg = 0;
--    Op->Mem.Off = Off;
-+    Op->Mem.OffsetReg = Sparc::G0;  // always 0
-+    Op->Mem.Off = 0;
-     Op->StartLoc = S;
-     Op->EndLoc = E;
-     return Op;
-@@ -415,7 +429,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
-     return Error(ErrorLoc, "invalid operand for instruction");
-   }
-   case Match_MnemonicFail:
--    return Error(IDLoc, "invalid instruction");
-+    return Error(IDLoc, "invalid instruction mnemonic");
-   }
-   return true;
- }
-@@ -439,21 +453,30 @@ ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc
-   return Error(StartLoc, "invalid register name");
- }
-
-+static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
-+                                 unsigned VariantID);
-+
- bool SparcAsmParser::
- ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
-                  SMLoc NameLoc,
-                  SmallVectorImpl<MCParsedAsmOperand*> &Operands)
- {
--  // Check if we have valid mnemonic.
--  if (!mnemonicIsValid(Name, 0)) {
--    Parser.eatToEndOfStatement();
--    return Error(NameLoc, "Unknown instruction");
--  }
-+
-   // First operand in MCInst is instruction mnemonic.
-   Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
-
-+  // apply mnemonic aliases, if any, so that we can parse operands correctly.
-+  applyMnemonicAliases(Name, getAvailableFeatures(), 0);
-+
-   if (getLexer().isNot(AsmToken::EndOfStatement)) {
-     // Read the first operand.
-+    if (getLexer().is(AsmToken::Comma)) {
-+      if (parseBranchModifiers(Operands) != MatchOperand_Success) {
-+        SMLoc Loc = getLexer().getLoc();
-+        Parser.eatToEndOfStatement();
-+        return Error(Loc, "unexpected token");
-+      }
-+    }
-     if (parseOperand(Operands, Name) != MatchOperand_Success) {
-       SMLoc Loc = getLexer().getLoc();
-       Parser.eatToEndOfStatement();
-@@ -482,8 +505,52 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef
- bool SparcAsmParser::
- ParseDirective(AsmToken DirectiveID)
- {
--  // Ignore all directives for now.
--  Parser.eatToEndOfStatement();
-+  StringRef IDVal = DirectiveID.getString();
-+
-+  if (IDVal == ".byte")
-+    return parseDirectiveWord(1, DirectiveID.getLoc());
-+
-+  if (IDVal == ".half")
-+    return parseDirectiveWord(2, DirectiveID.getLoc());
-+
-+  if (IDVal == ".word")
-+    return parseDirectiveWord(4, DirectiveID.getLoc());
-+
-+  if (IDVal == ".nword")
-+    return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
-+
-+  if (is64Bit() && IDVal == ".xword")
-+    return parseDirectiveWord(8, DirectiveID.getLoc());
-+
-+  if (IDVal == ".register") {
-+    // For now, ignore .register directive.
-+    Parser.eatToEndOfStatement();
-+    return false;
-+  }
-+
-+  // Let the MC layer to handle other directives.
-+  return true;
-+}
-+
-+bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
-+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
-+    for (;;) {
-+      const MCExpr *Value;
-+      if (getParser().parseExpression(Value))
-+        return true;
-+
-+      getParser().getStreamer().EmitValue(Value, Size);
-+
-+      if (getLexer().is(AsmToken::EndOfStatement))
-+        break;
-+
-+      // FIXME: Improve diagnostic.
-+      if (getLexer().isNot(AsmToken::Comma))
-+        return Error(L, "unexpected token in directive");
-+      Parser.Lex();
-+    }
-+  }
-+  Parser.Lex();
-   return false;
- }
-
-@@ -504,7 +571,7 @@ parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &
-   case AsmToken::Comma:
-   case AsmToken::RBrac:
-   case AsmToken::EndOfStatement:
--    Operands.push_back(SparcOperand::CreateMEMri(BaseReg, 0, S, E));
-+    Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
-     return MatchOperand_Success;
-
-   case AsmToken:: Plus:
-@@ -573,11 +640,21 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
-     Operands.push_back(SparcOperand::CreateToken("]",
-                                                  Parser.getTok().getLoc()));
-     Parser.Lex(); // Eat the ]
-+
-+    // Parse an optional address-space identifier after the address.
-+    if (getLexer().is(AsmToken::Integer)) {
-+      SparcOperand *Op = 0;
-+      ResTy = parseSparcAsmOperand(Op, false);
-+      if (ResTy != MatchOperand_Success || !Op)
-+        return MatchOperand_ParseFail;
-+      Operands.push_back(Op);
-+    }
-     return MatchOperand_Success;
-   }
-
-   SparcOperand *Op = 0;
--  ResTy = parseSparcAsmOperand(Op);
-+
-+  ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
-   if (ResTy != MatchOperand_Success || !Op)
-     return MatchOperand_ParseFail;
-
-@@ -588,7 +665,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
- }
-
- SparcAsmParser::OperandMatchResultTy
--SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op)
-+SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall)
- {
-
-   SMLoc S = Parser.getTok().getLoc();
-@@ -611,21 +688,21 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
-       default:
-         Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
-         break;
--      case Sparc::Y:
--        Op = SparcOperand::CreateToken("%y", S);
-+      case Sparc::PSR:
-+        Op = SparcOperand::CreateToken("%psr", S);
-         break;
--
-+      case Sparc::WIM:
-+        Op = SparcOperand::CreateToken("%wim", S);
-+        break;
-+      case Sparc::TBR:
-+        Op = SparcOperand::CreateToken("%tbr", S);
-+        break;
-       case Sparc::ICC:
-         if (name == "xcc")
-           Op = SparcOperand::CreateToken("%xcc", S);
-         else
-           Op = SparcOperand::CreateToken("%icc", S);
-         break;
--
--      case Sparc::FCC:
--        assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
--        Op = SparcOperand::CreateToken("%fcc0", S);
--        break;
-       }
-       break;
-     }
-@@ -637,6 +714,7 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
-
-   case AsmToken::Minus:
-   case AsmToken::Integer:
-+  case AsmToken::LParen:
-     if (!getParser().parseExpression(EVal, E))
-       Op = SparcOperand::CreateImm(EVal, S, E);
-     break;
-@@ -649,6 +727,10 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
-
-       const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
-                                                   getContext());
-+      if (isCall &&
-+          getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
-+        Res = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_WPLT30, Res,
-+                                  getContext());
-       Op = SparcOperand::CreateImm(Res, S, E);
-     }
-     break;
-@@ -657,6 +739,27 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
-   return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
- }
-
-+SparcAsmParser::OperandMatchResultTy SparcAsmParser::
-+parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
-+
-+  // parse (,a|,pn|,pt)+
-+
-+  while (getLexer().is(AsmToken::Comma)) {
-+
-+    Parser.Lex(); // Eat the comma
-+
-+    if (!getLexer().is(AsmToken::Identifier))
-+      return MatchOperand_ParseFail;
-+    StringRef modName = Parser.getTok().getString();
-+    if (modName == "a" || modName == "pn" || modName == "pt") {
-+      Operands.push_back(SparcOperand::CreateToken(modName,
-+                                                   Parser.getTok().getLoc()));
-+      Parser.Lex(); // eat the identifier.
-+    }
-+  }
-+  return MatchOperand_Success;
-+}
-+
- bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
-                                        unsigned &RegNo,
-                                        unsigned &RegKind)
-@@ -682,20 +785,46 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
-
-     if (name.equals("y")) {
-       RegNo = Sparc::Y;
--      RegKind = SparcOperand::rk_Y;
-+      RegKind = SparcOperand::rk_Special;
-       return true;
-     }
-
-+    if (name.substr(0, 3).equals_lower("asr")
-+        && !name.substr(3).getAsInteger(10, intVal)
-+        && intVal > 0 && intVal < 32) {
-+      RegNo = ASRRegs[intVal];
-+      RegKind = SparcOperand::rk_Special;
-+      return true;
-+    }
-+
-     if (name.equals("icc")) {
-       RegNo = Sparc::ICC;
--      RegKind = SparcOperand::rk_CCReg;
-+      RegKind = SparcOperand::rk_Special;
-       return true;
-     }
-
-+    if (name.equals("psr")) {
-+      RegNo = Sparc::PSR;
-+      RegKind = SparcOperand::rk_Special;
-+      return true;
-+    }
-+
-+    if (name.equals("wim")) {
-+      RegNo = Sparc::WIM;
-+      RegKind = SparcOperand::rk_Special;
-+      return true;
-+    }
-+
-+    if (name.equals("tbr")) {
-+      RegNo = Sparc::TBR;
-+      RegKind = SparcOperand::rk_Special;
-+      return true;
-+    }
-+
-     if (name.equals("xcc")) {
-       // FIXME:: check 64bit.
-       RegNo = Sparc::ICC;
--      RegKind = SparcOperand::rk_CCReg;
-+      RegKind = SparcOperand::rk_Special;
-       return true;
-     }
-
-@@ -704,8 +833,8 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
-         && !name.substr(3).getAsInteger(10, intVal)
-         && intVal < 4) {
-       // FIXME: check 64bit and  handle %fcc1 - %fcc3
--      RegNo = Sparc::FCC;
--      RegKind = SparcOperand::rk_CCReg;
-+      RegNo = Sparc::FCC0 + intVal;
-+      RegKind = SparcOperand::rk_Special;
-       return true;
-     }
-
-@@ -767,7 +896,32 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
-   return false;
- }
-
-+static bool hasGOTReference(const MCExpr *Expr) {
-+  switch (Expr->getKind()) {
-+  case MCExpr::Target:
-+    if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
-+      return hasGOTReference(SE->getSubExpr());
-+    break;
-
-+  case MCExpr::Constant:
-+    break;
-+
-+  case MCExpr::Binary: {
-+    const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
-+    return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
-+  }
-+
-+  case MCExpr::SymbolRef: {
-+    const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
-+    return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
-+  }
-+
-+  case MCExpr::Unary:
-+    return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
-+  }
-+  return false;
-+}
-+
- bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
-                                             SMLoc &EndLoc)
- {
-@@ -790,6 +944,23 @@ bool SparcAsmParser::matchSparcAsmModifiers(const MCEx
-   const MCExpr *subExpr;
-   if (Parser.parseParenExpression(subExpr, EndLoc))
-     return false;
-+
-+  bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
-+
-+  switch(VK) {
-+  default: break;
-+  case SparcMCExpr::VK_Sparc_LO:
-+    VK =  (hasGOTReference(subExpr)
-+           ? SparcMCExpr::VK_Sparc_PC10
-+           : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
-+    break;
-+  case SparcMCExpr::VK_Sparc_HI:
-+    VK =  (hasGOTReference(subExpr)
-+           ? SparcMCExpr::VK_Sparc_PC22
-+           : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
-+    break;
-+  }
-+
-   EVal = SparcMCExpr::Create(VK, subExpr, getContext());
-   return true;
- }
Index: patches/patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp
===================================================================
RCS file: patches/patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp
diff -N patches/patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp
--- patches/patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp 19 May 2015 05:33:39 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,325 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp,v 1.2 2015/05/19 05:33:39 ajacoutot Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
-r237580
-Add support for the Sparc implementation-defined "ASR" registers.
-
-r237581
-Sparc: Add the "alternate address space" load/store instructions.
-
-- Adds support for the asm syntax, which has an immediate integer
-  "ASI" (address space identifier) appearing after an address, before
-  a comma.
-
-- Adds the various-width load, store, and swap in alternate address
-  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
-  sta, swapa)
-
---- lib/Target/Sparc/Disassembler/SparcDisassembler.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/Sparc/Disassembler/SparcDisassembler.cpp Mon May 18 17:43:53 2015
-@@ -113,6 +113,19 @@ static const unsigned QFPRegDecoderTable[] = {
-   SP::Q6,  SP::Q14,  ~0U,  ~0U,
-   SP::Q7,  SP::Q15,  ~0U,  ~0U } ;
-
-+static const unsigned FCCRegDecoderTable[] = {
-+  SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
-+
-+static const unsigned ASRRegDecoderTable[] = {
-+  SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
-+  SP::ASR4,  SP::ASR5,  SP::ASR6,  SP::ASR7,
-+  SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
-+  SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
-+  SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
-+  SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
-+  SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
-+  SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
-+
- static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
-                                                unsigned RegNo,
-                                                uint64_t Address,
-@@ -174,7 +187,52 @@ static DecodeStatus DecodeQFPRegsRegisterClass(MCInst
-   return MCDisassembler::Success;
- }
-
-+static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-+                                               uint64_t Address,
-+                                               const void *Decoder) {
-+  if (RegNo > 3)
-+    return MCDisassembler::Fail;
-+  Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
-+  return MCDisassembler::Success;
-+}
-
-+static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-+                                               uint64_t Address,
-+                                               const void *Decoder) {
-+  if (RegNo > 31)
-+    return MCDisassembler::Fail;
-+  Inst.addOperand(MCOperand::CreateReg(ASRRegDecoderTable[RegNo]));
-+  return MCDisassembler::Success;
-+}
-+
-+
-+static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
-+                                  const void *Decoder);
-+static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
-+                                 const void *Decoder);
-+static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
-+                                  const void *Decoder);
-+static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
-+                                  const void *Decoder);
-+static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
-+                                   uint64_t Address, const void *Decoder);
-+static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
-+                                  uint64_t Address, const void *Decoder);
-+static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
-+                                   uint64_t Address, const void *Decoder);
-+static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
-+                                   uint64_t Address, const void *Decoder);
-+static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
-+                               uint64_t Address, const void *Decoder);
-+static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
-+                                 uint64_t Address, const void *Decoder);
-+static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
-+                               const void *Decoder);
-+static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
-+                                 const void *Decoder);
-+static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
-+                               const void *Decoder);
-+
- #include "SparcGenDisassemblerTables.inc"
-
- /// readInstruction - read four bytes from the MemoryObject
-@@ -225,4 +283,231 @@ SparcDisassembler::getInstruction(MCInst &instr,
-   }
-
-   return MCDisassembler::Fail;
-+}
-+
-+
-+typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
-+                                   const void *Decoder);
-+
-+static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
-+                              const void *Decoder,
-+                              bool isLoad, DecodeFunc DecodeRD) {
-+  unsigned rd = fieldFromInstruction(insn, 25, 5);
-+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
-+  bool isImm = fieldFromInstruction(insn, 13, 1);
-+  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
-+  unsigned asi = fieldFromInstruction(insn, 5, 8);
-+  unsigned rs2 = 0;
-+  unsigned simm13 = 0;
-+  if (isImm)
-+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
-+  else
-+    rs2 = fieldFromInstruction(insn, 0, 5);
-+
-+  DecodeStatus status;
-+  if (isLoad) {
-+    status = DecodeRD(MI, rd, Address, Decoder);
-+    if (status != MCDisassembler::Success)
-+      return status;
-+  }
-+
-+  // Decode rs1.
-+  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
-+  if (status != MCDisassembler::Success)
-+    return status;
-+
-+  // Decode imm|rs2.
-+  if (isImm)
-+    MI.addOperand(MCOperand::CreateImm(simm13));
-+  else {
-+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
-+    if (status != MCDisassembler::Success)
-+      return status;
-+  }
-+
-+  if (hasAsi)
-+    MI.addOperand(MCOperand::CreateImm(asi));
-+
-+  if (!isLoad) {
-+    status = DecodeRD(MI, rd, Address, Decoder);
-+    if (status != MCDisassembler::Success)
-+      return status;
-+  }
-+  return MCDisassembler::Success;
-+}
-+
-+static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
-+                                  const void *Decoder) {
-+  return DecodeMem(Inst, insn, Address, Decoder, true,
-+                   DecodeIntRegsRegisterClass);
-+}
-+
-+static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
-+                                 const void *Decoder) {
-+  return DecodeMem(Inst, insn, Address, Decoder, true,
-+                   DecodeFPRegsRegisterClass);
-+}
-+
-+static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
-+                                  const void *Decoder) {
-+  return DecodeMem(Inst, insn, Address, Decoder, true,
-+                   DecodeDFPRegsRegisterClass);
-+}
-+
-+static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
-+                                  const void *Decoder) {
-+  return DecodeMem(Inst, insn, Address, Decoder, true,
-+                   DecodeQFPRegsRegisterClass);
-+}
-+
-+static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
-+                                   uint64_t Address, const void *Decoder) {
-+  return DecodeMem(Inst, insn, Address, Decoder, false,
-+                   DecodeIntRegsRegisterClass);
-+}
-+
-+static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
-+                                  const void *Decoder) {
-+  return DecodeMem(Inst, insn, Address, Decoder, false,
-+                   DecodeFPRegsRegisterClass);
-+}
-+
-+static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
-+                                   uint64_t Address, const void *Decoder) {
-+  return DecodeMem(Inst, insn, Address, Decoder, false,
-+                   DecodeDFPRegsRegisterClass);
-+}
-+
-+static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
-+                                   uint64_t Address, const void *Decoder) {
-+  return DecodeMem(Inst, insn, Address, Decoder, false,
-+                   DecodeQFPRegsRegisterClass);
-+}
-+
-+static bool tryAddingSymbolicOperand(int64_t Value,  bool isBranch,
-+                                     uint64_t Address, uint64_t Offset,
-+                                     uint64_t Width, MCInst &MI,
-+                                     const void *Decoder) {
-+  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
-+  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
-+                                       Offset, Width);
-+}
-+
-+static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
-+                               uint64_t Address, const void *Decoder) {
-+  unsigned tgt = fieldFromInstruction(insn, 0, 30);
-+  tgt <<= 2;
-+  if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
-+                                0, 30, MI, Decoder))
-+    MI.addOperand(MCOperand::CreateImm(tgt));
-+  return MCDisassembler::Success;
-+}
-+
-+static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
-+                                 uint64_t Address, const void *Decoder) {
-+  unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
-+  MI.addOperand(MCOperand::CreateImm(tgt));
-+  return MCDisassembler::Success;
-+}
-+
-+static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
-+                               const void *Decoder) {
-+
-+  unsigned rd = fieldFromInstruction(insn, 25, 5);
-+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
-+  unsigned isImm = fieldFromInstruction(insn, 13, 1);
-+  unsigned rs2 = 0;
-+  unsigned simm13 = 0;
-+  if (isImm)
-+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
-+  else
-+    rs2 = fieldFromInstruction(insn, 0, 5);
-+
-+  // Decode RD.
-+  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
-+  if (status != MCDisassembler::Success)
-+    return status;
-+
-+  // Decode RS1.
-+  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
-+  if (status != MCDisassembler::Success)
-+    return status;
-+
-+  // Decode RS1 | SIMM13.
-+  if (isImm)
-+    MI.addOperand(MCOperand::CreateImm(simm13));
-+  else {
-+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
-+    if (status != MCDisassembler::Success)
-+      return status;
-+  }
-+  return MCDisassembler::Success;
-+}
-+
-+static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
-+                                 const void *Decoder) {
-+
-+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
-+  unsigned isImm = fieldFromInstruction(insn, 13, 1);
-+  unsigned rs2 = 0;
-+  unsigned simm13 = 0;
-+  if (isImm)
-+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
-+  else
-+    rs2 = fieldFromInstruction(insn, 0, 5);
-+
-+  // Decode RS1.
-+  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
-+  if (status != MCDisassembler::Success)
-+    return status;
-+
-+  // Decode RS2 | SIMM13.
-+  if (isImm)
-+    MI.addOperand(MCOperand::CreateImm(simm13));
-+  else {
-+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
-+    if (status != MCDisassembler::Success)
-+      return status;
-+  }
-+  return MCDisassembler::Success;
-+}
-+
-+static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
-+                               const void *Decoder) {
-+
-+  unsigned rd = fieldFromInstruction(insn, 25, 5);
-+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
-+  unsigned isImm = fieldFromInstruction(insn, 13, 1);
-+  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
-+  unsigned asi = fieldFromInstruction(insn, 5, 8);
-+  unsigned rs2 = 0;
-+  unsigned simm13 = 0;
-+  if (isImm)
-+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
-+  else
-+    rs2 = fieldFromInstruction(insn, 0, 5);
-+
-+  // Decode RD.
-+  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
-+  if (status != MCDisassembler::Success)
-+    return status;
-+
-+  // Decode RS1.
-+  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
-+  if (status != MCDisassembler::Success)
-+    return status;
-+
-+  // Decode RS1 | SIMM13.
-+  if (isImm)
-+    MI.addOperand(MCOperand::CreateImm(simm13));
-+  else {
-+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
-+    if (status != MCDisassembler::Success)
-+      return status;
-+  }
-+
-+  if (hasAsi)
-+    MI.addOperand(MCOperand::CreateImm(asi));
-+
-+  return MCDisassembler::Success;
- }
Index: patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp
===================================================================
RCS file: patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp
diff -N patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp
--- patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,99 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp.orig Sun Jun 15 02:44:25 2014
-+++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp Sun Jun 15 03:02:07 2014
-@@ -20,10 +20,22 @@
- #include "llvm/Support/raw_ostream.h"
- using namespace llvm;
-
-+// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
-+// namespace. But SPARC backend uses "SP" as its namespace.
-+namespace llvm {
-+namespace Sparc {
-+  using namespace SP;
-+}
-+}
-+
- #define GET_INSTRUCTION_NAME
- #define PRINT_ALIAS_INSTR
- #include "SparcGenAsmWriter.inc"
-
-+bool SparcInstPrinter::isV9() const {
-+  return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
-+}
-+
- void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
- {
-   OS << '%' << StringRef(getRegisterName(RegNo)).lower();
-@@ -49,7 +61,15 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCIn
-       return false;
-     switch (MI->getOperand(0).getReg()) {
-     default: return false;
--    case SP::G0: // jmp $addr
-+    case SP::G0: // jmp $addr | ret | retl
-+      if (MI->getOperand(2).isImm() &&
-+          MI->getOperand(2).getImm() == 8) {
-+        switch(MI->getOperand(1).getReg()) {
-+        default: break;
-+        case SP::I7: O << "\tret"; return true;
-+        case SP::O7: O << "\tretl"; return true;
-+        }
-+      }
-       O << "\tjmp "; printMemOperand(MI, 1, O);
-       return true;
-     case SP::O7: // call $addr
-@@ -57,7 +77,29 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCIn
-       return true;
-     }
-   }
-+  case SP::V9FCMPS:  case SP::V9FCMPD:  case SP::V9FCMPQ:
-+  case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
-+    if (isV9()
-+        || (MI->getNumOperands() != 3)
-+        || (!MI->getOperand(0).isReg())
-+        || (MI->getOperand(0).getReg() != SP::FCC0))
-+      return false;
-+    // if V8, skip printing %fcc0.
-+    switch(MI->getOpcode()) {
-+    default:
-+    case SP::V9FCMPS:  O << "\tfcmps "; break;
-+    case SP::V9FCMPD:  O << "\tfcmpd "; break;
-+    case SP::V9FCMPQ:  O << "\tfcmpq "; break;
-+    case SP::V9FCMPES: O << "\tfcmpes "; break;
-+    case SP::V9FCMPED: O << "\tfcmped "; break;
-+    case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
-+    }
-+    printOperand(MI, 1, O);
-+    O << ", ";
-+    printOperand(MI, 2, O);
-+    return true;
-   }
-+  }
- }
-
- void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
-@@ -109,11 +151,17 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI
-   switch (MI->getOpcode()) {
-   default: break;
-   case SP::FBCOND:
--  case SP::MOVFCCrr:
--  case SP::MOVFCCri:
--  case SP::FMOVS_FCC:
--  case SP::FMOVD_FCC:
--  case SP::FMOVQ_FCC:  // Make sure CC is a fp conditional flag.
-+  case SP::FBCONDA:
-+  case SP::BPFCC:
-+  case SP::BPFCCA:
-+  case SP::BPFCCNT:
-+  case SP::BPFCCANT:
-+  case SP::MOVFCCrr:  case SP::V9MOVFCCrr:
-+  case SP::MOVFCCri:  case SP::V9MOVFCCri:
-+  case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
-+  case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
-+  case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
-+    // Make sure CC is a fp conditional flag.
-     CC = (CC < 16) ? (CC + 16) : CC;
-     break;
-   }
Index: patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h
===================================================================
RCS file: patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h
diff -N patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h
--- patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,34 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/InstPrinter/SparcInstPrinter.h.orig Sun Jun 15 02:48:05 2014
-+++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.h Sun Jun 15 03:02:09 2014
-@@ -15,21 +15,25 @@
- #define SparcINSTPRINTER_H
-
- #include "llvm/MC/MCInstPrinter.h"
-+#include "llvm/MC/MCSubtargetInfo.h"
-
- namespace llvm {
-
- class MCOperand;
-
- class SparcInstPrinter : public MCInstPrinter {
-+  const MCSubtargetInfo &STI;
- public:
-  SparcInstPrinter(const MCAsmInfo &MAI,
-                   const MCInstrInfo &MII,
--                  const MCRegisterInfo &MRI)
--   : MCInstPrinter(MAI, MII, MRI) {}
-+                  const MCRegisterInfo &MRI,
-+                  const MCSubtargetInfo &sti)
-+   : MCInstPrinter(MAI, MII, MRI), STI(sti) {}
-
-   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
-   virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
-   bool printSparcAliasInstr(const MCInst *MI, raw_ostream &OS);
-+  bool isV9() const;
-
-   // Autogenerated by tblgen.
-   void printInstruction(const MCInst *MI, raw_ostream &O);
Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp
===================================================================
RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp
diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp
--- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,66 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp.orig Sun Jun 15 02:50:32 2014
-+++ lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp Sun Jun 15 03:01:21 2014
-@@ -11,8 +11,10 @@
- #include "MCTargetDesc/SparcFixupKinds.h"
- #include "MCTargetDesc/SparcMCTargetDesc.h"
- #include "llvm/MC/MCELFObjectWriter.h"
-+#include "llvm/MC/MCExpr.h"
- #include "llvm/MC/MCFixupKindInfo.h"
- #include "llvm/MC/MCObjectWriter.h"
-+#include "llvm/MC/MCValue.h"
- #include "llvm/Support/TargetRegistry.h"
-
- using namespace llvm;
-@@ -37,6 +39,12 @@ static unsigned adjustFixupValue(unsigned Kind, uint64
-   case Sparc::fixup_sparc_br19:
-     return (Value >> 2) & 0x7ffff;
-
-+  case Sparc::fixup_sparc_br16_2:
-+    return (Value >> 2) & 0xc000;
-+
-+  case Sparc::fixup_sparc_br16_14:
-+    return (Value >> 2) & 0x3fff;
-+
-   case Sparc::fixup_sparc_pc22:
-   case Sparc::fixup_sparc_got22:
-   case Sparc::fixup_sparc_tls_gd_hi22:
-@@ -104,6 +112,8 @@ namespace {
-         { "fixup_sparc_call30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
-         { "fixup_sparc_br22",      10,     22,  MCFixupKindInfo::FKF_IsPCRel },
-         { "fixup_sparc_br19",      13,     19,  MCFixupKindInfo::FKF_IsPCRel },
-+        { "fixup_sparc_br16_2",    10,      2,  MCFixupKindInfo::FKF_IsPCRel },
-+        { "fixup_sparc_br16_14",   18,     14,  MCFixupKindInfo::FKF_IsPCRel },
-         { "fixup_sparc_hi22",      10,     22,  0 },
-         { "fixup_sparc_lo10",      22,     10,  0 },
-         { "fixup_sparc_h44",       10,     22,  0 },
-@@ -154,6 +164,8 @@ namespace {
-       switch ((Sparc::Fixups)Fixup.getKind()) {
-       default: break;
-       case Sparc::fixup_sparc_wplt30:
-+        if (Target.getSymA()->getSymbol().isTemporary())
-+          return;
-       case Sparc::fixup_sparc_tls_gd_hi22:
-       case Sparc::fixup_sparc_tls_gd_lo10:
-       case Sparc::fixup_sparc_tls_gd_add:
-@@ -196,9 +208,14 @@ namespace {
-     }
-
-     bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
--      // FIXME: Zero fill for now.
--      for (uint64_t i = 0; i != Count; ++i)
--        OW->Write8(0);
-+      // Cannot emit NOP with size not multiple of 32 bits.
-+      if (Count % 4 != 0)
-+        return false;
-+
-+      uint64_t NumNops = Count / 4;
-+      for (uint64_t i = 0; i != NumNops; ++i)
-+        OW->Write32(0x01000000);
-+
-       return true;
-     }
-
Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h
===================================================================
RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h
diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h
--- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,17 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h.orig Sun Jun 15 02:50:50 2014
-+++ lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h Sun Jun 15 03:01:26 2014
-@@ -26,6 +26,10 @@ namespace llvm {
-       /// branches on icc/xcc
-       fixup_sparc_br19,
-
-+      /// fixup_sparc_bpr  - 16-bit fixup for bpr
-+      fixup_sparc_br16_2,
-+      fixup_sparc_br16_14,
-+
-       /// fixup_sparc_hi22  - 22-bit fixup corresponding to %hi(foo)
-       /// for sethi
-       fixup_sparc_hi22,
Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp
===================================================================
RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp
diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp
--- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp 11 Feb 2015 00:29:05 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,17 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp,v 1.2 2015/02/11 00:29:05 brad Exp $
-
-r225957
-Use the integrated assembler by default on SPARC.
-
---- lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp Mon Feb  2 11:12:32 2015
-@@ -43,8 +43,7 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) {
-   SunStyleELFSectionSwitchSyntax = true;
-   UsesELFSectionDirectiveForBSS = true;
-
--  if (TheTriple.getOS() == llvm::Triple::Solaris)
--    UseIntegratedAssembler = true;
-+  UseIntegratedAssembler = true;
- }
-
- const MCExpr*
Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp
===================================================================
RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp
diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp
--- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,63 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp.orig Sun Jun 15 02:44:51 2014
-+++ lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp Sun Jun 15 03:01:21 2014
-@@ -61,6 +61,12 @@ class SparcMCCodeEmitter : public MCCodeEmitter { (pub
-   unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
-                              SmallVectorImpl<MCFixup> &Fixups,
-                              const MCSubtargetInfo &STI) const;
-+  unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
-+                                      SmallVectorImpl<MCFixup> &Fixups,
-+                                      const MCSubtargetInfo &STI) const;
-+  unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
-+                                       SmallVectorImpl<MCFixup> &Fixups,
-+                                       const MCSubtargetInfo &STI) const;
-
- };
- } // end anonymous namespace
-@@ -173,13 +179,39 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo
-   if (MO.isReg() || MO.isImm())
-     return getMachineOpValue(MI, MO, Fixups, STI);
-
--  Sparc::Fixups fixup = Sparc::fixup_sparc_br22;
--  if (MI.getOpcode() == SP::BPXCC)
--    fixup = Sparc::fixup_sparc_br19;
-+  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
-+                                   (MCFixupKind)Sparc::fixup_sparc_br22));
-+  return 0;
-+}
-
-+unsigned SparcMCCodeEmitter::
-+getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
-+                           SmallVectorImpl<MCFixup> &Fixups,
-+                           const MCSubtargetInfo &STI) const {
-+  const MCOperand &MO = MI.getOperand(OpNo);
-+  if (MO.isReg() || MO.isImm())
-+    return getMachineOpValue(MI, MO, Fixups, STI);
-+
-   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
--                                   (MCFixupKind)fixup));
-+                                   (MCFixupKind)Sparc::fixup_sparc_br19));
-   return 0;
- }
-+unsigned SparcMCCodeEmitter::
-+getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
-+                           SmallVectorImpl<MCFixup> &Fixups,
-+                           const MCSubtargetInfo &STI) const {
-+  const MCOperand &MO = MI.getOperand(OpNo);
-+  if (MO.isReg() || MO.isImm())
-+    return getMachineOpValue(MI, MO, Fixups, STI);
-+
-+  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
-+                                   (MCFixupKind)Sparc::fixup_sparc_br16_2));
-+  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
-+                                   (MCFixupKind)Sparc::fixup_sparc_br16_14));
-+
-+  return 0;
-+}
-+
-+
-
- #include "SparcGenMCCodeEmitter.inc"
Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp
===================================================================
RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp
diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp
--- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,25 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp.orig Sun Jun 15 02:48:45 2014
-+++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Sun Jun 15 03:01:21 2014
-@@ -67,6 +67,9 @@ static MCRegisterInfo *createSparcMCRegisterInfo(Strin
- static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
-                                                    StringRef FS) {
-   MCSubtargetInfo *X = new MCSubtargetInfo();
-+  Triple TheTriple(TT);
-+  if (CPU.empty())
-+    CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8";
-   InitSparcMCSubtargetInfo(X, TT, CPU, FS);
-   return X;
- }
-@@ -150,7 +153,7 @@ static MCInstPrinter *createSparcMCInstPrinter(const T
-                                               const MCInstrInfo &MII,
-                                               const MCRegisterInfo &MRI,
-                                               const MCSubtargetInfo &STI) {
--  return new SparcInstPrinter(MAI, MII, MRI);
-+  return new SparcInstPrinter(MAI, MII, MRI, STI);
- }
-
- extern "C" void LLVMInitializeSparcTargetMC() {
Index: patches/patch-lib_Target_Sparc_SparcCodeEmitter_cpp
===================================================================
RCS file: patches/patch-lib_Target_Sparc_SparcCodeEmitter_cpp
diff -N patches/patch-lib_Target_Sparc_SparcCodeEmitter_cpp
--- patches/patch-lib_Target_Sparc_SparcCodeEmitter_cpp 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,36 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_SparcCodeEmitter_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/SparcCodeEmitter.cpp.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/Sparc/SparcCodeEmitter.cpp Sun Jun 15 04:00:05 2014
-@@ -76,6 +76,10 @@ class SparcCodeEmitter : public MachineFunctionPass {
-                                 unsigned) const;
-   unsigned getBranchTargetOpValue(const MachineInstr &MI,
-                                   unsigned) const;
-+  unsigned getBranchPredTargetOpValue(const MachineInstr &MI,
-+                                      unsigned) const;
-+  unsigned getBranchOnRegTargetOpValue(const MachineInstr &MI,
-+                                       unsigned) const;
-
-   void emitWord(unsigned Word);
-
-@@ -194,6 +198,18 @@ unsigned SparcCodeEmitter::getCallTargetOpValue(const
-
- unsigned SparcCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI,
-                                                   unsigned opIdx) const {
-+  const MachineOperand MO = MI.getOperand(opIdx);
-+  return getMachineOpValue(MI, MO);
-+}
-+
-+unsigned SparcCodeEmitter::getBranchPredTargetOpValue(const MachineInstr &MI,
-+                                                      unsigned opIdx) const {
-+  const MachineOperand MO = MI.getOperand(opIdx);
-+  return getMachineOpValue(MI, MO);
-+}
-+
-+unsigned SparcCodeEmitter::getBranchOnRegTargetOpValue(const MachineInstr &MI,
-+                                                       unsigned opIdx) const {
-   const MachineOperand MO = MI.getOperand(opIdx);
-   return getMachineOpValue(MI, MO);
- }
Index: patches/patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp
===================================================================
RCS file: patches/patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp
diff -N patches/patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp
--- patches/patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp 19 May 2015 05:33:39 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,31 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp,v 1.1 2015/05/19 05:33:39 ajacoutot Exp $
-
-r237580
-Add support for the Sparc implementation-defined "ASR" registers.
-
---- lib/Target/Sparc/SparcISelDAGToDAG.cpp.orig Mon May 18 16:07:47 2015
-+++ lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon May 18 16:07:50 2015
-@@ -168,8 +168,10 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
-     } else {
-       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
-     }
--    TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
--                                     CurDAG->getRegister(SP::G0, MVT::i32)), 0);
-+    TopPart = SDValue(CurDAG->getMachineNode(SP::WRASRrr, dl, MVT::i32,
-+                                 TopPart,
-+                                 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
-+    TopPart = CurDAG->getCopyToReg(TopPart, dl, SP::Y, TopPart, SDValue()).getValue(1);
-
-     // FIXME: Handle div by immediate.
-     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
-@@ -185,7 +187,9 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
-     SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
-                                          MulLHS, MulRHS);
-     // The high part is in the Y register.
--    return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
-+    return CurDAG->SelectNodeTo(N, SP::RDASR, MVT::i32,
-+                                CurDAG->getRegister(SP::Y, MVT::i32),
-+                                SDValue(Mul, 1));
-   }
-   }
-
Index: patches/patch-lib_Target_Sparc_SparcInstr64Bit_td
===================================================================
RCS file: patches/patch-lib_Target_Sparc_SparcInstr64Bit_td
diff -N patches/patch-lib_Target_Sparc_SparcInstr64Bit_td
--- patches/patch-lib_Target_Sparc_SparcInstr64Bit_td 19 May 2015 05:33:39 -0000 1.3
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,193 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_SparcInstr64Bit_td,v 1.3 2015/05/19 05:33:39 ajacoutot Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
-r208965
-Sparc: disable printing on longer "brX,pt" aliases
-
-r237581
-Sparc: Add the "alternate address space" load/store instructions.
-
-- Adds support for the asm syntax, which has an immediate integer
-  "ASI" (address space identifier) appearing after an address, before
-  a comma.
-
-- Adds the various-width load, store, and swap in alternate address
-  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
-  sta, swapa)
-
---- lib/Target/Sparc/SparcInstr64Bit.td.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/Sparc/SparcInstr64Bit.td Mon May 18 16:33:33 2015
-@@ -235,7 +235,8 @@ def UDIVXri : F3_2<2, 0b001101,
- let Predicates = [Is64Bit] in {
-
- // 64-bit loads.
--defm LDX   : Load<"ldx", 0b001011, load, I64Regs, i64>;
-+let DecoderMethod = "DecodeLoadInt" in
-+  defm LDX   : Load<"ldx", 0b001011, load, I64Regs, i64>;
-
- let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in
-   def TLS_LDXrr : F3_1<3, 0b001011,
-@@ -270,10 +271,12 @@ def : Pat<(i64 (extloadi32 ADDRrr:$addr)),  (LDrr ADDR
- def : Pat<(i64 (extloadi32 ADDRri:$addr)),  (LDri ADDRri:$addr)>;
-
- // Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
--defm LDSW   : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
-+let DecoderMethod = "DecodeLoadInt" in
-+  defm LDSW   : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
-
- // 64-bit stores.
--defm STX    : Store<"stx", 0b001110, store,  I64Regs, i64>;
-+let DecoderMethod = "DecodeStoreInt" in
-+  defm STX    : Store<"stx", 0b001110, store,  I64Regs, i64>;
-
- // Truncating stores from i64 are identical to the i32 stores.
- def : Pat<(truncstorei8  i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
-@@ -294,14 +297,6 @@ def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:
- // 64-bit Conditionals.
- //===----------------------------------------------------------------------===//
-
--// Conditional branch class on %xcc:
--class XBranchSP<dag ins, string asmstr, list<dag> pattern>
--  : F2_3<0b001, 0b10, (outs), ins, asmstr, pattern> {
--  let isBranch = 1;
--  let isTerminator = 1;
--  let hasDelaySlot = 1;
--}
--
- //
- // Flag-setting instructions like subcc and addcc set both icc and xcc flags.
- // The icc flags correspond to the 32-bit result, and the xcc are for the
-@@ -312,14 +307,12 @@ class XBranchSP<dag ins, string asmstr, list<dag> patt
-
- let Predicates = [Is64Bit] in {
-
--let Uses = [ICC] in
--def BPXCC : XBranchSP<(ins brtarget:$imm19, CCOp:$cond),
--                     "b$cond %xcc, $imm19",
--                     [(SPbrxcc bb:$imm19, imm:$cond)]>;
-+let Uses = [ICC], cc = 0b10 in
-+  defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>;
-
- // Conditional moves on %xcc.
- let Uses = [ICC], Constraints = "$f = $rd" in {
--let cc = 0b110 in {
-+let intcc = 1, cc = 0b10 in {
- def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
-                       (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
-                       "mov$cond %xcc, $rs2, $rd",
-@@ -332,7 +325,7 @@ def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
-                        (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;
- } // cc
-
--let opf_cc = 0b110 in {
-+let intcc = 1, opf_cc = 0b10 in {
- def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
-                       (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
-                       "fmovs$cond %xcc, $rs2, $rd",
-@@ -351,6 +344,84 @@ def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs
- } // opf_cc
- } // Uses, Constraints
-
-+// Branch On integer register with Prediction (BPr).
-+let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in
-+multiclass BranchOnReg<bits<3> cond, string OpcStr> {
-+  def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
-+             !strconcat(OpcStr, " $rs1, $imm16"), []>;
-+  def apt  : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
-+             !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
-+  def napn  : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
-+             !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
-+  def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
-+             !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
-+}
-+
-+multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
-+  def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
-+                  (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
-+  def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
-+                  (APT I64Regs:$rs1, bprtarget16:$imm16), 0>;
-+}
-+
-+defm BPZ   : BranchOnReg<0b001, "brz">;
-+defm BPLEZ : BranchOnReg<0b010, "brlez">;
-+defm BPLZ  : BranchOnReg<0b011, "brlz">;
-+defm BPNZ  : BranchOnReg<0b101, "brnz">;
-+defm BPGZ  : BranchOnReg<0b110, "brgz">;
-+defm BPGEZ : BranchOnReg<0b111, "brgez">;
-+
-+defm : bpr_alias<"brz",   BPZnapt,   BPZapt  >;
-+defm : bpr_alias<"brlez", BPLEZnapt, BPLEZapt>;
-+defm : bpr_alias<"brlz",  BPLZnapt,  BPLZapt >;
-+defm : bpr_alias<"brnz",  BPNZnapt,  BPNZapt >;
-+defm : bpr_alias<"brgz",  BPGZnapt,  BPGZapt >;
-+defm : bpr_alias<"brgez", BPGEZnapt, BPGEZapt>;
-+
-+// Move integer register on register condition (MOVr).
-+multiclass MOVR< bits<3> rcond,  string OpcStr> {
-+  def rr : F4_4r<0b101111, 0b00000, rcond, (outs I64Regs:$rd),
-+                   (ins I64Regs:$rs1, IntRegs:$rs2),
-+                   !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
-+
-+  def ri : F4_4i<0b101111, rcond, (outs I64Regs:$rd),
-+                   (ins I64Regs:$rs1, i64imm:$simm10),
-+                   !strconcat(OpcStr, " $rs1, $simm10, $rd"), []>;
-+}
-+
-+defm MOVRRZ  : MOVR<0b001, "movrz">;
-+defm MOVRLEZ : MOVR<0b010, "movrlez">;
-+defm MOVRLZ  : MOVR<0b011, "movrlz">;
-+defm MOVRNZ  : MOVR<0b101, "movrnz">;
-+defm MOVRGZ  : MOVR<0b110, "movrgz">;
-+defm MOVRGEZ : MOVR<0b111, "movrgez">;
-+
-+// Move FP register on integer register condition (FMOVr).
-+multiclass FMOVR<bits<3> rcond, string OpcStr> {
-+
-+  def S : F4_4r<0b110101, 0b00101, rcond,
-+                (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
-+                !strconcat(!strconcat("fmovrs", OpcStr)," $rs1, $rs2, $rd"),
-+                []>;
-+  def D : F4_4r<0b110101, 0b00110, rcond,
-+                (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
-+                !strconcat(!strconcat("fmovrd", OpcStr)," $rs1, $rs2, $rd"),
-+                []>;
-+  def Q : F4_4r<0b110101, 0b00111, rcond,
-+                (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
-+                !strconcat(!strconcat("fmovrq", OpcStr)," $rs1, $rs2, $rd"),
-+                []>, Requires<[HasHardQuad]>;
-+}
-+
-+let Predicates = [HasV9] in {
-+  defm FMOVRZ   : FMOVR<0b001, "z">;
-+  defm FMOVRLEZ : FMOVR<0b010, "lez">;
-+  defm FMOVRLZ  : FMOVR<0b011, "lz">;
-+  defm FMOVRNZ  : FMOVR<0b101, "nz">;
-+  defm FMOVRGZ  : FMOVR<0b110, "gz">;
-+  defm FMOVRGEZ : FMOVR<0b111, "gez">;
-+}
-+
- //===----------------------------------------------------------------------===//
- // 64-bit Floating Point Conversions.
- //===----------------------------------------------------------------------===//
-@@ -414,8 +485,8 @@ def SETHIXi : F2_1<0b100,
- }
-
- // ATOMICS.
--let Predicates = [Is64Bit], Constraints = "$swap = $rd" in {
--  def CASXrr: F3_1_asi<3, 0b111110, 0b10000000,
-+let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
-+  def CASXrr: F3_1_asi<3, 0b111110,
-                 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
-                                      I64Regs:$swap),
-                  "casx [$rs1], $rs2, $rd",
-@@ -470,6 +541,9 @@ def ATOMIC_SWAP_64 : Pseudo<(outs I64Regs:$rd),
-                             (ins ptr_rc:$addr, I64Regs:$rs2), "",
-                             [(set i64:$rd,
-                                   (atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
-+
-+let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in
-+ defm TXCC : TRAP<"%xcc">;
-
- // Global addresses, constant pool entries
- let Predicates = [Is64Bit] in {
Index: patches/patch-lib_Target_Sparc_SparcInstrAliases_td
===================================================================
RCS file: patches/patch-lib_Target_Sparc_SparcInstrAliases_td
diff -N patches/patch-lib_Target_Sparc_SparcInstrAliases_td
--- patches/patch-lib_Target_Sparc_SparcInstrAliases_td 19 May 2015 05:33:39 -0000 1.4
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,340 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_SparcInstrAliases_td,v 1.4 2015/05/19 05:33:39 ajacoutot Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
-r208966
-Sparc: disable printing of jmp/call aliases (C++ does it)
-
-These aliases are handled entirely in C++ and only having TableGen InstAliases
-for some of them was confusing LLVM.
-
-r236042
-Sparc: Add alternate aliases for conditional branch instructions.
-
---- lib/Target/Sparc/SparcInstrAliases.td.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/Sparc/SparcInstrAliases.td Mon May 18 19:45:10 2015
-@@ -13,32 +13,53 @@
- // Instruction aliases for conditional moves.
-
- // mov<cond> <ccreg> rs2, rd
--multiclass cond_mov_alias<string cond, int condVal, string ccreg,
-+multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
-                           Instruction movrr, Instruction movri,
-                           Instruction fmovs, Instruction fmovd> {
-
--  // mov<cond> (%icc|%xcc|%fcc0), rs2, rd
-+  // mov<cond> (%icc|%xcc), rs2, rd
-   def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
-                              ", $rs2, $rd"),
-                   (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
-
--  // mov<cond> (%icc|%xcc|%fcc0), simm11, rd
-+  // mov<cond> (%icc|%xcc), simm11, rd
-   def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
-                              ", $simm11, $rd"),
-                   (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
-
--  // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd
-+  // fmovs<cond> (%icc|%xcc), $rs2, $rd
-   def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
-                              ", $rs2, $rd"),
-                   (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
-
--  // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd
-+  // fmovd<cond> (%icc|%xcc), $rs2, $rd
-   def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
-                              ", $rs2, $rd"),
-                   (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
- }
-
-+// mov<cond> <ccreg> rs2, rd
-+multiclass fpcond_mov_alias<string cond, int condVal,
-+                           Instruction movrr, Instruction movri,
-+                           Instruction fmovs, Instruction fmovd> {
-
-+  // mov<cond> %fcc[0-3], rs2, rd
-+  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
-+                  (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
-+
-+  // mov<cond> %fcc[0-3], simm11, rd
-+  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
-+                  (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
-+
-+  // fmovs<cond> %fcc[0-3], $rs2, $rd
-+  def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
-+                  (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
-+
-+  // fmovd<cond> %fcc[0-3], $rs2, $rd
-+  def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
-+                  (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
-+}
-+
- // Instruction aliases for integer conditional branches and moves.
- multiclass int_cond_alias<string cond, int condVal> {
-
-@@ -46,15 +67,64 @@ multiclass int_cond_alias<string cond, int condVal> {
-   def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
-                   (BCOND brtarget:$imm, condVal)>;
-
-+  // b<cond>,a $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
-+                  (BCONDA brtarget:$imm, condVal)>;
-+
-+  // b<cond> %icc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
-+                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
-+
-+  // b<cond>,pt %icc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
-+                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
-+
-+  // b<cond>,a %icc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
-+                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
-+
-+  // b<cond>,a,pt %icc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
-+                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
-+
-+  // b<cond>,pn %icc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
-+                  (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
-+
-+  // b<cond>,a,pn %icc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
-+                  (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
-+
-   // b<cond> %xcc, $imm
-   def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
-                   (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
-
--  defm : cond_mov_alias<cond, condVal, " %icc",
-+  // b<cond>,pt %xcc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
-+                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
-+
-+  // b<cond>,a %xcc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
-+                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
-+
-+  // b<cond>,a,pt %xcc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
-+                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
-+
-+  // b<cond>,pn %xcc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
-+                  (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
-+
-+  // b<cond>,a,pn %xcc, $imm
-+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
-+                  (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
-+
-+
-+  defm : intcond_mov_alias<cond, condVal, " %icc",
-                             MOVICCrr, MOVICCri,
-                             FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
-
--  defm : cond_mov_alias<cond, condVal, " %xcc",
-+  defm : intcond_mov_alias<cond, condVal, " %xcc",
-                             MOVXCCrr, MOVXCCri,
-                             FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
-
-@@ -66,6 +136,59 @@ multiclass int_cond_alias<string cond, int condVal> {
-                   (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
-                   Requires<[Is64Bit, HasHardQuad]>;
-
-+  // t<cond> %icc, rs1 + rs2
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
-+                  (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
-+                  Requires<[HasV9]>;
-+
-+  // t<cond> %icc,  rs => t<cond> %icc, G0 + rs
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
-+                  (TICCrr G0, IntRegs:$rs2, condVal)>,
-+                  Requires<[HasV9]>;
-+
-+  // t<cond> %xcc, rs1 + rs2
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
-+                  (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
-+                  Requires<[HasV9]>;
-+
-+  // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
-+                  (TXCCrr G0, IntRegs:$rs2, condVal)>,
-+                  Requires<[HasV9]>;
-+
-+  // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
-+                  (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
-+
-+  // t<cond> rs=> t<cond> %icc,  G0 + rs2
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
-+                  (TICCrr G0, IntRegs:$rs2, condVal)>;
-+
-+  // t<cond> %icc, rs1 + imm
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
-+                  (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
-+                  Requires<[HasV9]>;
-+  // t<cond> %icc, imm => t<cond> %icc, G0 + imm
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
-+                  (TICCri G0, i32imm:$imm, condVal)>,
-+                  Requires<[HasV9]>;
-+  // t<cond> %xcc, rs1 + imm
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
-+                  (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
-+                  Requires<[HasV9]>;
-+  // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
-+                  (TXCCri G0, i32imm:$imm, condVal)>,
-+                  Requires<[HasV9]>;
-+
-+  // t<cond> rs1 + imm => t<cond> %icc, rs1 + imm
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
-+                  (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>;
-+
-+  // t<cond> imm => t<cond> %icc, G0 + imm
-+  def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
-+                  (TICCri G0, i32imm:$imm, condVal)>;
-+
- }
-
-
-@@ -76,20 +199,57 @@ multiclass fp_cond_alias<string cond, int condVal> {
-   def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
-                   (FBCOND brtarget:$imm, condVal), 0>;
-
--  defm : cond_mov_alias<cond, condVal, " %fcc0",
--                        MOVFCCrr, MOVFCCri,
--                        FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>;
-+  // fb<cond>,a $imm
-+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
-+                  (FBCONDA brtarget:$imm, condVal), 0>;
-
-+  // fb<cond> %fcc0, $imm
-+  def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
-+                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
-+                  Requires<[HasV9]>;
-+
-+  // fb<cond>,pt %fcc0, $imm
-+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
-+                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
-+                  Requires<[HasV9]>;
-+
-+  // fb<cond>,a %fcc0, $imm
-+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
-+                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
-+                  Requires<[HasV9]>;
-+
-+  // fb<cond>,a,pt %fcc0, $imm
-+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
-+                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
-+                   Requires<[HasV9]>;
-+
-+  // fb<cond>,pn %fcc0, $imm
-+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
-+                  (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
-+                   Requires<[HasV9]>;
-+
-+  // fb<cond>,a,pn %fcc0, $imm
-+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
-+                  (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
-+                  Requires<[HasV9]>;
-+
-+  defm : fpcond_mov_alias<cond, condVal,
-+                          V9MOVFCCrr, V9MOVFCCri,
-+                          V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
-+
-   // fmovq<cond> %fcc0, $rs2, $rd
--  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"),
--                  (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
-+  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
-+                  (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
-+                                                          condVal)>,
-                   Requires<[HasV9, HasHardQuad]>;
- }
-
- defm : int_cond_alias<"a",    0b1000>;
- defm : int_cond_alias<"n",    0b0000>;
- defm : int_cond_alias<"ne",   0b1001>;
-+defm : int_cond_alias<"nz",   0b1001>; // same as ne
- defm : int_cond_alias<"e",    0b0001>;
-+defm : int_cond_alias<"z",    0b0001>; // same as e
- defm : int_cond_alias<"g",    0b1010>;
- defm : int_cond_alias<"le",   0b0010>;
- defm : int_cond_alias<"ge",   0b1011>;
-@@ -97,12 +257,16 @@ defm : int_cond_alias<"l",    0b0011>;
- defm : int_cond_alias<"gu",   0b1100>;
- defm : int_cond_alias<"leu",  0b0100>;
- defm : int_cond_alias<"cc",   0b1101>;
-+defm : int_cond_alias<"geu",  0b1101>; // same as cc
- defm : int_cond_alias<"cs",   0b0101>;
-+defm : int_cond_alias<"lu",   0b0101>; // same as cs
- defm : int_cond_alias<"pos",  0b1110>;
- defm : int_cond_alias<"neg",  0b0110>;
- defm : int_cond_alias<"vc",   0b1111>;
- defm : int_cond_alias<"vs",   0b0111>;
-
-+defm : fp_cond_alias<"a",     0b0000>;
-+defm : fp_cond_alias<"n",     0b1000>;
- defm : fp_cond_alias<"u",     0b0111>;
- defm : fp_cond_alias<"g",     0b0110>;
- defm : fp_cond_alias<"ug",    0b0101>;
-@@ -110,7 +274,9 @@ defm : fp_cond_alias<"l",     0b0100>;
- defm : fp_cond_alias<"ul",    0b0011>;
- defm : fp_cond_alias<"lg",    0b0010>;
- defm : fp_cond_alias<"ne",    0b0001>;
-+defm : fp_cond_alias<"nz",    0b0001>; // same as ne
- defm : fp_cond_alias<"e",     0b1001>;
-+defm : fp_cond_alias<"z",     0b1001>; // same as e
- defm : fp_cond_alias<"ue",    0b1010>;
- defm : fp_cond_alias<"ge",    0b1011>;
- defm : fp_cond_alias<"uge",   0b1100>;
-@@ -118,16 +284,15 @@ defm : fp_cond_alias<"le",    0b1101>;
- defm : fp_cond_alias<"ule",   0b1110>;
- defm : fp_cond_alias<"o",     0b1111>;
-
--
- // Instruction aliases for JMPL.
-
- // jmp addr -> jmpl addr, %g0
--def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr)>;
--def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr)>;
-+def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
-+def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
-
- // call addr -> jmpl addr, %o7
--def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>;
--def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>;
-+def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
-+def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
-
- // retl -> RETL 8
- def : InstAlias<"retl", (RETL 8)>;
-@@ -140,3 +305,27 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0
-
- // mov simm13, rd -> or %g0, simm13, rd
- def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
-+
-+// restore -> restore %g0, %g0, %g0
-+def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
-+
-+def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
-+
-+def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
-+def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
-+
-+def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
-+def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
-+
-+
-+def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
-+def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
-+def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
-+                Requires<[HasHardQuad]>;
-+
-+def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
-+def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
-+                                                     DFPRegs:$rs2)>;
-+def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
-+                                                     QFPRegs:$rs2)>,
-+                Requires<[HasHardQuad]>;
Index: patches/patch-lib_Target_Sparc_SparcInstrFormats_td
===================================================================
RCS file: patches/patch-lib_Target_Sparc_SparcInstrFormats_td
diff -N patches/patch-lib_Target_Sparc_SparcInstrFormats_td
--- patches/patch-lib_Target_Sparc_SparcInstrFormats_td 19 May 2015 05:33:39 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,225 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_SparcInstrFormats_td,v 1.2 2015/05/19 05:33:39 ajacoutot Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
-r237581
-Sparc: Add the "alternate address space" load/store instructions.
-
-- Adds support for the asm syntax, which has an immediate integer
-  "ASI" (address space identifier) appearing after an address, before
-  a comma.
-
-- Adds the various-width load, store, and swap in alternate address
-  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
-  sta, swapa)
-
---- lib/Target/Sparc/SparcInstrFormats.td.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/Sparc/SparcInstrFormats.td Mon May 18 19:44:39 2015
-@@ -51,38 +51,51 @@ class F2_1<bits<3> op2Val, dag outs, dag ins, string a
-   let Inst{29-25} = rd;
- }
-
--class F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr,
-+class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
-            list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
-   bits<4>   cond;
--  bit       annul = 0;     // currently unused
--
-   let op2         = op2Val;
-
-   let Inst{29}    = annul;
-   let Inst{28-25} = cond;
- }
-
--class F2_3<bits<3> op2Val, bits<2> ccVal, dag outs, dag ins, string asmstr,
--           list<dag> pattern>
--   : InstSP<outs, ins, asmstr, pattern> {
--  bit      annul;
-+class F2_3<bits<3> op2Val, bit annul, bit pred,
-+           dag outs, dag ins, string asmstr, list<dag> pattern>
-+      : InstSP<outs, ins, asmstr, pattern> {
-+  bits<2>  cc;
-   bits<4>  cond;
--  bit      pred;
-   bits<19> imm19;
-
-   let op          = 0;    // op = 0
-
--  bit annul       = 0;    // currently unused
--  let pred        = 1;    // default is predict taken
--
-   let Inst{29}    = annul;
-   let Inst{28-25} = cond;
-   let Inst{24-22} = op2Val;
--  let Inst{21-20} = ccVal;
-+  let Inst{21-20} = cc;
-   let Inst{19}    = pred;
-   let Inst{18-0}  = imm19;
- }
-
-+class F2_4<bits<3> cond, bit annul, bit pred,
-+           dag outs, dag ins, string asmstr, list<dag> pattern>
-+      : InstSP<outs, ins, asmstr, pattern> {
-+  bits<16> imm16;
-+  bits<5>  rs1;
-+
-+  let op          = 0;    // op = 0
-+
-+  let Inst{29}    = annul;
-+  let Inst{28}    = 0;
-+  let Inst{27-25} = cond;
-+  let Inst{24-22} = 0b011;
-+  let Inst{21-20} = imm16{15-14};
-+  let Inst{19}    = pred;
-+  let Inst{18-14} = rs1;
-+  let Inst{13-0}  = imm16{13-0};
-+}
-+
-+
- //===----------------------------------------------------------------------===//
- // Format #3 instruction classes in the Sparc
- //===----------------------------------------------------------------------===//
-@@ -100,8 +113,9 @@ class F3<dag outs, dag ins, string asmstr, list<dag> p
-
- // Specific F3 classes: SparcV8 manual, page 44
- //
--class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins,
-+class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
-            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
-+  bits<8> asi;
-   bits<5> rs2;
-
-   let op         = opVal;
-@@ -113,8 +127,10 @@ class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8>
- }
-
- class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
--       list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins,
--                                                     asmstr, pattern>;
-+       list<dag> pattern> : F3_1_asi<opVal, op3val, outs, ins,
-+                                                     asmstr, pattern> {
-+  let asi = 0;
-+}
-
- class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
-            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
-@@ -159,7 +175,6 @@ class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opf
-
-   let op         = opVal;
-   let op3        = op3val;
--  let rd         = 0;
-
-   let Inst{13-5} = opfval;   // fp opcode
-   let Inst{4-0}  = rs2;
-@@ -218,44 +233,101 @@ class F4_1<bits<6> op3, dag outs, dag ins,
-             string asmstr, list<dag> pattern>
-       : F4<op3, outs, ins, asmstr, pattern> {
-
--  bits<3> cc;
-+  bit    intcc;
-+  bits<2> cc;
-   bits<4> cond;
-   bits<5> rs2;
-
-   let Inst{4-0}   = rs2;
--  let Inst{11}    = cc{0};
--  let Inst{12}    = cc{1};
-+  let Inst{12-11} = cc;
-   let Inst{13}    = 0;
-   let Inst{17-14} = cond;
--  let Inst{18}    = cc{2};
-+  let Inst{18}    = intcc;
-
- }
-
- class F4_2<bits<6> op3, dag outs, dag ins,
-             string asmstr, list<dag> pattern>
-       : F4<op3, outs, ins, asmstr, pattern> {
--  bits<3>  cc;
-+  bit      intcc;
-+  bits<2>  cc;
-   bits<4>  cond;
-   bits<11> simm11;
-
-   let Inst{10-0}  = simm11;
--  let Inst{11}    = cc{0};
--  let Inst{12}    = cc{1};
-+  let Inst{12-11} = cc;
-   let Inst{13}    = 1;
-   let Inst{17-14} = cond;
--  let Inst{18}    = cc{2};
-+  let Inst{18}    = intcc;
- }
-
- class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
-            string asmstr, list<dag> pattern>
-       : F4<op3, outs, ins, asmstr, pattern> {
-   bits<4> cond;
--  bits<3> opf_cc;
-+  bit     intcc;
-+  bits<2> opf_cc;
-   bits<5> rs2;
-
-   let Inst{18}     = 0;
-   let Inst{17-14}  = cond;
--  let Inst{13-11}  = opf_cc;
-+  let Inst{13}     = intcc;
-+  let Inst{12-11}  = opf_cc;
-   let Inst{10-5}   = opf_low;
-   let Inst{4-0}    = rs2;
-+}
-+
-+class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins,
-+            string asmstr, list<dag> pattern>
-+       : F4<op3, outs, ins, asmstr, pattern> {
-+  bits <5> rs1;
-+  bits <5> rs2;
-+  let Inst{18-14} = rs1;
-+  let Inst{13}    = 0;  // IsImm
-+  let Inst{12-10} = rcond;
-+  let Inst{9-5}   = opf_low;
-+  let Inst{4-0}   = rs2;
-+}
-+
-+
-+class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins,
-+            string asmstr, list<dag> pattern>
-+       : F4<op3, outs, ins, asmstr, pattern> {
-+  bits<5> rs1;
-+  bits<10> simm10;
-+  let Inst{18-14} = rs1;
-+  let Inst{13}    = 1;  // IsImm
-+  let Inst{12-10} = rcond;
-+  let Inst{9-0}   = simm10;
-+}
-+
-+
-+class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, string asmstr,
-+       list<dag> pattern>: F3<outs, ins, asmstr, pattern> {
-+
-+   bits<4> cond;
-+   bits<2> cc;
-+
-+   let op = 0b10;
-+   let rd{4} = 0;
-+   let rd{3-0} = cond;
-+   let op3 = op3Val;
-+   let Inst{13} = isimm;
-+   let Inst{12-11} = cc;
-+
-+}
-+
-+class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, string asmstr,
-+    list<dag> pattern>: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern> {
-+   bits<5> rs2;
-+
-+   let Inst{10-5} = 0;
-+   let Inst{4-0}  = rs2;
-+}
-+class TRAPSPri<bits<6> op3Val, dag outs, dag ins, string asmstr,
-+    list<dag> pattern>: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern> {
-+   bits<8> imm;
-+
-+   let Inst{10-8} = 0;
-+   let Inst{7-0}  = imm;
- }
Index: patches/patch-lib_Target_Sparc_SparcInstrInfo_td
===================================================================
RCS file: patches/patch-lib_Target_Sparc_SparcInstrInfo_td
diff -N patches/patch-lib_Target_Sparc_SparcInstrInfo_td
--- patches/patch-lib_Target_Sparc_SparcInstrInfo_td 19 May 2015 05:33:39 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,722 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_SparcInstrInfo_td,v 1.2 2015/05/19 05:33:39 ajacoutot Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
-r237580
-Add support for the Sparc implementation-defined "ASR" registers.
-
-r237581
-Sparc: Add the "alternate address space" load/store instructions.
-
-- Adds support for the asm syntax, which has an immediate integer
-  "ASI" (address space identifier) appearing after an address, before
-  a comma.
-
-- Adds the various-width load, store, and swap in alternate address
-  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
-  sta, swapa)
-
-r237582
-Sparc: Support PSR, TBR, WIM read/write instructions.
-
---- lib/Target/Sparc/SparcInstrInfo.td.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/Sparc/SparcInstrInfo.td Mon May 18 18:31:25 2015
-@@ -29,7 +29,8 @@ def Is64Bit : Predicate<"Subtarget.is64Bit()">;
-
- // HasV9 - This predicate is true when the target processor supports V9
- // instructions.  Note that the machine may be running in 32-bit mode.
--def HasV9   : Predicate<"Subtarget.isV9()">;
-+def HasV9   : Predicate<"Subtarget.isV9()">,
-+              AssemblerPredicate<"FeatureV9">;
-
- // HasNoV9 - This predicate is true when the target doesn't have V9
- // instructions.  Use of this is just a hack for the isel not having proper
-@@ -37,7 +38,12 @@ def HasV9   : Predicate<"Subtarget.isV9()">;
- def HasNoV9 : Predicate<"!Subtarget.isV9()">;
-
- // HasVIS - This is true when the target processor has VIS extensions.
--def HasVIS : Predicate<"Subtarget.isVIS()">;
-+def HasVIS : Predicate<"Subtarget.isVIS()">,
-+             AssemblerPredicate<"FeatureVIS">;
-+def HasVIS2 : Predicate<"Subtarget.isVIS2()">,
-+             AssemblerPredicate<"FeatureVIS2">;
-+def HasVIS3 : Predicate<"Subtarget.isVIS3()">,
-+             AssemblerPredicate<"FeatureVIS3">;
-
- // HasHardQuad - This is true when the target processor supports quad floating
- // point instructions.
-@@ -104,10 +110,23 @@ def brtarget : Operand<OtherVT> {
-   let EncoderMethod = "getBranchTargetOpValue";
- }
-
-+def bprtarget : Operand<OtherVT> {
-+  let EncoderMethod = "getBranchPredTargetOpValue";
-+}
-+
-+def bprtarget16 : Operand<OtherVT> {
-+  let EncoderMethod = "getBranchOnRegTargetOpValue";
-+}
-+
- def calltarget : Operand<i32> {
-   let EncoderMethod = "getCallTargetOpValue";
-+  let DecoderMethod = "DecodeCall";
- }
-
-+def simm13Op : Operand<i32> {
-+  let DecoderMethod = "DecodeSIMM13";
-+}
-+
- // Operand for printing out a condition code.
- let PrintMethod = "printCCOperand" in
-   def CCOp : Operand<i32>;
-@@ -246,7 +265,7 @@ multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
-                  (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
-                  !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
-   def ri  : F3_2<2, Op3Val,
--                 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
-+                 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
-                  !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
- }
-
-@@ -263,6 +282,17 @@ multiclass Load<string OpcStr, bits<6> Op3Val, SDPatte
-                  [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
- }
-
-+// LoadA multiclass - As above, but also define alternate address space variant
-+multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
-+                 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
-+             Load<OpcStr, Op3Val, OpNode, RC, Ty> {
-+  // TODO: The LD*Arr instructions are currently asm only; hooking up
-+  // CodeGen's address spaces to use these is a future task.
-+  def Arr  : F3_1_asi<3, LoadAOp3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
-+                !strconcat(OpcStr, "a [$addr] $asi, $dst"),
-+                []>;
-+}
-+
- // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
- multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
-            RegisterClass RC, ValueType Ty> {
-@@ -276,6 +306,16 @@ multiclass Store<string OpcStr, bits<6> Op3Val, SDPatt
-                  [(OpNode Ty:$rd, ADDRri:$addr)]>;
- }
-
-+multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
-+                  SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
-+             Store<OpcStr, Op3Val, OpNode, RC, Ty> {
-+  // TODO: The ST*Arr instructions are currently asm only; hooking up
-+  // CodeGen's address spaces to use these is a future task.
-+  def Arr  : F3_1_asi<3, StoreAOp3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
-+                  !strconcat(OpcStr, "a $rd, [$addr] $asi"),
-+                  []>;
-+}
-+
- //===----------------------------------------------------------------------===//
- // Instructions
- //===----------------------------------------------------------------------===//
-@@ -316,8 +356,8 @@ let isBarrier = 1, isTerminator = 1, rd = 0b1000, rs1
-   def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
-
- let rd = 0 in
--  def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
--                  "unimp $val", []>;
-+  def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
-+                  "unimp $imm22", []>;
-
- // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
- // instruction selection into a branch sequence.  This has to handle all
-@@ -344,7 +384,7 @@ let Uses = [ICC], usesCustomInserter = 1 in {
-             [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
- }
-
--let usesCustomInserter = 1, Uses = [FCC] in {
-+let usesCustomInserter = 1, Uses = [FCC0] in {
-
-   def SELECT_CC_Int_FCC
-    : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
-@@ -366,7 +406,8 @@ let usesCustomInserter = 1, Uses = [FCC] in {
- }
-
- // JMPL Instruction.
--let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
-+let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
-+    DecoderMethod = "DecodeJMPL" in {
-   def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
-                   "jmpl $addr, $dst", []>;
-   def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
-@@ -386,29 +427,47 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
-                   "jmp %i7+$val", []>;
- }
-
-+let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
-+     isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
-+  def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
-+                       "rett $addr", []>;
-+  def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
-+                       "rett $addr", []>;
-+}
-+
- // Section B.1 - Load Integer Instructions, p. 90
--defm LDSB : Load<"ldsb", 0b001001, sextloadi8,  IntRegs, i32>;
--defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
--defm LDUB : Load<"ldub", 0b000001, zextloadi8,  IntRegs, i32>;
--defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
--defm LD   : Load<"ld",   0b000000, load,        IntRegs, i32>;
-+let DecoderMethod = "DecodeLoadInt" in {
-+  defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8,  IntRegs, i32>;
-+  defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
-+  defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8,  IntRegs, i32>;
-+  defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
-+  defm LD   : LoadA<"ld",   0b000000, 0b010000, load,        IntRegs, i32>;
-+}
-
- // Section B.2 - Load Floating-point Instructions, p. 92
--defm LDF   : Load<"ld",  0b100000, load, FPRegs,  f32>;
--defm LDDF  : Load<"ldd", 0b100011, load, DFPRegs, f64>;
--defm LDQF  : Load<"ldq", 0b100010, load, QFPRegs, f128>,
--             Requires<[HasV9, HasHardQuad]>;
-+let DecoderMethod = "DecodeLoadFP" in
-+  defm LDF   : Load<"ld",  0b100000, load, FPRegs,  f32>;
-+let DecoderMethod = "DecodeLoadDFP" in
-+  defm LDDF  : Load<"ldd", 0b100011, load, DFPRegs, f64>;
-+let DecoderMethod = "DecodeLoadQFP" in
-+  defm LDQF  : Load<"ldq", 0b100010, load, QFPRegs, f128>,
-+               Requires<[HasV9, HasHardQuad]>;
-
- // Section B.4 - Store Integer Instructions, p. 95
--defm STB   : Store<"stb", 0b000101, truncstorei8,  IntRegs, i32>;
--defm STH   : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
--defm ST    : Store<"st",  0b000100, store,         IntRegs, i32>;
-+let DecoderMethod = "DecodeStoreInt" in {
-+  defm STB   : StoreA<"stb", 0b000101, 0b010101, truncstorei8,  IntRegs, i32>;
-+  defm STH   : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
-+  defm ST    : StoreA<"st",  0b000100, 0b010100, store,         IntRegs, i32>;
-+}
-
- // Section B.5 - Store Floating-point Instructions, p. 97
--defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
--defm STDF  : Store<"std", 0b100111, store,         DFPRegs, f64>;
--defm STQF  : Store<"stq", 0b100110, store,         QFPRegs, f128>,
--             Requires<[HasV9, HasHardQuad]>;
-+let DecoderMethod = "DecodeStoreFP" in
-+  defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
-+let DecoderMethod = "DecodeStoreDFP" in
-+  defm STDF  : Store<"std", 0b100111, store,         DFPRegs, f64>;
-+let DecoderMethod = "DecodeStoreQFP" in
-+  defm STQF  : Store<"stq", 0b100110, store,         QFPRegs, f128>,
-+               Requires<[HasV9, HasHardQuad]>;
-
- // Section B.9 - SETHI Instruction, p. 104
- def SETHIi: F2_1<0b100,
-@@ -422,42 +481,51 @@ let rd = 0, imm22 = 0 in
-   def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
-
- // Section B.11 - Logical Instructions, p. 106
--defm AND    : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
-+defm AND    : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
-
- def ANDNrr  : F3_1<2, 0b000101,
-                    (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
-                    "andn $rs1, $rs2, $rd",
-                    [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
- def ANDNri  : F3_2<2, 0b000101,
--                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
-+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
-                    "andn $rs1, $simm13, $rd", []>;
-
--defm OR     : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
-+defm OR     : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
-
- def ORNrr   : F3_1<2, 0b000110,
-                    (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
-                    "orn $rs1, $rs2, $rd",
-                    [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
- def ORNri   : F3_2<2, 0b000110,
--                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
-+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
-                    "orn $rs1, $simm13, $rd", []>;
--defm XOR    : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
-+defm XOR    : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
-
- def XNORrr  : F3_1<2, 0b000111,
-                    (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
-                    "xnor $rs1, $rs2, $rd",
-                    [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
- def XNORri  : F3_2<2, 0b000111,
--                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
-+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
-                    "xnor $rs1, $simm13, $rd", []>;
-
-+let Defs = [ICC] in {
-+  defm ANDCC  : F3_12np<"andcc",  0b010001>;
-+  defm ANDNCC : F3_12np<"andncc", 0b010101>;
-+  defm ORCC   : F3_12np<"orcc",   0b010010>;
-+  defm ORNCC  : F3_12np<"orncc",  0b010110>;
-+  defm XORCC  : F3_12np<"xorcc",  0b010011>;
-+  defm XNORCC : F3_12np<"xnorcc", 0b010111>;
-+}
-+
- // Section B.12 - Shift Instructions, p. 107
--defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
--defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
--defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
-+defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
-+defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
-+defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
-
- // Section B.13 - Add Instructions, p. 108
--defm ADD   : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
-+defm ADD   : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
-
- // "LEA" forms of add (patterns to make tblgen happy)
- let Predicates = [Is32Bit], isCodeGenOnly = 1 in
-@@ -467,26 +535,32 @@ let Predicates = [Is32Bit], isCodeGenOnly = 1 in
-                      [(set iPTR:$dst, ADDRri:$addr)]>;
-
- let Defs = [ICC] in
--  defm ADDCC  : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
-+  defm ADDCC  : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
-
-+let Uses = [ICC] in
-+  defm ADDC   : F3_12np<"addx", 0b001000>;
-+
- let Uses = [ICC], Defs = [ICC] in
--  defm ADDE  : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
-+  defm ADDE  : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
-
- // Section B.15 - Subtract Instructions, p. 110
--defm SUB    : F3_12  <"sub"  , 0b000100, sub, IntRegs, i32, i32imm>;
-+defm SUB    : F3_12  <"sub"  , 0b000100, sub, IntRegs, i32, simm13Op>;
- let Uses = [ICC], Defs = [ICC] in
--  defm SUBE   : F3_12  <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
-+  defm SUBE   : F3_12  <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
-
- let Defs = [ICC] in
--  defm SUBCC  : F3_12  <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
-+  defm SUBCC  : F3_12  <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
-
-+let Uses = [ICC] in
-+  defm SUBC   : F3_12np <"subx", 0b001100>;
-+
- let Defs = [ICC], rd = 0 in {
-   def CMPrr   : F3_1<2, 0b010100,
-                      (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
-                      "cmp $rs1, $rs2",
-                      [(SPcmpicc i32:$rs1, i32:$rs2)]>;
-   def CMPri   : F3_2<2, 0b010100,
--                     (outs), (ins IntRegs:$rs1, i32imm:$simm13),
-+                     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
-                      "cmp $rs1, $simm13",
-                      [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
- }
-@@ -494,15 +568,25 @@ let Defs = [ICC], rd = 0 in {
- // Section B.18 - Multiply Instructions, p. 113
- let Defs = [Y] in {
-   defm UMUL : F3_12np<"umul", 0b001010>;
--  defm SMUL : F3_12  <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
-+  defm SMUL : F3_12  <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
- }
-
-+let Defs = [Y, ICC] in {
-+  defm UMULCC : F3_12np<"umulcc", 0b011010>;
-+  defm SMULCC : F3_12np<"smulcc", 0b011011>;
-+}
-+
- // Section B.19 - Divide Instructions, p. 115
- let Defs = [Y] in {
-   defm UDIV : F3_12np<"udiv", 0b001110>;
-   defm SDIV : F3_12np<"sdiv", 0b001111>;
- }
-
-+let Defs = [Y, ICC] in {
-+  defm UDIVCC : F3_12np<"udivcc", 0b011110>;
-+  defm SDIVCC : F3_12np<"sdivcc", 0b011111>;
-+}
-+
- // Section B.20 - SAVE and RESTORE, p. 117
- defm SAVE    : F3_12np<"save"   , 0b111100>;
- defm RESTORE : F3_12np<"restore", 0b111101>;
-@@ -511,7 +595,7 @@ defm RESTORE : F3_12np<"restore", 0b111101>;
-
- // unconditional branch class.
- class BranchAlways<dag ins, string asmstr, list<dag> pattern>
--  : F2_2<0b010, (outs), ins, asmstr, pattern> {
-+  : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
-   let isBranch     = 1;
-   let isTerminator = 1;
-   let hasDelaySlot = 1;
-@@ -521,14 +605,36 @@ class BranchAlways<dag ins, string asmstr, list<dag> p
- let cond = 8 in
-   def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
-
-+
-+let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
-+
- // conditional branch class:
- class BranchSP<dag ins, string asmstr, list<dag> pattern>
-- : F2_2<0b010, (outs), ins, asmstr, pattern> {
--  let isBranch = 1;
--  let isTerminator = 1;
--  let hasDelaySlot = 1;
-+ : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
-+
-+// conditional branch with annul class:
-+class BranchSPA<dag ins, string asmstr, list<dag> pattern>
-+ : F2_2<0b010, 1, (outs), ins, asmstr, pattern>;
-+
-+// Conditional branch class on %icc|%xcc with predication:
-+multiclass IPredBranch<string regstr, list<dag> CCPattern> {
-+  def CC    : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
-+                  !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
-+                   CCPattern>;
-+  def CCA   : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
-+                  !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
-+                   []>;
-+  def CCNT  : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
-+                   !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
-+                   []>;
-+  def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
-+                   !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
-+                   []>;
- }
-
-+} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
-+
-+
- // Indirect branch instructions.
- let isTerminator = 1, isBarrier = 1,  hasDelaySlot = 1, isBranch =1,
-      isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
-@@ -542,33 +648,64 @@ let isTerminator = 1, isBarrier = 1,  hasDelaySlot = 1
-                    [(brind ADDRri:$ptr)]>;
- }
-
--let Uses = [ICC] in
-+let Uses = [ICC] in {
-   def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
-                          "b$cond $imm22",
-                         [(SPbricc bb:$imm22, imm:$cond)]>;
-+  def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
-+                         "b$cond,a $imm22", []>;
-
-+  let Predicates = [HasV9], cc = 0b00 in
-+    defm BPI : IPredBranch<"%icc", []>;
-+}
-+
- // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
-
-+let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
-+
- // floating-point conditional branch class:
- class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
-- : F2_2<0b110, (outs), ins, asmstr, pattern> {
--  let isBranch = 1;
--  let isTerminator = 1;
--  let hasDelaySlot = 1;
-+ : F2_2<0b110, 0, (outs), ins, asmstr, pattern>;
-+
-+// floating-point conditional branch with annul class:
-+class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
-+ : F2_2<0b110, 1, (outs), ins, asmstr, pattern>;
-+
-+// Conditional branch class on %fcc0-%fcc3 with predication:
-+multiclass FPredBranch {
-+  def CC    : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
-+                                         FCCRegs:$cc),
-+                  "fb$cond $cc, $imm19", []>;
-+  def CCA   : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
-+                                         FCCRegs:$cc),
-+                  "fb$cond,a $cc, $imm19", []>;
-+  def CCNT  : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
-+                                         FCCRegs:$cc),
-+                  "fb$cond,pn $cc, $imm19", []>;
-+  def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
-+                                         FCCRegs:$cc),
-+                  "fb$cond,a,pn $cc, $imm19", []>;
- }
-+} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
-
--let Uses = [FCC] in
-+let Uses = [FCC0] in {
-   def FBCOND  : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
-                               "fb$cond $imm22",
-                               [(SPbrfcc bb:$imm22, imm:$cond)]>;
-+  def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
-+                             "fb$cond,a $imm22", []>;
-+}
-
-+let Predicates = [HasV9] in
-+  defm BPF : FPredBranch;
-
-+
- // Section B.24 - Call and Link Instruction, p. 125
- // This is the only Format 1 instruction
- let Uses = [O6],
-     hasDelaySlot = 1, isCall = 1 in {
--  def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
--                    "call $dst", []> {
-+  def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
-+                    "call $disp", []> {
-     bits<30> disp;
-     let op = 1;
-     let Inst{29-0} = disp;
-@@ -588,20 +725,37 @@ let Uses = [O6],
- }
-
- // Section B.28 - Read State Register Instructions
--let Uses = [Y], rs1 = 0, rs2 = 0 in
--  def RDY : F3_1<2, 0b101000,
--                 (outs IntRegs:$dst), (ins),
--                 "rd %y, $dst", []>;
-+let rs2 = 0 in
-+  def RDASR : F3_1<2, 0b101000,
-+                 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
-+                 "rd $rs1, $rd", []>;
-
--// Section B.29 - Write State Register Instructions
--let Defs = [Y], rd = 0 in {
--  def WRYrr : F3_1<2, 0b110000,
--                   (outs), (ins IntRegs:$b, IntRegs:$c),
--                   "wr $b, $c, %y", []>;
--  def WRYri : F3_2<2, 0b110000,
--                   (outs), (ins IntRegs:$b, i32imm:$c),
--                   "wr $b, $c, %y", []>;
-+// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
-+let Predicates = [HasNoV9] in {
-+  let rs2 = 0, rs1 = 0, Uses=[PSR] in
-+    def RDPSR : F3_1<2, 0b101001,
-+     (outs IntRegs:$rd), (ins),
-+     "rd %psr, $rd", []>;
-+
-+  let rs2 = 0, rs1 = 0, Uses=[WIM] in
-+    def RDWIM : F3_1<2, 0b101010,
-+     (outs IntRegs:$rd), (ins),
-+     "rd %wim, $rd", []>;
-+
-+  let rs2 = 0, rs1 = 0, Uses=[TBR] in
-+    def RDTBR : F3_1<2, 0b101011,
-+     (outs IntRegs:$rd), (ins),
-+     "rd %tbr, $rd", []>;
- }
-+
-+// Section B.29 - Write State Register Instructions
-+def WRASRrr : F3_1<2, 0b110000,
-+                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
-+                 "wr $rs1, $rs2, $rd", []>;
-+def WRASRri : F3_2<2, 0b110000,
-+                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
-+                 "wr $rs1, $simm13, $rd", []>;
-+
- // Convert Integer to Floating-point Instructions, p. 141
- def FITOS : F3_3u<2, 0b110100, 0b011000100,
-                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
-@@ -617,6 +771,36 @@ def FITOQ : F3_3u<2, 0b110100, 0b011001100,
-                  [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
-                  Requires<[HasHardQuad]>;
-
-+// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
-+let Predicates = [HasNoV9] in {
-+  let Defs = [PSR], rd=0 in {
-+    def WRPSRrr : F3_1<2, 0b110001,
-+     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
-+     "wr $rs1, $rs2, %psr", []>;
-+    def WRPSRri : F3_2<2, 0b110001,
-+     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
-+     "wr $rs1, $simm13, %psr", []>;
-+  }
-+
-+  let Defs = [WIM], rd=0 in {
-+    def WRWIMrr : F3_1<2, 0b110010,
-+     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
-+     "wr $rs1, $rs2, %wim", []>;
-+    def WRWIMri : F3_2<2, 0b110010,
-+     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
-+     "wr $rs1, $simm13, %wim", []>;
-+  }
-+
-+  let Defs = [TBR], rd=0 in {
-+    def WRTBRrr : F3_1<2, 0b110011,
-+     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
-+     "wr $rs1, $rs2, %tbr", []>;
-+    def WRTBRri : F3_2<2, 0b110011,
-+     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
-+     "wr $rs1, $simm13, %tbr", []>;
-+  }
-+}
-+
- // Convert Floating-point to Integer Instructions, p. 142
- def FSTOI : F3_3u<2, 0b110100, 0b011010001,
-                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
-@@ -771,7 +955,7 @@ def FDIVQ  : F3_3<2, 0b110100, 0b001001111,
- // This behavior is modeled with a forced noop after the instruction in
- // DelaySlotFiller.
-
--let Defs = [FCC] in {
-+let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
-   def FCMPS  : F3_3c<2, 0b110101, 0b001010001,
-                    (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
-                    "fcmps $rs1, $rs2",
-@@ -823,7 +1007,7 @@ let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
- // V9 Conditional Moves.
- let Predicates = [HasV9], Constraints = "$f = $rd" in {
-   // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
--  let Uses = [ICC], cc = 0b100 in {
-+  let Uses = [ICC], intcc = 1, cc = 0b00 in {
-     def MOVICCrr
-       : F4_1<0b101100, (outs IntRegs:$rd),
-              (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
-@@ -838,7 +1022,7 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in
-                     (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
-   }
-
--  let Uses = [FCC], cc = 0b000 in {
-+  let Uses = [FCC0], intcc = 0, cc = 0b00 in {
-     def MOVFCCrr
-       : F4_1<0b101100, (outs IntRegs:$rd),
-              (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
-@@ -852,7 +1036,7 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in
-                     (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
-   }
-
--  let Uses = [ICC], opf_cc = 0b100 in {
-+  let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
-     def FMOVS_ICC
-       : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
-              (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
-@@ -871,7 +1055,7 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in
-                Requires<[HasHardQuad]>;
-   }
-
--  let Uses = [FCC], opf_cc = 0b000 in {
-+  let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
-     def FMOVS_FCC
-       : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
-              (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
-@@ -921,6 +1105,59 @@ let Predicates = [HasV9] in {
-                    Requires<[HasHardQuad]>;
- }
-
-+// Floating-point compare instruction with %fcc0-%fcc3.
-+def V9FCMPS  : F3_3c<2, 0b110101, 0b001010001,
-+               (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
-+               "fcmps $rd, $rs1, $rs2", []>;
-+def V9FCMPD  : F3_3c<2, 0b110101, 0b001010010,
-+                (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                "fcmpd $rd, $rs1, $rs2", []>;
-+def V9FCMPQ  : F3_3c<2, 0b110101, 0b001010011,
-+                (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
-+                "fcmpq $rd, $rs1, $rs2", []>,
-+                 Requires<[HasHardQuad]>;
-+
-+let hasSideEffects = 1 in {
-+  def V9FCMPES  : F3_3c<2, 0b110101, 0b001010101,
-+                   (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
-+                   "fcmpes $rd, $rs1, $rs2", []>;
-+  def V9FCMPED  : F3_3c<2, 0b110101, 0b001010110,
-+                   (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                   "fcmped $rd, $rs1, $rs2", []>;
-+  def V9FCMPEQ  : F3_3c<2, 0b110101, 0b001010111,
-+                   (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
-+                   "fcmpeq $rd, $rs1, $rs2", []>,
-+                   Requires<[HasHardQuad]>;
-+}
-+
-+// Floating point conditional move instrucitons with %fcc0-%fcc3.
-+let Predicates = [HasV9] in {
-+  let Constraints = "$f = $rd", intcc = 0 in {
-+    def V9MOVFCCrr
-+      : F4_1<0b101100, (outs IntRegs:$rd),
-+             (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
-+             "mov$cond $cc, $rs2, $rd", []>;
-+    def V9MOVFCCri
-+      : F4_2<0b101100, (outs IntRegs:$rd),
-+             (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
-+             "mov$cond $cc, $simm11, $rd", []>;
-+    def V9FMOVS_FCC
-+      : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
-+             (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
-+             "fmovs$cond $opf_cc, $rs2, $rd", []>;
-+    def V9FMOVD_FCC
-+      : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
-+             (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
-+             "fmovd$cond $opf_cc, $rs2, $rd", []>;
-+    def V9FMOVQ_FCC
-+      : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
-+             (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
-+             "fmovq$cond $opf_cc, $rs2, $rd", []>,
-+             Requires<[HasHardQuad]>;
-+  } // Constraints = "$f = $rd", ...
-+} // let Predicates = [hasV9]
-+
-+
- // POPCrr - This does a ctpop of a 64-bit register.  As such, we have to clear
- // the top 32-bits before using it.  To do this clearing, we use a SRLri X,0.
- let rs1 = 0 in
-@@ -935,10 +1172,10 @@ let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0
-   def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
-
- let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
-- def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
-+ def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
-                     "membar $simm13", []>;
-
--let Constraints = "$val = $dst" in {
-+let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
-   def SWAPrr : F3_1<3, 0b001111,
-                  (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
-                  "swap [$addr], $dst",
-@@ -947,16 +1184,48 @@ let Constraints = "$val = $dst" in {
-                  (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
-                  "swap [$addr], $dst",
-                  [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
-+  def SWAPArr : F3_1_asi<3, 0b011111,
-+                 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
-+                 "swapa [$addr] $asi, $dst",
-+                 [/*FIXME: pattern?*/]>;
- }
-
--let Predicates = [HasV9], Constraints = "$swap = $rd" in
--  def CASrr: F3_1_asi<3, 0b111100, 0b10000000,
-+// TODO: Should add a CASArr variant. In fact, the CAS instruction,
-+// unlike other instructions, only comes in a form which requires an
-+// ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the
-+// default unprivileged ASI for SparcV9.  (Also of note: some modern
-+// SparcV8 implementations provide CASA as an extension, but require
-+// the use of SparcV8's default ASI, 0xA ("User Data") instead.)
-+let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
-+  def CASrr: F3_1_asi<3, 0b111100,
-                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
-                                      IntRegs:$swap),
-                  "cas [$rs1], $rs2, $rd",
-                  [(set i32:$rd,
-                      (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
-
-+let Defs = [ICC] in {
-+defm TADDCC   : F3_12np<"taddcc",   0b100000>;
-+defm TSUBCC   : F3_12np<"tsubcc",   0b100001>;
-+
-+let hasSideEffects = 1 in {
-+  defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
-+  defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
-+}
-+}
-+
-+multiclass TRAP<string regStr> {
-+  def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
-+                                       CCOp:$cond),
-+              !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
-+  def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
-+                                      CCOp:$cond),
-+              !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
-+}
-+
-+let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
-+  defm TICC : TRAP<"%icc">;
-+
- //===----------------------------------------------------------------------===//
- // Non-Instruction Patterns
- //===----------------------------------------------------------------------===//
-@@ -1032,4 +1301,5 @@ def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri
-
-
- include "SparcInstr64Bit.td"
-+include "SparcInstrVIS.td"
- include "SparcInstrAliases.td"
Index: patches/patch-lib_Target_Sparc_SparcInstrVIS_td
===================================================================
RCS file: patches/patch-lib_Target_Sparc_SparcInstrVIS_td
diff -N patches/patch-lib_Target_Sparc_SparcInstrVIS_td
--- patches/patch-lib_Target_Sparc_SparcInstrVIS_td 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,270 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_SparcInstrVIS_td,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/SparcInstrVIS.td.orig Sun Jun 15 02:52:10 2014
-+++ lib/Target/Sparc/SparcInstrVIS.td Sun Jun 15 02:57:59 2014
-@@ -0,0 +1,263 @@
-+//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
-+//
-+//                     The LLVM Compiler Infrastructure
-+//
-+// This file is distributed under the University of Illinois Open Source
-+// License. See LICENSE.TXT for details.
-+//
-+//===----------------------------------------------------------------------===//
-+//
-+// This file contains instruction formats, definitions and patterns needed for
-+// VIS, VIS II, VIS II instructions on SPARC.
-+//===----------------------------------------------------------------------===//
-+
-+// VIS Instruction Format.
-+class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
-+      list<dag> pattern>
-+      : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
-+
-+class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
-+       : VISInstFormat<opfval,
-+        (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
-+        !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
-+
-+// VIS Instruction with integer destination register.
-+class VISInstID<bits<9> opfval, string OpcStr>
-+       : VISInstFormat<opfval,
-+        (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+        !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
-+
-+// For VIS Instructions with no operand.
-+let rd = 0, rs1 = 0, rs2 = 0 in
-+class VISInst0<bits<9> opfval, string asmstr>
-+       : VISInstFormat<opfval, (outs), (ins), asmstr, []>;
-+
-+// For VIS Instructions with only rs1, rd operands.
-+let rs2 = 0 in
-+class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
-+       : VISInstFormat<opfval,
-+        (outs RC:$rd), (ins RC:$rs1),
-+        !strconcat(OpcStr, " $rs1, $rd"), []>;
-+
-+// For VIS Instructions with only rs2, rd operands.
-+let rs1 = 0 in
-+class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
-+       : VISInstFormat<opfval,
-+        (outs RC:$rd), (ins RC:$rs2),
-+        !strconcat(OpcStr, " $rs2, $rd"), []>;
-+
-+// For VIS Instructions with only rd operand.
-+let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
-+class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
-+       : VISInstFormat<opfval,
-+        (outs RC:$rd), (ins RC:$f),
-+        !strconcat(OpcStr, " $rd"), []>;
-+
-+// VIS 1 Instructions
-+let Predicates = [HasVIS] in {
-+
-+def FPADD16     : VISInst<0b001010000, "fpadd16">;
-+def FPADD16S    : VISInst<0b001010001, "fpadd16s">;
-+def FPADD32     : VISInst<0b001010010, "fpadd32">;
-+def FPADD32S    : VISInst<0b001010011, "fpadd32s">;
-+def FPSUB16     : VISInst<0b001010100, "fpsub16">;
-+def FPSUB16S    : VISInst<0b001010101, "fpsub16S">;
-+def FPSUB32     : VISInst<0b001010110, "fpsub32">;
-+def FPSUB32S    : VISInst<0b001010111, "fpsub32S">;
-+
-+def FPACK16     : VISInst2<0b000111011, "fpack16">;
-+def FPACK32     : VISInst <0b000111010, "fpack32">;
-+def FPACKFIX    : VISInst2<0b000111101, "fpackfix">;
-+def FEXPAND     : VISInst2<0b001001101, "fexpand">;
-+def FPMERGE     : VISInst <0b001001011, "fpmerge">;
-+
-+def FMUL8X16    : VISInst<0b00110001, "fmul8x16">;
-+def FMUL8X16AU  : VISInst<0b00110011, "fmul8x16au">;
-+def FMUL8X16AL  : VISInst<0b00110101, "fmul8x16al">;
-+def FMUL8SUX16  : VISInst<0b00110110, "fmul8sux16">;
-+def FMUL8ULX16  : VISInst<0b00110111, "fmul8ulx16">;
-+def FMULD8SUX16 : VISInst<0b00111000, "fmuld8sux16">;
-+def FMULD8ULX16 : VISInst<0b00111001, "fmuld8ulx16">;
-+
-+def ALIGNADDR   : VISInst<0b000011000, "alignaddr", I64Regs>;
-+def ALIGNADDRL  : VISInst<0b000011010, "alignaddrl", I64Regs>;
-+def FALIGNADATA : VISInst<0b001001000, "faligndata">;
-+
-+def FZERO       : VISInstD<0b001100000, "fzero">;
-+def FZEROS      : VISInstD<0b001100001, "fzeros", FPRegs>;
-+def FONE        : VISInstD<0b001111110, "fone">;
-+def FONES       : VISInstD<0b001111111, "fones", FPRegs>;
-+def FSRC1       : VISInst1<0b001110100, "fsrc1">;
-+def FSRC1S      : VISInst1<0b001110101, "fsrc1s", FPRegs>;
-+def FSRC2       : VISInst2<0b001111000, "fsrc2">;
-+def FSRC2S      : VISInst2<0b001111001, "fsrc2s", FPRegs>;
-+def FNOT1       : VISInst1<0b001101010, "fnot1">;
-+def FNOT1S      : VISInst1<0b001101011, "fnot1s", FPRegs>;
-+def FNOT2       : VISInst2<0b001100110, "fnot2">;
-+def FNOT2S      : VISInst2<0b001100111, "fnot2s", FPRegs>;
-+def FOR         : VISInst<0b001111100,  "for">;
-+def FORS        : VISInst<0b001111101,  "fors",  FPRegs>;
-+def FNOR        : VISInst<0b001100010,  "fnor">;
-+def FNORS       : VISInst<0b001100011,  "fnors", FPRegs>;
-+def FAND        : VISInst<0b001110000,  "fand">;
-+def FANDS       : VISInst<0b001110001,  "fands", FPRegs>;
-+def FNAND       : VISInst<0b001101110,  "fnand">;
-+def FNANDS      : VISInst<0b001101111,  "fnands", FPRegs>;
-+def FXOR        : VISInst<0b001101100,  "fxor">;
-+def FXORS       : VISInst<0b001101101,  "fxors", FPRegs>;
-+def FXNOR       : VISInst<0b001110010,  "fxnor">;
-+def FXNORS      : VISInst<0b001110011,  "fxnors", FPRegs>;
-+
-+def FORNOT1     : VISInst<0b001111010,  "fornot1">;
-+def FORNOT1S    : VISInst<0b001111011,  "fornot1s",  FPRegs>;
-+def FORNOT2     : VISInst<0b001110110,  "fornot2">;
-+def FORNOT2S    : VISInst<0b001110111,  "fornot2s",  FPRegs>;
-+def FANDNOT1    : VISInst<0b001101000,  "fandnot1">;
-+def FANDNOT1S   : VISInst<0b001101001,  "fandnot1s", FPRegs>;
-+def FANDNOT2    : VISInst<0b001100100,  "fandnot2">;
-+def FANDNOT2S   : VISInst<0b001100101,  "fandnot2s", FPRegs>;
-+
-+def FCMPGT16    : VISInstID<0b000101000,  "fcmpgt16">;
-+def FCMPGT32    : VISInstID<0b000101100,  "fcmpgt32">;
-+def FCMPLE16    : VISInstID<0b000100000,  "fcmple16">;
-+def FCMPLE32    : VISInstID<0b000100100,  "fcmple32">;
-+def FCMPNE16    : VISInstID<0b000100010,  "fcmpne16">;
-+def FCMPNE32    : VISInstID<0b000100110,  "fcmpne32">;
-+def FCMPEQ16    : VISInstID<0b000101010,  "fcmpeq16">;
-+def FCMPEQ32    : VISInstID<0b000101110,  "fcmpeq32">;
-+
-+
-+def EDGE8       : VISInst<0b000000000,  "edge8",   I64Regs>;
-+def EDGE8L      : VISInst<0b000000010,  "edge8l",  I64Regs>;
-+def EDGE16      : VISInst<0b000000100,  "edge16",  I64Regs>;
-+def EDGE16L     : VISInst<0b000000110,  "edge16l", I64Regs>;
-+def EDGE32      : VISInst<0b000001000,  "edge32",  I64Regs>;
-+def EDGE32L     : VISInst<0b000001010,  "edge32l", I64Regs>;
-+
-+def PDIST       : VISInst<0b00111110, "pdist">;
-+
-+def ARRAY8      : VISInst<0b000010000, "array8",  I64Regs>;
-+def ARRAY16     : VISInst<0b000010010, "array16", I64Regs>;
-+def ARRAY32     : VISInst<0b000010100, "array32", I64Regs>;
-+
-+def SHUTDOWN    : VISInst0<0b010000000, "shutdown">;
-+
-+} // Predicates = [HasVIS]
-+
-+
-+// VIS 2 Instructions.
-+let Predicates = [HasVIS2] in {
-+
-+def BMASK     : VISInst<0b000011001, "bmask", I64Regs>;
-+def BSHUFFLE  : VISInst<0b000011100, "bshuffle">;
-+
-+def SIAM      : VISInst0<0b010000001, "siam">;
-+
-+def EDGE8N    : VISInst<0b000000001,  "edge8n",   I64Regs>;
-+def EDGE8LN   : VISInst<0b000000011,  "edge8ln",  I64Regs>;
-+def EDGE16N   : VISInst<0b000000101,  "edge16n",  I64Regs>;
-+def EDGE16LN  : VISInst<0b000000111,  "edge16ln", I64Regs>;
-+def EDGE32N   : VISInst<0b000001001,  "edge32n",  I64Regs>;
-+def EDGE32LN  : VISInst<0b000001011,  "edge32ln", I64Regs>;
-+} // Predicates = [HasVIS2]
-+
-+
-+// VIS 3 Instructions.
-+let Predicates = [HasVIS3] in {
-+
-+let Uses = [ICC] in
-+def ADDXC : VISInst<0b000010001, "addxc", I64Regs>;
-+
-+let Defs = [ICC], Uses = [ICC] in
-+def ADDXCCC : VISInst<0b000010011, "addxccc", I64Regs>;
-+
-+let rd = 0, rs1 = 0 in {
-+def CMASK8  : VISInstFormat<0b000011011, (outs), (ins I64Regs:$rs2),
-+              "cmask8 $rs2", []>;
-+def CMASK16  : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2),
-+              "cmask16 $rs2", []>;
-+def CMASK32  : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
-+              "cmask32 $rs2", []>;
-+
-+}
-+
-+def FCHKSM16 : VISInst<0b01000100, "fchksm16">;
-+
-+def FHADDS   : F3_3<0b10, 0b110100, 0b001100001,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fhadds $rs1, $rs2, $rd", []>;
-+def FHADDD   : F3_3<0b10, 0b110100, 0b001100010,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fhaddd $rs1, $rs2, $rd", []>;
-+def FHSUBS   : F3_3<0b10, 0b110100, 0b001100101,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fhsubs $rs1, $rs2, $rd", []>;
-+def FHSUBD   : F3_3<0b10, 0b110100, 0b001100110,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fhsubd $rs1, $rs2, $rd", []>;
-+def FLCMPS   : VISInstFormat<0b101010001, (outs FCCRegs:$rd),
-+                     (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                     "flcmps $rd, $rs1, $rs2", []>;
-+def FLCMPD   : VISInstFormat<0b101010010, (outs FCCRegs:$rd),
-+                     (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                     "flcmpd $rd, $rs1, $rs2", []>;
-+
-+def FMEAN16  : VISInst<0b001000000, "fmean16">;
-+
-+def FNADDS   : F3_3<0b10, 0b110100, 0b001010001,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fnadds $rs1, $rs2, $rd", []>;
-+def FNADDD   : F3_3<0b10, 0b110100, 0b001010010,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fnaddd $rs1, $rs2, $rd", []>;
-+def FNHADDS  : F3_3<0b10, 0b110100, 0b001110001,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fnhadds $rs1, $rs2, $rd", []>;
-+def FNHADDD  : F3_3<0b10, 0b110100, 0b001110010,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fnhaddd $rs1, $rs2, $rd", []>;
-+
-+def FNMULS   : F3_3<0b10, 0b110100, 0b001011001,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fnhadds $rs1, $rs2, $rd", []>;
-+def FNMULD   : F3_3<0b10, 0b110100, 0b001011010,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fnhaddd $rs1, $rs2, $rd", []>;
-+def FNSMULD  : F3_3<0b10, 0b110100, 0b001111001,
-+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
-+                    "fnhadds $rs1, $rs2, $rd", []>;
-+
-+def FPADD64   : VISInst<0b001000010, "fpadd64">;
-+
-+def FSLL16    : VISInst<0b00100001, "fsll16">;
-+def FSRL16    : VISInst<0b00100011, "fsrl16">;
-+def FSLL32    : VISInst<0b00100101, "fsll32">;
-+def FSRL32    : VISInst<0b00100111, "fsrl32">;
-+def FSLAS16   : VISInst<0b00101001, "fslas16">;
-+def FSRA16    : VISInst<0b00101011, "fsra16">;
-+def FSLAS32   : VISInst<0b00101101, "fslas32">;
-+def FSRA32    : VISInst<0b00101111, "fsra32">;
-+
-+let rs1 = 0 in
-+def LZCNT     : VISInstFormat<0b000010111, (outs I64Regs:$rd),
-+                   (ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
-+
-+let rs1 = 0 in {
-+def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
-+                   (ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;
-+def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd),
-+                   (ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>;
-+def MOVDTOX  : VISInstFormat<0b100010000, (outs I64Regs:$rd),
-+                   (ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>;
-+def MOVWTOS  :  VISInstFormat<0b100011001, (outs DFPRegs:$rd),
-+                   (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
-+def MOVXTOD  :  VISInstFormat<0b100011000, (outs DFPRegs:$rd),
-+                   (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
-+}
-+
-+def PDISTN   : VISInst<0b000111111, "pdistn">;
-+
-+def UMULXHI  : VISInst<0b000010110, "umulxhi", I64Regs>;
-+def XMULX    : VISInst<0b100010101, "xmulx",   I64Regs>;
-+def XMULXHI  : VISInst<0b100010111, "xmulxhi", I64Regs>;
-+} // Predicates = [IsVIS3]
Index: patches/patch-lib_Target_Sparc_SparcRegisterInfo_td
===================================================================
RCS file: patches/patch-lib_Target_Sparc_SparcRegisterInfo_td
diff -N patches/patch-lib_Target_Sparc_SparcRegisterInfo_td
--- patches/patch-lib_Target_Sparc_SparcRegisterInfo_td 19 May 2015 05:33:39 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,87 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_SparcRegisterInfo_td,v 1.2 2015/05/19 05:33:39 ajacoutot Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
-r237580
-Add support for the Sparc implementation-defined "ASR" registers.
-
-r237582
-Sparc: Support PSR, TBR, WIM read/write instructions.
-
---- lib/Target/Sparc/SparcRegisterInfo.td.orig Sun Mar  2 21:57:39 2014
-+++ lib/Target/Sparc/SparcRegisterInfo.td Mon May 18 18:32:12 2015
-@@ -16,7 +16,8 @@ class SparcReg<bits<16> Enc, string n> : Register<n> {
-   let Namespace = "SP";
- }
-
--class SparcCtrlReg<string n>: Register<n> {
-+class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
-+  let HWEncoding = Enc;
-   let Namespace = "SP";
- }
-
-@@ -49,12 +50,50 @@ class Rq<bits<16> Enc, string n, list<Register> subreg
- }
-
- // Control Registers
--def ICC : SparcCtrlReg<"ICC">; // This represents icc and xcc in 64-bit code.
--def FCC : SparcCtrlReg<"FCC">;
-+def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
-+foreach I = 0-3 in
-+  def FCC#I : SparcCtrlReg<I, "FCC"#I>;
-
- // Y register
--def Y : SparcCtrlReg<"Y">, DwarfRegNum<[64]>;
-+def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
-+// Ancillary state registers (implementation defined)
-+def ASR1 : SparcCtrlReg<1, "ASR1">;
-+def ASR2 : SparcCtrlReg<2, "ASR2">;
-+def ASR3 : SparcCtrlReg<3, "ASR3">;
-+def ASR4 : SparcCtrlReg<4, "ASR4">;
-+def ASR5 : SparcCtrlReg<5, "ASR5">;
-+def ASR6 : SparcCtrlReg<6, "ASR6">;
-+def ASR7 : SparcCtrlReg<7, "ASR7">;
-+def ASR8 : SparcCtrlReg<8, "ASR8">;
-+def ASR9 : SparcCtrlReg<9, "ASR9">;
-+def ASR10 : SparcCtrlReg<10, "ASR10">;
-+def ASR11 : SparcCtrlReg<11, "ASR11">;
-+def ASR12 : SparcCtrlReg<12, "ASR12">;
-+def ASR13 : SparcCtrlReg<13, "ASR13">;
-+def ASR14 : SparcCtrlReg<14, "ASR14">;
-+def ASR15 : SparcCtrlReg<15, "ASR15">;
-+def ASR16 : SparcCtrlReg<16, "ASR16">;
-+def ASR17 : SparcCtrlReg<17, "ASR17">;
-+def ASR18 : SparcCtrlReg<18, "ASR18">;
-+def ASR19 : SparcCtrlReg<19, "ASR19">;
-+def ASR20 : SparcCtrlReg<20, "ASR20">;
-+def ASR21 : SparcCtrlReg<21, "ASR21">;
-+def ASR22 : SparcCtrlReg<22, "ASR22">;
-+def ASR23 : SparcCtrlReg<23, "ASR23">;
-+def ASR24 : SparcCtrlReg<24, "ASR24">;
-+def ASR25 : SparcCtrlReg<25, "ASR25">;
-+def ASR26 : SparcCtrlReg<26, "ASR26">;
-+def ASR27 : SparcCtrlReg<27, "ASR27">;
-+def ASR28 : SparcCtrlReg<28, "ASR28">;
-+def ASR29 : SparcCtrlReg<29, "ASR29">;
-+def ASR30 : SparcCtrlReg<30, "ASR30">;
-+def ASR31 : SparcCtrlReg<31, "ASR31">;
-
-+// Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
-+def PSR : SparcCtrlReg<0, "PSR">;
-+def WIM : SparcCtrlReg<0, "WIM">;
-+def TBR : SparcCtrlReg<0, "TBR">;
-+
- // Integer registers
- def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
- def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
-@@ -204,3 +243,10 @@ def FPRegs : RegisterClass<"SP", [f32], 32, (sequence
- def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
-
- def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
-+
-+// Floating point control register classes.
-+def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
-+
-+// Ancillary state registers
-+def ASRRegs : RegisterClass<"SP", [i32], 32,
-+                            (add Y, (sequence "ASR%u", 1, 31))>;
Index: patches/patch-lib_Target_Sparc_SparcSubtarget_h
===================================================================
RCS file: patches/patch-lib_Target_Sparc_SparcSubtarget_h
diff -N patches/patch-lib_Target_Sparc_SparcSubtarget_h
--- patches/patch-lib_Target_Sparc_SparcSubtarget_h 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,24 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_SparcSubtarget_h,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/SparcSubtarget.h.orig Sun Jun 15 02:53:17 2014
-+++ lib/Target/Sparc/SparcSubtarget.h Sun Jun 15 02:58:11 2014
-@@ -27,7 +27,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
-   virtual void anchor();
-   bool IsV9;
-   bool V8DeprecatedInsts;
--  bool IsVIS;
-+  bool IsVIS, IsVIS2, IsVIS3;
-   bool Is64Bit;
-   bool HasHardQuad;
-   bool UsePopc;
-@@ -38,6 +38,8 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
-
-   bool isV9() const { return IsV9; }
-   bool isVIS() const { return IsVIS; }
-+  bool isVIS2() const { return IsVIS2; }
-+  bool isVIS3() const { return IsVIS3; }
-   bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
-   bool hasHardQuad() const { return HasHardQuad; }
-   bool usePopc() const { return UsePopc; }
Index: patches/patch-lib_Target_Sparc_Sparc_td
===================================================================
RCS file: patches/patch-lib_Target_Sparc_Sparc_td
diff -N patches/patch-lib_Target_Sparc_Sparc_td
--- patches/patch-lib_Target_Sparc_Sparc_td 11 Jul 2014 01:05:24 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,43 +0,0 @@
-$OpenBSD: patch-lib_Target_Sparc_Sparc_td,v 1.1 2014/07/11 01:05:24 brad Exp $
-
-Sync up the SPARC backend up to commit r203424.
-
---- lib/Target/Sparc/Sparc.td.orig Sun Jun 15 02:52:51 2014
-+++ lib/Target/Sparc/Sparc.td Sun Jun 15 02:57:59 2014
-@@ -29,6 +29,12 @@ def FeatureV8Deprecated
- def FeatureVIS
-   : SubtargetFeature<"vis", "IsVIS", "true",
-                      "Enable UltraSPARC Visual Instruction Set extensions">;
-+def FeatureVIS2
-+  : SubtargetFeature<"vis2", "IsVIS2", "true",
-+                     "Enable Visual Instruction Set extensions II">;
-+def FeatureVIS3
-+  : SubtargetFeature<"vis3", "IsVIS3", "true",
-+                     "Enable Visual Instruction Set extensions III">;
-
- def FeatureHardQuad
-   : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
-@@ -69,12 +75,17 @@ def : Proc<"sparclite86x",    []>;
- def : Proc<"sparclet",        []>;
- def : Proc<"tsc701",          []>;
- def : Proc<"v9",              [FeatureV9]>;
--def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated]>;
--def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated]>;
--def : Proc<"niagara",         [FeatureV9, FeatureV8Deprecated]>;
--def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc]>;
--def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc]>;
--def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc]>;
-+def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
-+def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated, FeatureVIS,
-+                               FeatureVIS2]>;
-+def : Proc<"niagara",         [FeatureV9, FeatureV8Deprecated, FeatureVIS,
-+                               FeatureVIS2]>;
-+def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-+                               FeatureVIS, FeatureVIS2]>;
-+def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-+                               FeatureVIS, FeatureVIS2]>;
-+def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-+                               FeatureVIS, FeatureVIS2, FeatureVIS3]>;
-
-
- //===----------------------------------------------------------------------===//
Index: patches/patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp
===================================================================
RCS file: patches/patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp
diff -N patches/patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp
--- patches/patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp 6 Jan 2015 00:58:02 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,20 +0,0 @@
-$OpenBSD: patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp,v 1.2 2015/01/06 00:58:02 brad Exp $
-
-r225227
-Remove X86 .quad workaround for buggy GNU assembler on OpenBSD / Bitrig.
-
---- lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp.orig Fri Oct 17 03:18:59 2014
-+++ lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp Fri Oct 17 03:38:34 2014
-@@ -111,12 +111,6 @@ X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
-   // Exceptions handling
-   ExceptionsType = ExceptionHandling::DwarfCFI;
-
--  // OpenBSD and Bitrig have buggy support for .quad in 32-bit mode, just split
--  // into two .words.
--  if ((T.getOS() == Triple::OpenBSD || T.getOS() == Triple::Bitrig) &&
--       T.getArch() == Triple::x86)
--    Data64bitsDirective = 0;
--
-   // Always enable the integrated assembler by default.
-   // Clang also enabled it when the OS is Solaris but that is redundant here.
-   UseIntegratedAssembler = true;
Index: patches/patch-lib_Target_X86_X86AsmPrinter_cpp
===================================================================
RCS file: patches/patch-lib_Target_X86_X86AsmPrinter_cpp
diff -N patches/patch-lib_Target_X86_X86AsmPrinter_cpp
--- patches/patch-lib_Target_X86_X86AsmPrinter_cpp 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,25 +0,0 @@
-$OpenBSD: patch-lib_Target_X86_X86AsmPrinter_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r205067
-Fix printing of register operands with q modifier.
-
-Emit 32-bit register names instead of 64-bit register names if the target does
-not have 64-bit general purpose registers.
-
---- lib/Target/X86/X86AsmPrinter.cpp.orig Sun Mar  2 21:57:40 2014
-+++ lib/Target/X86/X86AsmPrinter.cpp Sat Jun 14 05:56:09 2014
-@@ -365,9 +365,11 @@ static bool printAsmMRegister(X86AsmPrinter &P, const
-   case 'k': // Print SImode register
-     Reg = getX86SubSuperRegister(Reg, MVT::i32);
-     break;
--  case 'q': // Print DImode register
--    // FIXME: gcc will actually print e instead of r for 32-bit.
--    Reg = getX86SubSuperRegister(Reg, MVT::i64);
-+  case 'q':
-+    // Print 64-bit register names if 64-bit integer registers are available.
-+    // Otherwise, print 32-bit register names.
-+    MVT::SimpleValueType Ty = P.getSubtarget().is64Bit() ? MVT::i64 : MVT::i32;
-+    Reg = getX86SubSuperRegister(Reg, Ty);
-     break;
-   }
-
Index: patches/patch-lib_Target_X86_X86ISelDAGToDAG_cpp
===================================================================
RCS file: patches/patch-lib_Target_X86_X86ISelDAGToDAG_cpp
diff -N patches/patch-lib_Target_X86_X86ISelDAGToDAG_cpp
--- patches/patch-lib_Target_X86_X86ISelDAGToDAG_cpp 24 Aug 2015 07:45:56 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,60 +0,0 @@
-$OpenBSD: patch-lib_Target_X86_X86ISelDAGToDAG_cpp,v 1.1 2015/08/24 07:45:56 ajacoutot Exp $
-
-r219009
-[ISel] Keep matching state consistent when folding during X86 address match
-
-In the X86 backend, matching an address is initiated by the 'addr' complex
-pattern and its friends.  During this process we may reassociate and-of-shift
-into shift-of-and (FoldMaskedShiftToScaledMask) to allow folding of the
-shift into the scale of the address.
-
-However as demonstrated by the testcase, this can trigger CSE of not only the
-shift and the AND which the code is prepared for but also the underlying load
-node.  In the testcase this node is sitting in the RecordedNode and MatchScope
-data structures of the matcher and becomes a deleted node upon CSE.  Returning
-from the complex pattern function, we try to access it again hitting an assert
-because the node is no longer a load even though this was checked before.
-
-Now obviously changing the DAG this late is bending the rules but I think it
-makes sense somewhat.  Outside of addresses we prefer and-of-shift because it
-may lead to smaller immediates (FoldMaskAndShiftToScale is an even better
-example because it create a non-canonical node).  We currently don't recognize
-addresses during DAGCombiner where arguably this canonicalization should be
-performed.  On the other hand, having this in the matcher allows us to cover
-all the cases where an address can be used in an instruction.
-
-I've also talked a little bit to Dan Gohman on llvm-dev who added the RAUW for
-the new shift node in FoldMaskedShiftToScaledMask.  This RAUW is responsible
-for initiating the recursive CSE on users
-(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-September/076903.html) but it
-is not strictly necessary since the shift is hooked into the visited user.  Of
-course it's safer to keep the DAG consistent at all times (e.g. for accurate
-number of uses, etc.).
-
-So rather than changing the fundamentals, I've decided to continue along the
-previous patches and detect the CSE.  This patch installs a very targeted
-DAGUpdateListener for the duration of a complex-pattern match and updates the
-matching state accordingly.  (Previous patches used HandleSDNode to detect the
-CSE but that's not practical here).  The listener is only installed on X86.
-
-I tested that there is no measurable overhead due to this while running
-through the spec2k BC files with llc.  The only thing we pay for is the
-creation of the listener.  The callback never ever triggers in spec2k since
-this is a corner case.
-
---- lib/Target/X86/X86ISelDAGToDAG.cpp.orig Tue Aug  4 22:53:05 2015
-+++ lib/Target/X86/X86ISelDAGToDAG.cpp Tue Aug  4 22:53:59 2015
-@@ -290,6 +290,13 @@ namespace {
-     const X86InstrInfo *getInstrInfo() const {
-       return getTargetMachine().getInstrInfo();
-     }
-+
-+    /// \brief Address-mode matching performs shift-of-and to and-of-shift
-+    /// reassociation in order to expose more scaled addressing
-+    /// opportunities.
-+    bool ComplexPatternFuncMutatesDAG() const {
-+      return true;
-+    }
-   };
- }
-
Index: patches/patch-lib_Target_X86_X86ISelLowering_cpp
===================================================================
RCS file: patches/patch-lib_Target_X86_X86ISelLowering_cpp
diff -N patches/patch-lib_Target_X86_X86ISelLowering_cpp
--- patches/patch-lib_Target_X86_X86ISelLowering_cpp 15 Sep 2014 19:24:16 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,74 +0,0 @@
-$OpenBSD: patch-lib_Target_X86_X86ISelLowering_cpp,v 1.2 2014/09/15 19:24:16 brad Exp $
-
-r203581
-Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)
-
-This fixes the bug where we would bitcast the 64-bit floating point result
-of cmpneqsd to a 64-bit integer even on 32-bit targets.
-
-r217410
-Set trunc store action to Expand for all X86 targets.
-
-When compiling without SSE2, isTruncStoreLegal(F64, F32) would return Legal, whereas
-with SSE2 it would return Expand. And since the Target doesn't seem to actually
-handle a truncstore for double -> float, it would just output a store of a full
-double in the space for a float hence overwriting other bits on the stack.
-
---- lib/Target/X86/X86ISelLowering.cpp.orig Sun Mar  2 21:57:40 2014
-+++ lib/Target/X86/X86ISelLowering.cpp Sun Sep 14 19:09:50 2014
-@@ -301,6 +301,8 @@ void X86TargetLowering::resetOperationActions() {
-   setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
-   setTruncStoreAction(MVT::i16, MVT::i8,  Expand);
-
-+  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
-+
-   // SETOEQ and SETUNE require checking two conditions.
-   setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
-   setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
-@@ -1012,8 +1014,6 @@ void X86TargetLowering::resetOperationActions() {
-       AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
-     }
-
--    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
--
-     // Custom lower v2i64 and v2f64 selects.
-     setOperationAction(ISD::LOAD,               MVT::v2f64, Legal);
-     setOperationAction(ISD::LOAD,               MVT::v2i64, Legal);
-@@ -18052,7 +18052,6 @@ static SDValue CMPEQCombine(SDNode *N, SelectionDAG &D
-
-         if ((cc0 == X86::COND_E  && cc1 == X86::COND_NP) ||
-             (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
--          bool is64BitFP = (CMP00.getValueType() == MVT::f64);
-           // FIXME: need symbolic constants for these magic numbers.
-           // See X86ATTInstPrinter.cpp:printSSECC().
-           unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
-@@ -18067,9 +18066,26 @@ static SDValue CMPEQCombine(SDNode *N, SelectionDAG &D
-           SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
-                                               CMP00.getValueType(), CMP00, CMP01,
-                                               DAG.getConstant(x86cc, MVT::i8));
--          MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
--          SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
--                                              OnesOrZeroesF);
-+
-+          bool is64BitFP = (CMP00.getValueType() == MVT::f64);
-+          MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
-+
-+          if (is64BitFP && !Subtarget->is64Bit()) {
-+            // On a 32-bit target, we cannot bitcast the 64-bit float to a
-+            // 64-bit integer, since that's not a legal type. Since
-+            // OnesOrZeroesF is all ones of all zeroes, we don't need all the
-+            // bits, but can do this little dance to extract the lowest 32 bits
-+            // and work with those going forward.
-+            SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
-+                                           OnesOrZeroesF);
-+            SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
-+                                           Vector64);
-+            OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
-+                                        Vector32, DAG.getIntPtrConstant(0));
-+            IntVT = MVT::i32;
-+          }
-+
-+          SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
-           SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
-                                       DAG.getConstant(1, IntVT));
-           SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
Index: patches/patch-lib_Transforms_Vectorize_LoopVectorize_cpp
===================================================================
RCS file: patches/patch-lib_Transforms_Vectorize_LoopVectorize_cpp
diff -N patches/patch-lib_Transforms_Vectorize_LoopVectorize_cpp
--- patches/patch-lib_Transforms_Vectorize_LoopVectorize_cpp 12 Dec 2014 21:51:39 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,22 +0,0 @@
-$OpenBSD: patch-lib_Transforms_Vectorize_LoopVectorize_cpp,v 1.1 2014/12/12 21:51:39 brad Exp $
-
-r223171
-PR21302. Vectorize only bottom-tested loops.
-
---- lib/Transforms/Vectorize/LoopVectorize.cpp.orig Thu Dec 11 11:41:59 2014
-+++ lib/Transforms/Vectorize/LoopVectorize.cpp Thu Dec 11 11:45:56 2014
-@@ -3247,6 +3247,14 @@ bool LoopVectorizationLegality::canVectorize() {
-   if (!TheLoop->getExitingBlock())
-     return false;
-
-+  // We only handle bottom-tested loops, i.e. loop in which the condition is
-+  // checked at the end of each iteration. With that we can assume that all
-+  // instructions in the loop are executed the same number of times.
-+  if (TheLoop->getExitingBlock() != TheLoop->getLoopLatch()) {
-+    DEBUG(dbgs() << "LV: loop control flow is not understood by vectorizer\n");
-+    return false;
-+  }
-+
-   // We need to have a loop header.
-   DEBUG(dbgs() << "LV: Found a loop: " <<
-         TheLoop->getHeader()->getName() << '\n');
Index: patches/patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td
===================================================================
RCS file: patches/patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td
diff -N patches/patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td
--- patches/patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td 9 Apr 2015 22:25:02 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,19 +0,0 @@
-$OpenBSD: patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td,v 1.1 2015/04/09 22:25:02 sthen Exp $
-
-r211785
-Implement the -fuse-ld= option.
-
-This commit implements the -fuse-ld= option, so that the user
-can specify -fuse-ld=bfd to use ld.bfd.
-
---- tools/clang/include/clang/Basic/DiagnosticDriverKinds.td.orig Thu Feb 26 07:01:37 2015
-+++ tools/clang/include/clang/Basic/DiagnosticDriverKinds.td Thu Feb 26 07:02:16 2015
-@@ -22,6 +22,8 @@ def err_drv_unknown_stdin_type_clang_cl : Error<
- def err_drv_unknown_language : Error<"language not recognized: '%0'">;
- def err_drv_invalid_arch_name : Error<
-   "invalid arch name '%0'">;
-+def err_drv_invalid_linker_name : Error<
-+  "invalid linker name in argument '%0'">;
- def err_drv_invalid_rtlib_name : Error<
-   "invalid runtime library name in argument '%0'">;
- def err_drv_unsupported_rtlib_for_platform : Error<
Index: patches/patch-tools_clang_include_clang_Driver_Options_td
===================================================================
RCS file: /cvs/ports/devel/llvm/patches/patch-tools_clang_include_clang_Driver_Options_td,v
retrieving revision 1.4
diff -u -p -r1.4 patch-tools_clang_include_clang_Driver_Options_td
--- patches/patch-tools_clang_include_clang_Driver_Options_td 9 Apr 2015 22:25:02 -0000 1.4
+++ patches/patch-tools_clang_include_clang_Driver_Options_td 23 Jan 2016 18:38:51 -0000
@@ -2,38 +2,14 @@ $OpenBSD: patch-tools_clang_include_clan
 
 Alias the command line parameter -p to -pg.
 
-r211785
-Implement the -fuse-ld= option.
-
-This commit implements the -fuse-ld= option, so that the user
-can specify -fuse-ld=bfd to use ld.bfd.
-
---- tools/clang/include/clang/Driver/Options.td.orig Sun Mar  2 22:03:58 2014
-+++ tools/clang/include/clang/Driver/Options.td Thu Feb 26 07:03:04 2015
-@@ -253,7 +253,7 @@ def Qn : Flag<["-"], "Qn">;
- def Qunused_arguments : Flag<["-"], "Qunused-arguments">, Flags<[DriverOption, CoreOption]>,
-   HelpText<"Don't emit warning for unused driver arguments">;
- def Q : Flag<["-"], "Q">;
--def R : Flag<["-"], "R">;
-+def R : JoinedOrSeparate<["-"], "R">, Flags<[RenderJoined]>;
- def S : Flag<["-"], "S">, Flags<[DriverOption,CC1Option]>, Group<Action_Group>,
-   HelpText<"Only run preprocess and compilation steps">;
- def Tbss : JoinedOrSeparate<["-"], "Tbss">, Group<T_Group>;
-@@ -1244,7 +1244,7 @@ def private__bundle : Flag<["-"], "private_bundle">;
- def pthreads : Flag<["-"], "pthreads">;
+--- tools/clang/include/clang/Driver/Options.td.orig Fri Jul 31 00:47:41 2015
++++ tools/clang/include/clang/Driver/Options.td Wed Sep  9 10:44:20 2015
+@@ -1560,7 +1560,7 @@ def pthreads : Flag<["-"], "pthreads">;
  def pthread : Flag<["-"], "pthread">, Flags<[CC1Option]>,
    HelpText<"Support POSIX threads in generated code">;
+ def no_pthread : Flag<["-"], "no-pthread">, Flags<[CC1Option]>;
 -def p : Flag<["-"], "p">;
 +def p : Flag<["-"], "p">, Alias<pg>;
  def pie : Flag<["-"], "pie">;
  def read__only__relocs : Separate<["-"], "read_only_relocs">;
  def remap : Flag<["-"], "remap">;
-@@ -1495,7 +1495,7 @@ def fprofile_dir : Joined<["-"], "fprofile-dir=">, Gro
-
- defm profile_use : BooleanFFlag<"profile-use">, Group<clang_ignored_f_Group>;
- def fprofile_use_EQ : Joined<["-"], "fprofile-use=">, Group<clang_ignored_f_Group>;
--def fuse_ld_EQ : Joined<["-"], "fuse-ld=">, Group<clang_ignored_f_Group>;
-+def fuse_ld_EQ : Joined<["-"], "fuse-ld=">, Group<f_Group>;
-
- defm align_functions : BooleanFFlag<"align-functions">, Group<clang_ignored_f_Group>;
- def falign_functions_EQ : Joined<["-"], "falign-functions=">, Group<clang_ignored_f_Group>;
Index: patches/patch-tools_clang_include_clang_Driver_ToolChain_h
===================================================================
RCS file: patches/patch-tools_clang_include_clang_Driver_ToolChain_h
diff -N patches/patch-tools_clang_include_clang_Driver_ToolChain_h
--- patches/patch-tools_clang_include_clang_Driver_ToolChain_h 9 Apr 2015 22:25:02 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,21 +0,0 @@
-$OpenBSD: patch-tools_clang_include_clang_Driver_ToolChain_h,v 1.1 2015/04/09 22:25:02 sthen Exp $
-
-r211785
-Implement the -fuse-ld= option.
-
-This commit implements the -fuse-ld= option, so that the user
-can specify -fuse-ld=bfd to use ld.bfd.
-
---- tools/clang/include/clang/Driver/ToolChain.h.orig Thu Feb 26 07:03:30 2015
-+++ tools/clang/include/clang/Driver/ToolChain.h Thu Feb 26 07:03:53 2015
-@@ -158,6 +158,10 @@ class ToolChain { (public)
-   std::string GetFilePath(const char *Name) const;
-   std::string GetProgramPath(const char *Name) const;
-
-+  /// Returns the linker path, respecting the -fuse-ld= argument to determine
-+  /// the linker suffix or name.
-+  std::string GetLinkerPath() const;
-+
-   /// \brief Dispatch to the specific toolchain for verbose printing.
-   ///
-   /// This is used when handling the verbose option to print detailed,
Index: patches/patch-tools_clang_lib_AST_ASTDumper_cpp
===================================================================
RCS file: patches/patch-tools_clang_lib_AST_ASTDumper_cpp
diff -N patches/patch-tools_clang_lib_AST_ASTDumper_cpp
--- patches/patch-tools_clang_lib_AST_ASTDumper_cpp 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,42 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_AST_ASTDumper_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r203050
-Change the color of comment nodes from bright yellow to blue.  Bright yellow on
-a white background is difficult to read.  Also include a chart showing which
-colors are used by which elements in the AST dump.
-
---- tools/clang/lib/AST/ASTDumper.cpp.orig Sun Mar  2 22:03:41 2014
-+++ tools/clang/lib/AST/ASTDumper.cpp Sat Jun 14 03:54:11 2014
-@@ -32,12 +32,23 @@ using namespace clang::comments;
-
- namespace  {
-   // Colors used for various parts of the AST dump
-+  // Do not use bold yellow for any text.  It is hard to read on white screens.
-
-   struct TerminalColor {
-     raw_ostream::Colors Color;
-     bool Bold;
-   };
-
-+  // Red           - CastColor
-+  // Green         - TypeColor
-+  // Bold Green    - DeclKindNameColor, UndeserializedColor
-+  // Yellow        - AddressColor, LocationColor
-+  // Blue          - CommentColor, NullColor, IndentColor
-+  // Bold Blue     - AttrColor
-+  // Bold Magenta  - StmtColor
-+  // Cyan          - ValueKindColor, ObjectKindColor
-+  // Bold Cyan     - ValueColor, DeclNameColor
-+
-   // Decl kind names (VarDecl, FunctionDecl, etc)
-   static const TerminalColor DeclKindNameColor = { raw_ostream::GREEN, true };
-   // Attr names (CleanupAttr, GuardedByAttr, etc)
-@@ -45,7 +56,7 @@ namespace  {
-   // Statement names (DeclStmt, ImplicitCastExpr, etc)
-   static const TerminalColor StmtColor = { raw_ostream::MAGENTA, true };
-   // Comment names (FullComment, ParagraphComment, TextComment, etc)
--  static const TerminalColor CommentColor = { raw_ostream::YELLOW, true };
-+  static const TerminalColor CommentColor = { raw_ostream::BLUE, false };
-
-   // Type names (int, float, etc, plus user defined types)
-   static const TerminalColor TypeColor = { raw_ostream::GREEN, false };
Index: patches/patch-tools_clang_lib_AST_ExprConstant_cpp
===================================================================
RCS file: patches/patch-tools_clang_lib_AST_ExprConstant_cpp
diff -N patches/patch-tools_clang_lib_AST_ExprConstant_cpp
--- patches/patch-tools_clang_lib_AST_ExprConstant_cpp 10 Jul 2014 22:46:37 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,57 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_AST_ExprConstant_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
-
-r203025
-PR19010: Make sure we initialize (empty) indirect base class subobjects when
-evaluating trivial default initialization of a literal class type.
-
---- tools/clang/lib/AST/ExprConstant.cpp.orig Sun Mar  2 22:03:41 2014
-+++ tools/clang/lib/AST/ExprConstant.cpp Sat Jun 14 03:37:45 2014
-@@ -5117,16 +5117,15 @@ bool RecordExprEvaluator::VisitCXXConstructExpr(const
-     if (!Result.isUninit())
-       return true;
-
--    if (ZeroInit)
--      return ZeroInitialization(E);
--
--    const CXXRecordDecl *RD = FD->getParent();
--    if (RD->isUnion())
--      Result = APValue((FieldDecl*)0);
--    else
--      Result = APValue(APValue::UninitStruct(), RD->getNumBases(),
--                       std::distance(RD->field_begin(), RD->field_end()));
--    return true;
-+    // We can get here in two different ways:
-+    //  1) We're performing value-initialization, and should zero-initialize
-+    //     the object, or
-+    //  2) We're performing default-initialization of an object with a trivial
-+    //     constexpr default constructor, in which case we should start the
-+    //     lifetimes of all the base subobjects (there can be no data member
-+    //     subobjects in this case) per [basic.life]p1.
-+    // Either way, ZeroInitialization is appropriate.
-+    return ZeroInitialization(E);
-   }
-
-   const FunctionDecl *Definition = 0;
-@@ -5606,19 +5605,9 @@ bool ArrayExprEvaluator::VisitCXXConstructExpr(const C
-     if (HadZeroInit)
-       return true;
-
--    if (ZeroInit) {
--      ImplicitValueInitExpr VIE(Type);
--      return EvaluateInPlace(*Value, Info, Subobject, &VIE);
--    }
--
--    const CXXRecordDecl *RD = FD->getParent();
--    if (RD->isUnion())
--      *Value = APValue((FieldDecl*)0);
--    else
--      *Value =
--          APValue(APValue::UninitStruct(), RD->getNumBases(),
--                  std::distance(RD->field_begin(), RD->field_end()));
--    return true;
-+    // See RecordExprEvaluator::VisitCXXConstructExpr for explanation.
-+    ImplicitValueInitExpr VIE(Type);
-+    return EvaluateInPlace(*Value, Info, Subobject, &VIE);
-   }
-
-   const FunctionDecl *Definition = 0;
Index: patches/patch-tools_clang_lib_Basic_Targets_cpp
===================================================================
RCS file: patches/patch-tools_clang_lib_Basic_Targets_cpp
diff -N patches/patch-tools_clang_lib_Basic_Targets_cpp
--- patches/patch-tools_clang_lib_Basic_Targets_cpp 15 Jun 2015 06:20:48 -0000 1.13
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,91 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_Basic_Targets_cpp,v 1.13 2015/06/15 06:20:48 ajacoutot Exp $
-
-r236179
-Propagate a terrible hack to the sparc target feature handling code
-by erasing the soft-float target feature if the rest of the front
-end added it because of defaults or the soft float option.
-
-r239046
-[SPARC] Fix types of size_t, intptr_t, and ptrdiff_t on Linux.
-
-They should be 'int' instead of 'long int' everywhere else except
-NetBSD too, from what I gather in GCC's spec files. So, optimistically
-changing it for everyone else, too.
-
---- tools/clang/lib/Basic/Targets.cpp.orig Sun Mar  2 22:03:40 2014
-+++ tools/clang/lib/Basic/Targets.cpp Fri Jun  5 00:55:44 2015
-@@ -4477,9 +4477,12 @@ class SparcTargetInfo : public TargetInfo { (public)
-   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
-                                     DiagnosticsEngine &Diags) {
-     SoftFloat = false;
--    for (unsigned i = 0, e = Features.size(); i != e; ++i)
--      if (Features[i] == "+soft-float")
--        SoftFloat = true;
-+    std::vector<std::string>::iterator Feature =
-+      std::find(Features.begin(), Features.end(), "+soft-float");
-+    if (Feature != Features.end()) {
-+      SoftFloat = true;
-+      Features.erase(Feature);
-+    }
-     return true;
-   }
-   virtual void getTargetDefines(const LangOptions &Opts,
-@@ -4579,6 +4582,20 @@ class SparcV8TargetInfo : public SparcTargetInfo {
- public:
-   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
-     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
-+    // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
-+    switch (getTriple().getOS()) {
-+    default:
-+      SizeType = UnsignedInt;
-+      IntPtrType = SignedInt;
-+      PtrDiffType = SignedInt;
-+      break;
-+    case llvm::Triple::NetBSD:
-+    case llvm::Triple::OpenBSD:
-+      SizeType = UnsignedLong;
-+      IntPtrType = SignedLong;
-+      PtrDiffType = SignedLong;
-+      break;
-+    }
-   }
-
-   virtual void getTargetDefines(const LangOptions &Opts,
-@@ -4650,25 +4667,6 @@ class SparcV9TargetInfo : public SparcTargetInfo { (pu
- } // end anonymous namespace.
-
- namespace {
--class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
--public:
--  AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
--      : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
--    SizeType = UnsignedInt;
--    PtrDiffType = SignedInt;
--  }
--};
--class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
--public:
--  SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
--      : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
--    SizeType = UnsignedInt;
--    PtrDiffType = SignedInt;
--  }
--};
--} // end anonymous namespace.
--
--namespace {
-   class SystemZTargetInfo : public TargetInfo {
-     static const char *const GCCRegNames[];
-
-@@ -5812,9 +5810,9 @@ static TargetInfo *AllocateTarget(const llvm::Triple &
-     case llvm::Triple::Linux:
-       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
-     case llvm::Triple::AuroraUX:
--      return new AuroraUXSparcV8TargetInfo(Triple);
-+      return new AuroraUXTargetInfo<SparcV8TargetInfo>(Triple);
-     case llvm::Triple::Solaris:
--      return new SolarisSparcV8TargetInfo(Triple);
-+      return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
-     case llvm::Triple::NetBSD:
-       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
-     case llvm::Triple::OpenBSD:
Index: patches/patch-tools_clang_lib_CodeGen_CGCXX_cpp
===================================================================
RCS file: patches/patch-tools_clang_lib_CodeGen_CGCXX_cpp
diff -N patches/patch-tools_clang_lib_CodeGen_CGCXX_cpp
--- patches/patch-tools_clang_lib_CodeGen_CGCXX_cpp 18 Apr 2014 21:26:56 -0000 1.2
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,24 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_CodeGen_CGCXX_cpp,v 1.2 2014/04/18 21:26:56 brad Exp $
-
-r203007
-Don't produce an alias between destructors with different calling conventions.
-
-http://llvm.org/bugs/show_bug.cgi?id=19007
-https://bugzilla.mozilla.org/show_bug.cgi?id=978423
-
---- tools/clang/lib/CodeGen/CGCXX.cpp.orig Fri Apr  4 23:01:26 2014
-+++ tools/clang/lib/CodeGen/CGCXX.cpp Fri Apr  4 23:02:50 2014
-@@ -92,7 +92,13 @@ bool CodeGenModule::TryEmitBaseDestructorAsAlias(const
-   if (!ClassLayout.getBaseClassOffset(UniqueBase).isZero())
-     return true;
-
-+  // Give up if the calling conventions don't match. We could update the call,
-+  // but it is probably not worth it.
-   const CXXDestructorDecl *BaseD = UniqueBase->getDestructor();
-+  if (BaseD->getType()->getAs<FunctionType>()->getCallConv() !=
-+      D->getType()->getAs<FunctionType>()->getCallConv())
-+    return true;
-+
-   return TryEmitDefinitionAsAlias(GlobalDecl(D, Dtor_Base),
-                                   GlobalDecl(BaseD, Dtor_Base),
-                                   false);
Index: patches/patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp
===================================================================
RCS file: patches/patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp
diff -N patches/patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp
--- patches/patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp 12 Sep 2014 12:39:47 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,17 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp,v 1.1 2014/09/12 12:39:47 brad Exp $
-
-r205331
-Debug info: fix a crash when emitting IndirectFieldDecls, which were previously
-not handled at all.
-
---- tools/clang/lib/CodeGen/CGDebugInfo.cpp.orig Thu Sep 11 20:38:24 2014
-+++ tools/clang/lib/CodeGen/CGDebugInfo.cpp Thu Sep 11 20:39:09 2014
-@@ -1258,7 +1258,7 @@ CollectTemplateParams(const TemplateParameterList *TPL
-         V = CGM.GetAddrOfFunction(FD);
-       // Member data pointers have special handling too to compute the fixed
-       // offset within the object.
--      if (isa<FieldDecl>(D)) {
-+      if (isa<FieldDecl>(D) || isa<IndirectFieldDecl>(D)) {
-         // These five lines (& possibly the above member function pointer
-         // handling) might be able to be refactored to use similar code in
-         // CodeGenModule::getMemberPointerConstant
Index: patches/patch-tools_clang_lib_CodeGen_TargetInfo_cpp
===================================================================
RCS file: patches/patch-tools_clang_lib_CodeGen_TargetInfo_cpp
diff -N patches/patch-tools_clang_lib_CodeGen_TargetInfo_cpp
--- patches/patch-tools_clang_lib_CodeGen_TargetInfo_cpp 16 Dec 2014 21:10:31 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,129 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_CodeGen_TargetInfo_cpp,v 1.1 2014/12/16 21:10:31 brad Exp $
-
-r221170
-Implement vaarg lowering for ppc32. Lowering of scalars and
-aggregates is supported. Complex numbers are not.
-
---- tools/clang/lib/CodeGen/TargetInfo.cpp.orig Tue Dec 16 12:53:59 2014
-+++ tools/clang/lib/CodeGen/TargetInfo.cpp Tue Dec 16 13:53:28 2014
-@@ -2838,12 +2838,20 @@ llvm::Value *NaClX86_64ABIInfo::EmitVAArg(llvm::Value
-
-
- // PowerPC-32
--
- namespace {
--class PPC32TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
-+/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
-+class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
- public:
--  PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
-+  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
-
-+  llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
-+                         CodeGenFunction &CGF) const;
-+};
-+
-+class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
-+public:
-+  PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT)) {}
-+
-   int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const {
-     // This is recovered from gcc output.
-     return 1; // r1 is the dedicated stack pointer
-@@ -2853,6 +2861,96 @@ class PPC32TargetCodeGenInfo : public DefaultTargetCod
-                                llvm::Value *Address) const;
- };
-
-+}
-+
-+llvm::Value *PPC32_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr,
-+                                           QualType Ty,
-+                                           CodeGenFunction &CGF) const {
-+  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
-+    // TODO: Implement this. For now ignore.
-+    (void)CTy;
-+    return NULL;
-+  }
-+
-+  bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
-+  bool isInt = Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
-+  llvm::Type *CharPtr = CGF.Int8PtrTy;
-+  llvm::Type *CharPtrPtr = CGF.Int8PtrPtrTy;
-+
-+  CGBuilderTy &Builder = CGF.Builder;
-+  llvm::Value *GPRPtr = Builder.CreateBitCast(VAListAddr, CharPtr, "gprptr");
-+  llvm::Value *GPRPtrAsInt = Builder.CreatePtrToInt(GPRPtr, CGF.Int32Ty);
-+  llvm::Value *FPRPtrAsInt = Builder.CreateAdd(GPRPtrAsInt, Builder.getInt32(1));
-+  llvm::Value *FPRPtr = Builder.CreateIntToPtr(FPRPtrAsInt, CharPtr);
-+  llvm::Value *OverflowAreaPtrAsInt = Builder.CreateAdd(FPRPtrAsInt, Builder.getInt32(3));
-+  llvm::Value *OverflowAreaPtr = Builder.CreateIntToPtr(OverflowAreaPtrAsInt, CharPtrPtr);
-+  llvm::Value *RegsaveAreaPtrAsInt = Builder.CreateAdd(OverflowAreaPtrAsInt, Builder.getInt32(4));
-+  llvm::Value *RegsaveAreaPtr = Builder.CreateIntToPtr(RegsaveAreaPtrAsInt, CharPtrPtr);
-+  llvm::Value *GPR = Builder.CreateLoad(GPRPtr, false, "gpr");
-+  // Align GPR when TY is i64.
-+  if (isI64) {
-+    llvm::Value *GPRAnd = Builder.CreateAnd(GPR, Builder.getInt8(1));
-+    llvm::Value *CC64 = Builder.CreateICmpEQ(GPRAnd, Builder.getInt8(1));
-+    llvm::Value *GPRPlusOne = Builder.CreateAdd(GPR, Builder.getInt8(1));
-+    GPR = Builder.CreateSelect(CC64, GPRPlusOne, GPR);
-+  }
-+  llvm::Value *FPR = Builder.CreateLoad(FPRPtr, false, "fpr");
-+  llvm::Value *OverflowArea = Builder.CreateLoad(OverflowAreaPtr, false, "overflow_area");
-+  llvm::Value *OverflowAreaAsInt = Builder.CreatePtrToInt(OverflowArea, CGF.Int32Ty);
-+  llvm::Value *RegsaveArea = Builder.CreateLoad(RegsaveAreaPtr, false, "regsave_area");
-+  llvm::Value *RegsaveAreaAsInt = Builder.CreatePtrToInt(RegsaveArea, CGF.Int32Ty);
-+
-+  llvm::Value *CC = Builder.CreateICmpULT(isInt ? GPR : FPR,
-+                                          Builder.getInt8(8), "cond");
-+
-+  llvm::Value *RegConstant = Builder.CreateMul(isInt ? GPR : FPR,
-+                                               Builder.getInt8(isInt ? 4 : 8));
-+
-+  llvm::Value *OurReg = Builder.CreateAdd(RegsaveAreaAsInt, Builder.CreateSExt(RegConstant, CGF.Int32Ty));
-+
-+  if (Ty->isFloatingType())
-+    OurReg = Builder.CreateAdd(OurReg, Builder.getInt32(32));
-+
-+  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
-+  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
-+  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
-+
-+  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
-+
-+  CGF.EmitBlock(UsingRegs);
-+
-+  llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
-+  llvm::Value *Result1 = Builder.CreateIntToPtr(OurReg, PTy);
-+  // Increase the GPR/FPR indexes.
-+  if (isInt) {
-+    GPR = Builder.CreateAdd(GPR, Builder.getInt8(isI64 ? 2 : 1));
-+    Builder.CreateStore(GPR, GPRPtr);
-+  } else {
-+    FPR = Builder.CreateAdd(FPR, Builder.getInt8(1));
-+    Builder.CreateStore(FPR, FPRPtr);
-+  }
-+  CGF.EmitBranch(Cont);
-+
-+  CGF.EmitBlock(UsingOverflow);
-+
-+  // Increase the overflow area.
-+  llvm::Value *Result2 = Builder.CreateIntToPtr(OverflowAreaAsInt, PTy);
-+  OverflowAreaAsInt = Builder.CreateAdd(OverflowAreaAsInt, Builder.getInt32(isInt ? 4 : 8));
-+  Builder.CreateStore(Builder.CreateIntToPtr(OverflowAreaAsInt, CharPtr), OverflowAreaPtr);
-+  CGF.EmitBranch(Cont);
-+
-+  CGF.EmitBlock(Cont);
-+
-+  llvm::PHINode *Result = CGF.Builder.CreatePHI(PTy, 2, "vaarg.addr");
-+  Result->addIncoming(Result1, UsingRegs);
-+  Result->addIncoming(Result2, UsingOverflow);
-+
-+  if (Ty->isAggregateType()) {
-+    llvm::Value *AGGPtr = Builder.CreateBitCast(Result, CharPtrPtr, "aggrptr")  ;
-+    return Builder.CreateLoad(AGGPtr, false, "aggr");
-+  }
-+
-+  return Result;
- }
-
- bool
Index: patches/patch-tools_clang_lib_Driver_ToolChain_cpp
===================================================================
RCS file: patches/patch-tools_clang_lib_Driver_ToolChain_cpp
diff -N patches/patch-tools_clang_lib_Driver_ToolChain_cpp
--- patches/patch-tools_clang_lib_Driver_ToolChain_cpp 9 Apr 2015 22:25:02 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,48 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_Driver_ToolChain_cpp,v 1.1 2015/04/09 22:25:02 sthen Exp $
-
-r211785
-Implement the -fuse-ld= option.
-
-This commit implements the -fuse-ld= option, so that the user
-can specify -fuse-ld=bfd to use ld.bfd.
-
---- tools/clang/lib/Driver/ToolChain.cpp.orig Thu Feb 26 07:04:19 2015
-+++ tools/clang/lib/Driver/ToolChain.cpp Thu Feb 26 07:05:21 2015
-@@ -15,6 +15,7 @@
- #include "clang/Driver/Options.h"
- #include "clang/Driver/SanitizerArgs.h"
- #include "clang/Driver/ToolChain.h"
-+#include "llvm/ADT/SmallString.h"
- #include "llvm/ADT/StringSwitch.h"
- #include "llvm/Option/Arg.h"
- #include "llvm/Option/ArgList.h"
-@@ -145,6 +146,29 @@ std::string ToolChain::GetFilePath(const char *Name) c
-
- std::string ToolChain::GetProgramPath(const char *Name) const {
-   return D.GetProgramPath(Name, *this);
-+}
-+
-+std::string ToolChain::GetLinkerPath() const {
-+  if (Arg *A = Args.getLastArg(options::OPT_fuse_ld_EQ)) {
-+    StringRef Suffix = A->getValue();
-+
-+    // If we're passed -fuse-ld= with no argument, or with the argument ld,
-+    // then use whatever the default system linker is.
-+    if (Suffix.empty() || Suffix == "ld")
-+      return GetProgramPath("ld");
-+
-+    llvm::SmallString<8> LinkerName("ld.");
-+    LinkerName.append(Suffix);
-+
-+    std::string LinkerPath(GetProgramPath(LinkerName.c_str()));
-+    if (llvm::sys::fs::exists(LinkerPath))
-+      return LinkerPath;
-+
-+    getDriver().Diag(diag::err_drv_invalid_linker_name) << A->getAsString(Args);
-+    return "";
-+  }
-+
-+  return GetProgramPath("ld");
- }
-
- types::ID ToolChain::LookupTypeForExtension(const char *Ext) const {
Index: patches/patch-tools_clang_lib_Driver_ToolChains_cpp
===================================================================
RCS file: patches/patch-tools_clang_lib_Driver_ToolChains_cpp
diff -N patches/patch-tools_clang_lib_Driver_ToolChains_cpp
--- patches/patch-tools_clang_lib_Driver_ToolChains_cpp 9 Apr 2015 22:25:02 -0000 1.4
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,36 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_Driver_ToolChains_cpp,v 1.4 2015/04/09 22:25:02 sthen Exp $
-
-r225958
-Use the integrated assembler by default on 32-bit PowerPC and SPARC.
-
-r211785
-Implement the -fuse-ld= option.
-
-This commit implements the -fuse-ld= option, so that the user
-can specify -fuse-ld=bfd to use ld.bfd.
-
---- tools/clang/lib/Driver/ToolChains.cpp.orig Sun Mar  2 22:03:41 2014
-+++ tools/clang/lib/Driver/ToolChains.cpp Thu Feb 26 07:06:45 2015
-@@ -2035,7 +2035,12 @@ bool Generic_GCC::IsIntegratedAssemblerDefault() const
-          getTriple().getArch() == llvm::Triple::aarch64 ||
-          getTriple().getArch() == llvm::Triple::aarch64_be ||
-          getTriple().getArch() == llvm::Triple::arm ||
--         getTriple().getArch() == llvm::Triple::thumb;
-+         getTriple().getArch() == llvm::Triple::thumb ||
-+         getTriple().getArch() == llvm::Triple::ppc ||
-+         getTriple().getArch() == llvm::Triple::ppc64 ||
-+         getTriple().getArch() == llvm::Triple::ppc64le ||
-+         getTriple().getArch() == llvm::Triple::sparc ||
-+         getTriple().getArch() == llvm::Triple::sparcv9;
- }
-
- void Generic_ELF::addClangTargetOptions(const ArgList &DriverArgs,
-@@ -2850,7 +2855,7 @@ Linux::Linux(const Driver &D, const llvm::Triple &Trip
-   PPaths.push_back(Twine(GCCInstallation.getParentLibPath() + "/../" +
-                          GCCInstallation.getTriple().str() + "/bin").str());
-
--  Linker = GetProgramPath("ld");
-+  Linker = GetLinkerPath();
-
-   Distro Distro = DetectDistro(Arch);
-
Index: patches/patch-tools_clang_lib_Driver_ToolChains_h
===================================================================
RCS file: patches/patch-tools_clang_lib_Driver_ToolChains_h
diff -N patches/patch-tools_clang_lib_Driver_ToolChains_h
--- patches/patch-tools_clang_lib_Driver_ToolChains_h 11 Feb 2015 00:29:05 -0000 1.11
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,44 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_Driver_ToolChains_h,v 1.11 2015/02/11 00:29:05 brad Exp $
-
-r209432
-Use stack protector strong by default on OpenBSD
-
-r225958
-Use the integrated assembler by default on 32-bit PowerPC and SPARC.
-
---- tools/clang/lib/Driver/ToolChains.h.orig Sun Mar  2 22:03:41 2014
-+++ tools/clang/lib/Driver/ToolChains.h Mon Feb  2 11:05:30 2015
-@@ -538,7 +538,7 @@ class LLVM_LIBRARY_VISIBILITY OpenBSD : public Generic
-   virtual bool isPIEDefault() const { return true; }
-
-   virtual unsigned GetDefaultStackProtectorLevel(bool KernelOrKext) const {
--    return 1;
-+    return 2;
-   }
-
- protected:
-@@ -582,12 +582,6 @@ class LLVM_LIBRARY_VISIBILITY FreeBSD : public Generic
-   virtual void
-   AddClangCXXStdlibIncludeArgs(const llvm::opt::ArgList &DriverArgs,
-                                llvm::opt::ArgStringList &CC1Args) const;
--  virtual bool IsIntegratedAssemblerDefault() const {
--    if (getTriple().getArch() == llvm::Triple::ppc ||
--        getTriple().getArch() == llvm::Triple::ppc64)
--      return true;
--    return Generic_ELF::IsIntegratedAssemblerDefault();
--  }
-
-   virtual bool UseSjLjExceptions() const;
-   virtual bool isPIEDefault() const;
-@@ -611,11 +605,6 @@ class LLVM_LIBRARY_VISIBILITY NetBSD : public Generic_
-                                llvm::opt::ArgStringList &CC1Args) const;
-   virtual bool IsUnwindTablesDefault() const {
-     return true;
--  }
--  virtual bool IsIntegratedAssemblerDefault() const {
--    if (getTriple().getArch() == llvm::Triple::ppc)
--      return true;
--    return Generic_ELF::IsIntegratedAssemblerDefault();
-   }
-
- protected:
Index: patches/patch-tools_clang_lib_Driver_Tools_cpp
===================================================================
RCS file: patches/patch-tools_clang_lib_Driver_Tools_cpp
diff -N patches/patch-tools_clang_lib_Driver_Tools_cpp
--- patches/patch-tools_clang_lib_Driver_Tools_cpp 4 Jun 2015 09:04:44 -0000 1.26
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,219 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_Driver_Tools_cpp,v 1.26 2015/06/04 09:04:44 ajacoutot Exp $
-
-r212838
-Handle SPARC float command line parameters for SPARCv9.
-
-r216029
-Handle SPARC float command line parameters for SPARCv9.
-
-r211624
-Use appropriate default PIE settings for OpenBSD.
-
-r239028
-Use the appropriate PIE level for OpenBSD/sparc.
-
-r210883
-Use dwarf-2 by default on OpenBSD and FreeBSD.
-
-r209479
-Don't reduce the stack protector level given -fstack-protector.
-
-r211785
-Implement the -fuse-ld= option.
-
-This commit implements the -fuse-ld= option, so that the user
-can specify -fuse-ld=bfd to use ld.bfd.
-
---- tools/clang/lib/Driver/Tools.cpp.orig Sun Mar  2 22:03:41 2014
-+++ tools/clang/lib/Driver/Tools.cpp Tue Jun  2 16:46:10 2015
-@@ -1150,7 +1150,7 @@ static std::string getR600TargetGPU(const ArgList &Arg
- }
-
- static void getSparcTargetFeatures(const ArgList &Args,
--                                   std::vector<const char *> Features) {
-+                                   std::vector<const char *> &Features) {
-   bool SoftFloatABI = true;
-   if (Arg *A =
-           Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float)) {
-@@ -1165,7 +1165,7 @@ void Clang::AddSparcTargetArgs(const ArgList &Args,
-                              ArgStringList &CmdArgs) const {
-   const Driver &D = getToolChain().getDriver();
-
--  // Select the float ABI as determined by -msoft-float, -mhard-float, and
-+  // Select the float ABI as determined by -msoft-float and -mhard-float.
-   StringRef FloatABI;
-   if (Arg *A = Args.getLastArg(options::OPT_msoft_float,
-                                options::OPT_mhard_float)) {
-@@ -1486,6 +1486,7 @@ static void getTargetFeatures(const Driver &D, const l
-     getPPCTargetFeatures(Args, Features);
-     break;
-   case llvm::Triple::sparc:
-+  case llvm::Triple::sparcv9:
-     getSparcTargetFeatures(Args, Features);
-     break;
-   case llvm::Triple::aarch64:
-@@ -2261,6 +2262,27 @@ void Clang::ConstructJob(Compilation &C, const JobActi
-     }
-   }
-
-+  // OpenBSD-specific defaults for PIE
-+  if (getToolChain().getTriple().getOS() == llvm::Triple::OpenBSD) {
-+    switch (getToolChain().getTriple().getArch()) {
-+    case llvm::Triple::mips64:
-+    case llvm::Triple::mips64el:
-+    case llvm::Triple::x86:
-+    case llvm::Triple::x86_64:
-+      IsPICLevelTwo = false; // "-fpie"
-+      break;
-+
-+    case llvm::Triple::ppc:
-+    case llvm::Triple::sparc:
-+    case llvm::Triple::sparcv9:
-+      IsPICLevelTwo = true; // "-fPIE"
-+      break;
-+
-+    default:
-+      break;
-+    }
-+  }
-+
-   // For the PIC and PIE flag options, this logic is different from the
-   // legacy logic in very old versions of GCC, as that logic was just
-   // a bug no one had ever fixed. This logic is both more rational and
-@@ -2631,6 +2653,7 @@ void Clang::ConstructJob(Compilation &C, const JobActi
-     break;
-
-   case llvm::Triple::sparc:
-+  case llvm::Triple::sparcv9:
-     AddSparcTargetArgs(Args, CmdArgs);
-     break;
-
-@@ -2696,8 +2719,10 @@ void Clang::ConstructJob(Compilation &C, const JobActi
-       // FIXME: we should support specifying dwarf version with
-       // -gline-tables-only.
-       CmdArgs.push_back("-gline-tables-only");
--      // Default is dwarf-2 for darwin.
--      if (getToolChain().getTriple().isOSDarwin())
-+      // Default is dwarf-2 for Darwin, OpenBSD and FreeBSD.
-+      const llvm::Triple &Triple = getToolChain().getTriple();
-+      if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::OpenBSD ||
-+          Triple.getOS() == llvm::Triple::FreeBSD)
-         CmdArgs.push_back("-gdwarf-2");
-     } else if (A->getOption().matches(options::OPT_gdwarf_2))
-       CmdArgs.push_back("-gdwarf-2");
-@@ -2707,8 +2732,10 @@ void Clang::ConstructJob(Compilation &C, const JobActi
-       CmdArgs.push_back("-gdwarf-4");
-     else if (!A->getOption().matches(options::OPT_g0) &&
-              !A->getOption().matches(options::OPT_ggdb0)) {
--      // Default is dwarf-2 for darwin.
--      if (getToolChain().getTriple().isOSDarwin())
-+      // Default is dwarf-2 for Darwin, OpenBSD and FreeBSD.
-+      const llvm::Triple &Triple = getToolChain().getTriple();
-+      if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::OpenBSD ||
-+          Triple.getOS() == llvm::Triple::FreeBSD)
-         CmdArgs.push_back("-gdwarf-2");
-       else
-         CmdArgs.push_back("-g");
-@@ -3197,9 +3224,10 @@ void Clang::ConstructJob(Compilation &C, const JobActi
-                                options::OPT_fstack_protector_all,
-                                options::OPT_fstack_protector_strong,
-                                options::OPT_fstack_protector)) {
--    if (A->getOption().matches(options::OPT_fstack_protector))
--      StackProtectorLevel = LangOptions::SSPOn;
--    else if (A->getOption().matches(options::OPT_fstack_protector_strong))
-+    if (A->getOption().matches(options::OPT_fstack_protector)) {
-+      StackProtectorLevel = std::max<unsigned>(LangOptions::SSPOn,
-+        getToolChain().GetDefaultStackProtectorLevel(KernelOrKext));
-+    } else if (A->getOption().matches(options::OPT_fstack_protector_strong))
-       StackProtectorLevel = LangOptions::SSPStrong;
-     else if (A->getOption().matches(options::OPT_fstack_protector_all))
-       StackProtectorLevel = LangOptions::SSPReq;
-@@ -5281,7 +5309,7 @@ void darwin::Link::ConstructJob(Compilation &C, const
-   Args.AddAllArgs(CmdArgs, options::OPT_F);
-
-   const char *Exec =
--    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
-+    Args.MakeArgString(getToolChain().GetLinkerPath());
-   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
- }
-
-@@ -5478,7 +5506,7 @@ void solaris::Link::ConstructJob(Compilation &C, const
-   addProfileRT(getToolChain(), Args, CmdArgs);
-
-   const char *Exec =
--    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
-+    Args.MakeArgString(getToolChain().GetLinkerPath());
-   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
- }
-
-@@ -5590,7 +5618,7 @@ void auroraux::Link::ConstructJob(Compilation &C, cons
-   addProfileRT(getToolChain(), Args, CmdArgs);
-
-   const char *Exec =
--    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
-+    Args.MakeArgString(getToolChain().GetLinkerPath());
-   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
- }
-
-@@ -5743,6 +5771,7 @@ void openbsd::Link::ConstructJob(Compilation &C, const
-                                        "/4.2.1"));
-
-   Args.AddAllArgs(CmdArgs, options::OPT_L);
-+  Args.AddAllArgs(CmdArgs, options::OPT_R);
-   Args.AddAllArgs(CmdArgs, options::OPT_T_Group);
-   Args.AddAllArgs(CmdArgs, options::OPT_e);
-   Args.AddAllArgs(CmdArgs, options::OPT_s);
-@@ -5795,7 +5824,7 @@ void openbsd::Link::ConstructJob(Compilation &C, const
-   }
-
-   const char *Exec =
--    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
-+    Args.MakeArgString(getToolChain().GetLinkerPath());
-   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
- }
-
-@@ -5935,7 +5964,7 @@ void bitrig::Link::ConstructJob(Compilation &C, const
-   }
-
-   const char *Exec =
--    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
-+    Args.MakeArgString(getToolChain().GetLinkerPath());
-   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
- }
-
-@@ -6200,7 +6229,7 @@ void freebsd::Link::ConstructJob(Compilation &C, const
-   addProfileRT(ToolChain, Args, CmdArgs);
-
-   const char *Exec =
--    Args.MakeArgString(ToolChain.GetProgramPath("ld"));
-+    Args.MakeArgString(ToolChain.GetLinkerPath());
-   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
- }
-
-@@ -6448,7 +6477,7 @@ void netbsd::Link::ConstructJob(Compilation &C, const
-
-   addProfileRT(getToolChain(), Args, CmdArgs);
-
--  const char *Exec = Args.MakeArgString(getToolChain().GetProgramPath("ld"));
-+  const char *Exec = Args.MakeArgString(getToolChain().GetLinkerPath());
-   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
- }
-
-@@ -6964,7 +6993,7 @@ void minix::Link::ConstructJob(Compilation &C, const J
-          Args.MakeArgString(getToolChain().GetFilePath("crtend.o")));
-   }
-
--  const char *Exec = Args.MakeArgString(getToolChain().GetProgramPath("ld"));
-+  const char *Exec = Args.MakeArgString(getToolChain().GetLinkerPath());
-   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
- }
-
-@@ -7148,7 +7177,7 @@ void dragonfly::Link::ConstructJob(Compilation &C, con
-   addProfileRT(getToolChain(), Args, CmdArgs);
-
-   const char *Exec =
--    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
-+    Args.MakeArgString(getToolChain().GetLinkerPath());
-   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
- }
-
Index: patches/patch-tools_clang_lib_Headers_xmmintrin_h
===================================================================
RCS file: patches/patch-tools_clang_lib_Headers_xmmintrin_h
diff -N patches/patch-tools_clang_lib_Headers_xmmintrin_h
--- patches/patch-tools_clang_lib_Headers_xmmintrin_h 13 Jun 2014 22:29:40 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,18 +0,0 @@
-$OpenBSD: patch-tools_clang_lib_Headers_xmmintrin_h,v 1.1 2014/06/13 22:29:40 brad Exp $
-
-r209489
-The last step of _mm_cvtps_pi16 should use _mm_packs_pi32, which is a function
-that reads two __m64 values and packs four 32-bit values into four 16-bit
-values.
-
---- tools/clang/lib/Headers/xmmintrin.h.orig Thu Jun  5 00:06:01 2014
-+++ tools/clang/lib/Headers/xmmintrin.h Thu Jun  5 00:06:36 2014
-@@ -905,7 +905,7 @@ _mm_cvtps_pi16(__m128 __a)
-   __a = _mm_movehl_ps(__a, __a);
-   __c = _mm_cvtps_pi32(__a);
-  
--  return _mm_packs_pi16(__b, __c);
-+  return _mm_packs_pi32(__b, __c);
- }
-
- static __inline__ __m64 __attribute__((__always_inline__, __nodebug__))
Index: patches/patch-tools_clang_tools_scan-build_scan-build
===================================================================
RCS file: /cvs/ports/devel/llvm/patches/patch-tools_clang_tools_scan-build_scan-build,v
retrieving revision 1.6
diff -u -p -r1.6 patch-tools_clang_tools_scan-build_scan-build
--- patches/patch-tools_clang_tools_scan-build_scan-build 18 Apr 2014 09:30:48 -0000 1.6
+++ patches/patch-tools_clang_tools_scan-build_scan-build 23 Jan 2016 18:38:52 -0000
@@ -1,7 +1,7 @@
 $OpenBSD: patch-tools_clang_tools_scan-build_scan-build,v 1.6 2014/04/18 09:30:48 brad Exp $
---- tools/clang/tools/scan-build/scan-build.orig Mon Feb 24 21:55:37 2014
-+++ tools/clang/tools/scan-build/scan-build Mon Feb 24 22:03:55 2014
-@@ -419,7 +419,7 @@ sub CopyFiles {
+--- tools/clang/tools/scan-build/scan-build.orig Thu Jul  2 00:35:29 2015
++++ tools/clang/tools/scan-build/scan-build Tue Sep  8 21:55:38 2015
+@@ -437,7 +437,7 @@ sub CopyFiles {
 
    my $Dir = shift;
 
@@ -10,7 +10,7 @@ $OpenBSD: patch-tools_clang_tools_scan-b
 
    DieDiag("Cannot find 'sorttable.js'.\n")
      if (! -r $JS);
-@@ -429,7 +429,7 @@ sub CopyFiles {
+@@ -447,7 +447,7 @@ sub CopyFiles {
    DieDiag("Could not copy 'sorttable.js' to '$Dir'.\n")
      if (! -r "$Dir/sorttable.js");
 
Index: patches/patch-tools_llvm-config_llvm-config_cpp
===================================================================
RCS file: patches/patch-tools_llvm-config_llvm-config_cpp
diff -N patches/patch-tools_llvm-config_llvm-config_cpp
--- patches/patch-tools_llvm-config_llvm-config_cpp 22 Jan 2015 12:29:36 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,54 +0,0 @@
-$OpenBSD: patch-tools_llvm-config_llvm-config_cpp,v 1.1 2015/01/22 12:29:36 brad Exp $
-
-r202719
-Don't emit a blank line when running llvm-config --system-libs.
-
---- tools/llvm-config/llvm-config.cpp.orig Thu Jan 22 06:25:33 2015
-+++ tools/llvm-config/llvm-config.cpp Thu Jan 22 06:30:40 2015
-@@ -345,27 +345,29 @@ int main(int argc, char **argv) {
-     ComputeLibsForComponents(Components, RequiredLibs,
-                              /*IncludeNonInstalled=*/IsInDevelopmentTree);
-
--    for (unsigned i = 0, e = RequiredLibs.size(); i != e; ++i) {
--      StringRef Lib = RequiredLibs[i];
--      if (i)
--        OS << ' ';
-+    if (PrintLibs || PrintLibNames || PrintLibFiles) {
-+      for (unsigned i = 0, e = RequiredLibs.size(); i != e; ++i) {
-+        StringRef Lib = RequiredLibs[i];
-+        if (i)
-+          OS << ' ';
-
--      if (PrintLibNames) {
--        OS << Lib;
--      } else if (PrintLibFiles) {
--        OS << ActiveLibDir << '/' << Lib;
--      } else if (PrintLibs) {
--        // If this is a typical library name, include it using -l.
--        if (Lib.startswith("lib") && Lib.endswith(".a")) {
--          OS << "-l" << Lib.slice(3, Lib.size()-2);
--          continue;
--        }
-+        if (PrintLibNames) {
-+          OS << Lib;
-+        } else if (PrintLibFiles) {
-+          OS << ActiveLibDir << '/' << Lib;
-+        } else if (PrintLibs) {
-+          // If this is a typical library name, include it using -l.
-+          if (Lib.startswith("lib") && Lib.endswith(".a")) {
-+            OS << "-l" << Lib.slice(3, Lib.size()-2);
-+            continue;
-+          }
-
--        // Otherwise, print the full path.
--        OS << ActiveLibDir << '/' << Lib;
-+          // Otherwise, print the full path.
-+          OS << ActiveLibDir << '/' << Lib;
-+        }
-       }
-+      OS << '\n';
-     }
--    OS << '\n';
-
-     // Print SYSTEM_LIBS after --libs.
-     // FIXME: Each LLVM component may have its dependent system libs.
Index: pkg/PLIST
===================================================================
RCS file: /cvs/ports/devel/llvm/pkg/PLIST,v
retrieving revision 1.21
diff -u -p -r1.21 PLIST
--- pkg/PLIST 18 Apr 2014 09:30:48 -0000 1.21
+++ pkg/PLIST 23 Jan 2016 18:38:52 -0000
@@ -4,7 +4,7 @@ bin/c++-analyzer
 bin/ccc-analyzer
 bin/clang
 bin/clang++
-@bin bin/clang-${LLVM_V}
+@bin bin/clang-3.7
 @bin bin/clang-check
 bin/clang-cl
 @bin bin/clang-format
@@ -17,17 +17,22 @@ bin/git-clang-format
 @bin bin/llvm-c-test
 @bin bin/llvm-config
 @bin bin/llvm-cov
+@bin bin/llvm-cxxdump
 @bin bin/llvm-diff
 @bin bin/llvm-dis
+@bin bin/llvm-dsymutil
 @bin bin/llvm-dwarfdump
 @bin bin/llvm-extract
+bin/llvm-lib
 @bin bin/llvm-link
 @bin bin/llvm-lto
 @bin bin/llvm-mc
 @bin bin/llvm-mcmarkup
 @bin bin/llvm-nm
 @bin bin/llvm-objdump
+@bin bin/llvm-pdbdump
 @bin bin/llvm-profdata
+bin/llvm-ranlib
 @bin bin/llvm-readobj
 @bin bin/llvm-rtdyld
 @bin bin/llvm-size
@@ -35,14 +40,18 @@ bin/git-clang-format
 @bin bin/llvm-symbolizer
 @bin bin/llvm-tblgen
 @bin bin/macho-dump
+@bin bin/obj2yaml
 @bin bin/opt
 bin/scan-build
+@bin bin/verify-uselistorder
+@bin bin/yaml2obj
 include/clang/
 include/clang-c/
 include/clang-c/BuildSystem.h
 include/clang-c/CXCompilationDatabase.h
 include/clang-c/CXErrorCode.h
 include/clang-c/CXString.h
+include/clang-c/Documentation.h
 include/clang-c/Index.h
 include/clang-c/Platform.h
 include/clang/ARCMigrate/
@@ -109,6 +118,7 @@ include/clang/AST/ExprCXX.h
 include/clang/AST/ExprObjC.h
 include/clang/AST/ExternalASTSource.h
 include/clang/AST/GlobalDecl.h
+include/clang/AST/LambdaCapture.h
 include/clang/AST/Mangle.h
 include/clang/AST/MangleNumberingContext.h
 include/clang/AST/NSAPI.h
@@ -163,17 +173,23 @@ include/clang/Analysis/Analyses/PostOrde
 include/clang/Analysis/Analyses/PseudoConstantAnalysis.h
 include/clang/Analysis/Analyses/ReachableCode.h
 include/clang/Analysis/Analyses/ThreadSafety.h
+include/clang/Analysis/Analyses/ThreadSafetyCommon.h
+include/clang/Analysis/Analyses/ThreadSafetyLogical.h
+include/clang/Analysis/Analyses/ThreadSafetyOps.def
+include/clang/Analysis/Analyses/ThreadSafetyTIL.h
+include/clang/Analysis/Analyses/ThreadSafetyTraverse.h
+include/clang/Analysis/Analyses/ThreadSafetyUtil.h
 include/clang/Analysis/Analyses/UninitializedValues.h
 include/clang/Analysis/AnalysisContext.h
 include/clang/Analysis/AnalysisDiagnostic.h
 include/clang/Analysis/CFG.h
 include/clang/Analysis/CFGStmtMap.h
 include/clang/Analysis/CallGraph.h
+include/clang/Analysis/CodeInjector.h
 include/clang/Analysis/DomainSpecific/
 include/clang/Analysis/DomainSpecific/CocoaConventions.h
 include/clang/Analysis/DomainSpecific/ObjCNoReturn.h
 include/clang/Analysis/FlowSensitive/
-include/clang/Analysis/FlowSensitive/DataflowSolver.h
 include/clang/Analysis/FlowSensitive/DataflowValues.h
 include/clang/Analysis/ProgramPoint.h
 include/clang/Analysis/Support/
@@ -182,16 +198,22 @@ include/clang/Basic/
 include/clang/Basic/ABI.h
 include/clang/Basic/AddressSpaces.h
 include/clang/Basic/AllDiagnostics.h
+include/clang/Basic/AttrHasAttributeImpl.inc
 include/clang/Basic/AttrKinds.h
 include/clang/Basic/AttrList.inc
+include/clang/Basic/Attributes.h
 include/clang/Basic/Builtins.def
 include/clang/Basic/Builtins.h
 include/clang/Basic/BuiltinsAArch64.def
+include/clang/Basic/BuiltinsAMDGPU.def
 include/clang/Basic/BuiltinsARM.def
 include/clang/Basic/BuiltinsHexagon.def
+include/clang/Basic/BuiltinsLe64.def
 include/clang/Basic/BuiltinsMips.def
+include/clang/Basic/BuiltinsNEON.def
 include/clang/Basic/BuiltinsNVPTX.def
 include/clang/Basic/BuiltinsPPC.def
+include/clang/Basic/BuiltinsSystemZ.def
 include/clang/Basic/BuiltinsX86.def
 include/clang/Basic/BuiltinsXCore.def
 include/clang/Basic/CapturedStmt.h
@@ -228,7 +250,6 @@ include/clang/Basic/Linkage.h
 include/clang/Basic/MacroBuilder.h
 include/clang/Basic/Module.h
 include/clang/Basic/ObjCRuntime.h
-include/clang/Basic/OnDiskHashTable.h
 include/clang/Basic/OpenCLExtensions.def
 include/clang/Basic/OpenMPKinds.def
 include/clang/Basic/OpenMPKinds.h
@@ -238,7 +259,9 @@ include/clang/Basic/OperatorPrecedence.h
 include/clang/Basic/PartialDiagnostic.h
 include/clang/Basic/PlistSupport.h
 include/clang/Basic/PrettyStackTrace.h
+include/clang/Basic/SanitizerBlacklist.h
 include/clang/Basic/Sanitizers.def
+include/clang/Basic/Sanitizers.h
 include/clang/Basic/SourceLocation.h
 include/clang/Basic/SourceManager.h
 include/clang/Basic/SourceManagerInternals.h
@@ -263,11 +286,11 @@ include/clang/CodeGen/CGFunctionInfo.h
 include/clang/CodeGen/CodeGenABITypes.h
 include/clang/CodeGen/CodeGenAction.h
 include/clang/CodeGen/ModuleBuilder.h
+include/clang/CodeGen/ObjectFilePCHContainerOperations.h
 include/clang/Config/
+include/clang/Config/config.h
 include/clang/Driver/
 include/clang/Driver/Action.h
-include/clang/Driver/CC1AsOptions.h
-include/clang/Driver/CC1AsOptions.inc
 include/clang/Driver/Compilation.h
 include/clang/Driver/Driver.h
 include/clang/Driver/DriverDiagnostic.h
@@ -294,7 +317,6 @@ include/clang/Frontend/
 include/clang/Frontend/ASTConsumers.h
 include/clang/Frontend/ASTUnit.h
 include/clang/Frontend/ChainedDiagnosticConsumer.h
-include/clang/Frontend/ChainedIncludesSource.h
 include/clang/Frontend/CodeGenOptions.def
 include/clang/Frontend/CodeGenOptions.h
 include/clang/Frontend/CommandLineSourceLoc.h
@@ -313,8 +335,11 @@ include/clang/Frontend/LayoutOverrideSou
 include/clang/Frontend/LogDiagnosticPrinter.h
 include/clang/Frontend/MigratorOptions.h
 include/clang/Frontend/MultiplexConsumer.h
+include/clang/Frontend/PCHContainerOperations.h
 include/clang/Frontend/PreprocessorOutputOptions.h
 include/clang/Frontend/SerializedDiagnosticPrinter.h
+include/clang/Frontend/SerializedDiagnosticReader.h
+include/clang/Frontend/SerializedDiagnostics.h
 include/clang/Frontend/TextDiagnostic.h
 include/clang/Frontend/TextDiagnosticBuffer.h
 include/clang/Frontend/TextDiagnosticPrinter.h
@@ -326,7 +351,6 @@ include/clang/Index/
 include/clang/Index/CommentToXML.h
 include/clang/Index/USRGeneration.h
 include/clang/Lex/
-include/clang/Lex/AttrSpellings.inc
 include/clang/Lex/CodeCompletionHandler.h
 include/clang/Lex/DirectoryLookup.h
 include/clang/Lex/ExternalPreprocessorSource.h
@@ -363,6 +387,7 @@ include/clang/Rewrite/
 include/clang/Rewrite/Core/
 include/clang/Rewrite/Core/DeltaTree.h
 include/clang/Rewrite/Core/HTMLRewrite.h
+include/clang/Rewrite/Core/RewriteBuffer.h
 include/clang/Rewrite/Core/RewriteRope.h
 include/clang/Rewrite/Core/Rewriter.h
 include/clang/Rewrite/Core/TokenRewriter.h
@@ -390,6 +415,7 @@ include/clang/Sema/IdentifierResolver.h
 include/clang/Sema/Initialization.h
 include/clang/Sema/LocInfoType.h
 include/clang/Sema/Lookup.h
+include/clang/Sema/LoopHint.h
 include/clang/Sema/MultiplexExternalSemaSource.h
 include/clang/Sema/ObjCMethodList.h
 include/clang/Sema/Overload.h
@@ -472,11 +498,14 @@ include/clang/StaticAnalyzer/Frontend/
 include/clang/StaticAnalyzer/Frontend/AnalysisConsumer.h
 include/clang/StaticAnalyzer/Frontend/CheckerRegistration.h
 include/clang/StaticAnalyzer/Frontend/FrontendActions.h
+include/clang/StaticAnalyzer/Frontend/ModelConsumer.h
 include/clang/Tooling/
 include/clang/Tooling/ArgumentsAdjusters.h
 include/clang/Tooling/CommonOptionsParser.h
 include/clang/Tooling/CompilationDatabase.h
 include/clang/Tooling/CompilationDatabasePluginRegistry.h
+include/clang/Tooling/Core/
+include/clang/Tooling/Core/Replacement.h
 include/clang/Tooling/FileMatchTrie.h
 include/clang/Tooling/JSONCompilationDatabase.h
 include/clang/Tooling/Refactoring.h
@@ -517,11 +546,11 @@ include/llvm/ADT/DenseMap.h
 include/llvm/ADT/DenseMapInfo.h
 include/llvm/ADT/DenseSet.h
 include/llvm/ADT/DepthFirstIterator.h
+include/llvm/ADT/EpochTracker.h
 include/llvm/ADT/EquivalenceClasses.h
 include/llvm/ADT/FoldingSet.h
 include/llvm/ADT/GraphTraits.h
 include/llvm/ADT/Hashing.h
-include/llvm/ADT/ImmutableIntervalMap.h
 include/llvm/ADT/ImmutableList.h
 include/llvm/ADT/ImmutableMap.h
 include/llvm/ADT/ImmutableSet.h
@@ -532,7 +561,6 @@ include/llvm/ADT/IntrusiveRefCntPtr.h
 include/llvm/ADT/MapVector.h
 include/llvm/ADT/None.h
 include/llvm/ADT/Optional.h
-include/llvm/ADT/OwningPtr.h
 include/llvm/ADT/PackedVector.h
 include/llvm/ADT/PointerIntPair.h
 include/llvm/ADT/PointerUnion.h
@@ -561,55 +589,60 @@ include/llvm/ADT/TinyPtrVector.h
 include/llvm/ADT/Triple.h
 include/llvm/ADT/Twine.h
 include/llvm/ADT/UniqueVector.h
-include/llvm/ADT/ValueMap.h
 include/llvm/ADT/VariadicFunction.h
 include/llvm/ADT/edit_distance.h
 include/llvm/ADT/ilist.h
 include/llvm/ADT/ilist_node.h
-include/llvm/ADT/polymorphic_ptr.h
+include/llvm/ADT/iterator.h
+include/llvm/ADT/iterator_range.h
 include/llvm/Analysis/
 include/llvm/Analysis/AliasAnalysis.h
 include/llvm/Analysis/AliasSetTracker.h
-include/llvm/Analysis/BlockFrequencyImpl.h
+include/llvm/Analysis/AssumptionCache.h
 include/llvm/Analysis/BlockFrequencyInfo.h
+include/llvm/Analysis/BlockFrequencyInfoImpl.h
 include/llvm/Analysis/BranchProbabilityInfo.h
 include/llvm/Analysis/CFG.h
 include/llvm/Analysis/CFGPrinter.h
+include/llvm/Analysis/CGSCCPassManager.h
 include/llvm/Analysis/CallGraph.h
 include/llvm/Analysis/CallGraphSCCPass.h
 include/llvm/Analysis/CallPrinter.h
 include/llvm/Analysis/CaptureTracking.h
 include/llvm/Analysis/CodeMetrics.h
 include/llvm/Analysis/ConstantFolding.h
-include/llvm/Analysis/ConstantsScanner.h
 include/llvm/Analysis/DOTGraphTraitsPass.h
 include/llvm/Analysis/DependenceAnalysis.h
 include/llvm/Analysis/DomPrinter.h
 include/llvm/Analysis/DominanceFrontier.h
-include/llvm/Analysis/FindUsedTypes.h
+include/llvm/Analysis/DominanceFrontierImpl.h
 include/llvm/Analysis/IVUsers.h
 include/llvm/Analysis/InlineCost.h
 include/llvm/Analysis/InstructionSimplify.h
 include/llvm/Analysis/Interval.h
 include/llvm/Analysis/IntervalIterator.h
 include/llvm/Analysis/IntervalPartition.h
+include/llvm/Analysis/IteratedDominanceFrontier.h
 include/llvm/Analysis/LazyCallGraph.h
 include/llvm/Analysis/LazyValueInfo.h
 include/llvm/Analysis/LibCallAliasAnalysis.h
 include/llvm/Analysis/LibCallSemantics.h
 include/llvm/Analysis/Lint.h
 include/llvm/Analysis/Loads.h
+include/llvm/Analysis/LoopAccessAnalysis.h
 include/llvm/Analysis/LoopInfo.h
 include/llvm/Analysis/LoopInfoImpl.h
 include/llvm/Analysis/LoopIterator.h
 include/llvm/Analysis/LoopPass.h
 include/llvm/Analysis/MemoryBuiltins.h
 include/llvm/Analysis/MemoryDependenceAnalysis.h
+include/llvm/Analysis/MemoryLocation.h
 include/llvm/Analysis/PHITransAddr.h
 include/llvm/Analysis/Passes.h
 include/llvm/Analysis/PostDominators.h
 include/llvm/Analysis/PtrUseVisitor.h
 include/llvm/Analysis/RegionInfo.h
+include/llvm/Analysis/RegionInfoImpl.h
 include/llvm/Analysis/RegionIterator.h
 include/llvm/Analysis/RegionPass.h
 include/llvm/Analysis/RegionPrinter.h
@@ -618,12 +651,17 @@ include/llvm/Analysis/ScalarEvolutionExp
 include/llvm/Analysis/ScalarEvolutionExpressions.h
 include/llvm/Analysis/ScalarEvolutionNormalization.h
 include/llvm/Analysis/SparsePropagation.h
+include/llvm/Analysis/TargetFolder.h
+include/llvm/Analysis/TargetLibraryInfo.def
+include/llvm/Analysis/TargetLibraryInfo.h
 include/llvm/Analysis/TargetTransformInfo.h
+include/llvm/Analysis/TargetTransformInfoImpl.h
 include/llvm/Analysis/Trace.h
 include/llvm/Analysis/ValueTracking.h
+include/llvm/Analysis/VectorUtils.h
 include/llvm/AsmParser/
 include/llvm/AsmParser/Parser.h
-include/llvm/AutoUpgrade.h
+include/llvm/AsmParser/SlotMapping.h
 include/llvm/Bitcode/
 include/llvm/Bitcode/BitCodes.h
 include/llvm/Bitcode/BitcodeWriterPass.h
@@ -634,13 +672,18 @@ include/llvm/Bitcode/ReaderWriter.h
 include/llvm/CodeGen/
 include/llvm/CodeGen/Analysis.h
 include/llvm/CodeGen/AsmPrinter.h
+include/llvm/CodeGen/BasicTTIImpl.h
 include/llvm/CodeGen/CalcSpillWeights.h
 include/llvm/CodeGen/CallingConvLower.h
 include/llvm/CodeGen/CommandFlags.h
 include/llvm/CodeGen/DAGCombine.h
 include/llvm/CodeGen/DFAPacketizer.h
+include/llvm/CodeGen/DIE.h
+include/llvm/CodeGen/DIEValue.def
+include/llvm/CodeGen/DwarfStringPoolEntry.h
 include/llvm/CodeGen/EdgeBundles.h
 include/llvm/CodeGen/FastISel.h
+include/llvm/CodeGen/FaultMaps.h
 include/llvm/CodeGen/FunctionLoweringInfo.h
 include/llvm/CodeGen/GCMetadata.h
 include/llvm/CodeGen/GCMetadataPrinter.h
@@ -648,7 +691,6 @@ include/llvm/CodeGen/GCStrategy.h
 include/llvm/CodeGen/GCs.h
 include/llvm/CodeGen/ISDOpcodes.h
 include/llvm/CodeGen/IntrinsicLowering.h
-include/llvm/CodeGen/JITCodeEmitter.h
 include/llvm/CodeGen/LatencyPriorityQueue.h
 include/llvm/CodeGen/LexicalScopes.h
 include/llvm/CodeGen/LinkAllAsmWriterComponents.h
@@ -661,17 +703,21 @@ include/llvm/CodeGen/LiveRangeEdit.h
 include/llvm/CodeGen/LiveRegMatrix.h
 include/llvm/CodeGen/LiveStackAnalysis.h
 include/llvm/CodeGen/LiveVariables.h
+include/llvm/CodeGen/MIRParser/
+include/llvm/CodeGen/MIRParser/MIRParser.h
+include/llvm/CodeGen/MIRYamlMapping.h
 include/llvm/CodeGen/MachORelocation.h
 include/llvm/CodeGen/MachineBasicBlock.h
 include/llvm/CodeGen/MachineBlockFrequencyInfo.h
 include/llvm/CodeGen/MachineBranchProbabilityInfo.h
-include/llvm/CodeGen/MachineCodeEmitter.h
-include/llvm/CodeGen/MachineCodeInfo.h
+include/llvm/CodeGen/MachineCombinerPattern.h
 include/llvm/CodeGen/MachineConstantPool.h
+include/llvm/CodeGen/MachineDominanceFrontier.h
 include/llvm/CodeGen/MachineDominators.h
 include/llvm/CodeGen/MachineFrameInfo.h
 include/llvm/CodeGen/MachineFunction.h
 include/llvm/CodeGen/MachineFunctionAnalysis.h
+include/llvm/CodeGen/MachineFunctionInitializer.h
 include/llvm/CodeGen/MachineFunctionPass.h
 include/llvm/CodeGen/MachineInstr.h
 include/llvm/CodeGen/MachineInstrBuilder.h
@@ -684,19 +730,19 @@ include/llvm/CodeGen/MachineModuleInfoIm
 include/llvm/CodeGen/MachineOperand.h
 include/llvm/CodeGen/MachinePassRegistry.h
 include/llvm/CodeGen/MachinePostDominators.h
+include/llvm/CodeGen/MachineRegionInfo.h
 include/llvm/CodeGen/MachineRegisterInfo.h
-include/llvm/CodeGen/MachineRelocation.h
 include/llvm/CodeGen/MachineSSAUpdater.h
 include/llvm/CodeGen/MachineScheduler.h
 include/llvm/CodeGen/MachineTraceMetrics.h
+include/llvm/CodeGen/MachineValueType.h
 include/llvm/CodeGen/PBQP/
+include/llvm/CodeGen/PBQP/CostAllocator.h
 include/llvm/CodeGen/PBQP/Graph.h
-include/llvm/CodeGen/PBQP/HeuristicBase.h
-include/llvm/CodeGen/PBQP/HeuristicSolver.h
-include/llvm/CodeGen/PBQP/Heuristics/
-include/llvm/CodeGen/PBQP/Heuristics/Briggs.h
 include/llvm/CodeGen/PBQP/Math.h
+include/llvm/CodeGen/PBQP/ReductionRules.h
 include/llvm/CodeGen/PBQP/Solution.h
+include/llvm/CodeGen/PBQPRAConstraint.h
 include/llvm/CodeGen/Passes.h
 include/llvm/CodeGen/PseudoSourceValue.h
 include/llvm/CodeGen/RegAllocPBQP.h
@@ -716,7 +762,6 @@ include/llvm/CodeGen/SelectionDAG.h
 include/llvm/CodeGen/SelectionDAGISel.h
 include/llvm/CodeGen/SelectionDAGNodes.h
 include/llvm/CodeGen/SlotIndexes.h
-include/llvm/CodeGen/StackMapLivenessAnalysis.h
 include/llvm/CodeGen/StackMaps.h
 include/llvm/CodeGen/StackProtector.h
 include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
@@ -724,54 +769,155 @@ include/llvm/CodeGen/TargetSchedule.h
 include/llvm/CodeGen/ValueTypes.h
 include/llvm/CodeGen/ValueTypes.td
 include/llvm/CodeGen/VirtRegMap.h
+include/llvm/CodeGen/WinEHFuncInfo.h
 include/llvm/Config/
 include/llvm/Config/AsmParsers.def
 include/llvm/Config/AsmPrinters.def
 include/llvm/Config/Disassemblers.def
 include/llvm/Config/Targets.def
-include/llvm/Config/config.h
 include/llvm/Config/llvm-config.h
-include/llvm/DIBuilder.h
 include/llvm/DebugInfo/
-include/llvm/DebugInfo.h
 include/llvm/DebugInfo/DIContext.h
-include/llvm/DebugInfo/DWARFFormValue.h
+include/llvm/DebugInfo/DWARF/
+include/llvm/DebugInfo/DWARF/DWARFAbbreviationDeclaration.h
+include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
+include/llvm/DebugInfo/DWARF/DWARFCompileUnit.h
+include/llvm/DebugInfo/DWARF/DWARFContext.h
+include/llvm/DebugInfo/DWARF/DWARFDebugAbbrev.h
+include/llvm/DebugInfo/DWARF/DWARFDebugArangeSet.h
+include/llvm/DebugInfo/DWARF/DWARFDebugAranges.h
+include/llvm/DebugInfo/DWARF/DWARFDebugFrame.h
+include/llvm/DebugInfo/DWARF/DWARFDebugInfoEntry.h
+include/llvm/DebugInfo/DWARF/DWARFDebugLine.h
+include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h
+include/llvm/DebugInfo/DWARF/DWARFDebugRangeList.h
+include/llvm/DebugInfo/DWARF/DWARFFormValue.h
+include/llvm/DebugInfo/DWARF/DWARFRelocMap.h
+include/llvm/DebugInfo/DWARF/DWARFSection.h
+include/llvm/DebugInfo/DWARF/DWARFTypeUnit.h
+include/llvm/DebugInfo/DWARF/DWARFUnit.h
+include/llvm/DebugInfo/PDB/
+include/llvm/DebugInfo/PDB/ConcreteSymbolEnumerator.h
+include/llvm/DebugInfo/PDB/DIA/
+include/llvm/DebugInfo/PDB/DIA/DIADataStream.h
+include/llvm/DebugInfo/PDB/DIA/DIAEnumDebugStreams.h
+include/llvm/DebugInfo/PDB/DIA/DIAEnumLineNumbers.h
+include/llvm/DebugInfo/PDB/DIA/DIAEnumSourceFiles.h
+include/llvm/DebugInfo/PDB/DIA/DIAEnumSymbols.h
+include/llvm/DebugInfo/PDB/DIA/DIALineNumber.h
+include/llvm/DebugInfo/PDB/DIA/DIARawSymbol.h
+include/llvm/DebugInfo/PDB/DIA/DIASession.h
+include/llvm/DebugInfo/PDB/DIA/DIASourceFile.h
+include/llvm/DebugInfo/PDB/DIA/DIASupport.h
+include/llvm/DebugInfo/PDB/IPDBDataStream.h
+include/llvm/DebugInfo/PDB/IPDBEnumChildren.h
+include/llvm/DebugInfo/PDB/IPDBLineNumber.h
+include/llvm/DebugInfo/PDB/IPDBRawSymbol.h
+include/llvm/DebugInfo/PDB/IPDBSession.h
+include/llvm/DebugInfo/PDB/IPDBSourceFile.h
+include/llvm/DebugInfo/PDB/PDB.h
+include/llvm/DebugInfo/PDB/PDBContext.h
+include/llvm/DebugInfo/PDB/PDBExtras.h
+include/llvm/DebugInfo/PDB/PDBSymDumper.h
+include/llvm/DebugInfo/PDB/PDBSymbol.h
+include/llvm/DebugInfo/PDB/PDBSymbolAnnotation.h
+include/llvm/DebugInfo/PDB/PDBSymbolBlock.h
+include/llvm/DebugInfo/PDB/PDBSymbolCompiland.h
+include/llvm/DebugInfo/PDB/PDBSymbolCompilandDetails.h
+include/llvm/DebugInfo/PDB/PDBSymbolCompilandEnv.h
+include/llvm/DebugInfo/PDB/PDBSymbolCustom.h
+include/llvm/DebugInfo/PDB/PDBSymbolData.h
+include/llvm/DebugInfo/PDB/PDBSymbolExe.h
+include/llvm/DebugInfo/PDB/PDBSymbolFunc.h
+include/llvm/DebugInfo/PDB/PDBSymbolFuncDebugEnd.h
+include/llvm/DebugInfo/PDB/PDBSymbolFuncDebugStart.h
+include/llvm/DebugInfo/PDB/PDBSymbolLabel.h
+include/llvm/DebugInfo/PDB/PDBSymbolPublicSymbol.h
+include/llvm/DebugInfo/PDB/PDBSymbolThunk.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeArray.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeBaseClass.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeBuiltin.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeCustom.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeDimension.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeEnum.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeFriend.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeFunctionArg.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeFunctionSig.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeManaged.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypePointer.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeTypedef.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeUDT.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeVTable.h
+include/llvm/DebugInfo/PDB/PDBSymbolTypeVTableShape.h
+include/llvm/DebugInfo/PDB/PDBSymbolUnknown.h
+include/llvm/DebugInfo/PDB/PDBSymbolUsingNamespace.h
+include/llvm/DebugInfo/PDB/PDBTypes.h
 include/llvm/ExecutionEngine/
 include/llvm/ExecutionEngine/ExecutionEngine.h
 include/llvm/ExecutionEngine/GenericValue.h
 include/llvm/ExecutionEngine/Interpreter.h
-include/llvm/ExecutionEngine/JIT.h
 include/llvm/ExecutionEngine/JITEventListener.h
-include/llvm/ExecutionEngine/JITMemoryManager.h
+include/llvm/ExecutionEngine/JITSymbolFlags.h
 include/llvm/ExecutionEngine/MCJIT.h
 include/llvm/ExecutionEngine/OProfileWrapper.h
-include/llvm/ExecutionEngine/ObjectBuffer.h
 include/llvm/ExecutionEngine/ObjectCache.h
-include/llvm/ExecutionEngine/ObjectImage.h
+include/llvm/ExecutionEngine/ObjectMemoryBuffer.h
+include/llvm/ExecutionEngine/Orc/
+include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h
+include/llvm/ExecutionEngine/Orc/CompileUtils.h
+include/llvm/ExecutionEngine/Orc/ExecutionUtils.h
+include/llvm/ExecutionEngine/Orc/IRCompileLayer.h
+include/llvm/ExecutionEngine/Orc/IRTransformLayer.h
+include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
+include/llvm/ExecutionEngine/Orc/JITSymbol.h
+include/llvm/ExecutionEngine/Orc/LambdaResolver.h
+include/llvm/ExecutionEngine/Orc/LazyEmittingLayer.h
+include/llvm/ExecutionEngine/Orc/LogicalDylib.h
+include/llvm/ExecutionEngine/Orc/NullResolver.h
+include/llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h
+include/llvm/ExecutionEngine/Orc/ObjectTransformLayer.h
+include/llvm/ExecutionEngine/Orc/OrcTargetSupport.h
+include/llvm/ExecutionEngine/OrcMCJITReplacement.h
 include/llvm/ExecutionEngine/RTDyldMemoryManager.h
 include/llvm/ExecutionEngine/RuntimeDyld.h
+include/llvm/ExecutionEngine/RuntimeDyldChecker.h
 include/llvm/ExecutionEngine/SectionMemoryManager.h
-include/llvm/GVMaterializer.h
 include/llvm/IR/
 include/llvm/IR/Argument.h
 include/llvm/IR/AssemblyAnnotationWriter.h
 include/llvm/IR/Attributes.h
+include/llvm/IR/AutoUpgrade.h
 include/llvm/IR/BasicBlock.h
+include/llvm/IR/CFG.h
+include/llvm/IR/CallSite.h
 include/llvm/IR/CallingConv.h
+include/llvm/IR/Comdat.h
 include/llvm/IR/Constant.h
+include/llvm/IR/ConstantFolder.h
+include/llvm/IR/ConstantRange.h
 include/llvm/IR/Constants.h
+include/llvm/IR/DIBuilder.h
 include/llvm/IR/DataLayout.h
+include/llvm/IR/DebugInfo.h
+include/llvm/IR/DebugInfoFlags.def
+include/llvm/IR/DebugInfoMetadata.h
+include/llvm/IR/DebugLoc.h
 include/llvm/IR/DerivedTypes.h
 include/llvm/IR/DiagnosticInfo.h
 include/llvm/IR/DiagnosticPrinter.h
 include/llvm/IR/Dominators.h
 include/llvm/IR/Function.h
+include/llvm/IR/GVMaterializer.h
+include/llvm/IR/GetElementPtrTypeIterator.h
 include/llvm/IR/GlobalAlias.h
+include/llvm/IR/GlobalObject.h
 include/llvm/IR/GlobalValue.h
 include/llvm/IR/GlobalVariable.h
 include/llvm/IR/IRBuilder.h
 include/llvm/IR/IRPrintingPasses.h
 include/llvm/IR/InlineAsm.h
+include/llvm/IR/InstIterator.h
+include/llvm/IR/InstVisitor.h
 include/llvm/IR/InstrTypes.h
 include/llvm/IR/Instruction.def
 include/llvm/IR/Instruction.h
@@ -781,46 +927,67 @@ include/llvm/IR/Intrinsics.gen
 include/llvm/IR/Intrinsics.h
 include/llvm/IR/Intrinsics.td
 include/llvm/IR/IntrinsicsAArch64.td
+include/llvm/IR/IntrinsicsAMDGPU.td
 include/llvm/IR/IntrinsicsARM.td
+include/llvm/IR/IntrinsicsBPF.td
 include/llvm/IR/IntrinsicsHexagon.td
 include/llvm/IR/IntrinsicsMips.td
 include/llvm/IR/IntrinsicsNVVM.td
 include/llvm/IR/IntrinsicsPowerPC.td
-include/llvm/IR/IntrinsicsR600.td
+include/llvm/IR/IntrinsicsSystemZ.td
+include/llvm/IR/IntrinsicsWebAssembly.td
 include/llvm/IR/IntrinsicsX86.td
 include/llvm/IR/IntrinsicsXCore.td
 include/llvm/IR/LLVMContext.h
 include/llvm/IR/LegacyPassManager.h
 include/llvm/IR/LegacyPassManagers.h
+include/llvm/IR/LegacyPassNameParser.h
 include/llvm/IR/MDBuilder.h
 include/llvm/IR/Mangler.h
+include/llvm/IR/Metadata.def
 include/llvm/IR/Metadata.h
+include/llvm/IR/MetadataTracking.h
 include/llvm/IR/Module.h
+include/llvm/IR/ModuleSlotTracker.h
+include/llvm/IR/NoFolder.h
 include/llvm/IR/OperandTraits.h
 include/llvm/IR/Operator.h
 include/llvm/IR/PassManager.h
+include/llvm/IR/PassManagerInternal.h
+include/llvm/IR/PatternMatch.h
+include/llvm/IR/PredIteratorCache.h
+include/llvm/IR/Statepoint.h
 include/llvm/IR/SymbolTableListTraits.h
+include/llvm/IR/TrackingMDRef.h
 include/llvm/IR/Type.h
 include/llvm/IR/TypeBuilder.h
 include/llvm/IR/TypeFinder.h
 include/llvm/IR/Use.h
+include/llvm/IR/UseListOrder.h
 include/llvm/IR/User.h
+include/llvm/IR/Value.def
 include/llvm/IR/Value.h
+include/llvm/IR/ValueHandle.h
+include/llvm/IR/ValueMap.h
 include/llvm/IR/ValueSymbolTable.h
 include/llvm/IR/Verifier.h
 include/llvm/IRReader/
 include/llvm/IRReader/IRReader.h
 include/llvm/InitializePasses.h
-include/llvm/InstVisitor.h
 include/llvm/LTO/
 include/llvm/LTO/LTOCodeGenerator.h
 include/llvm/LTO/LTOModule.h
+include/llvm/LibDriver/
+include/llvm/LibDriver/LibDriver.h
 include/llvm/LineEditor/
 include/llvm/LineEditor/LineEditor.h
 include/llvm/LinkAllIR.h
 include/llvm/LinkAllPasses.h
-include/llvm/Linker.h
+include/llvm/Linker/
+include/llvm/Linker/Linker.h
 include/llvm/MC/
+include/llvm/MC/ConstantPools.h
+include/llvm/MC/MCAnalysis/
 include/llvm/MC/MCAsmBackend.h
 include/llvm/MC/MCAsmInfo.h
 include/llvm/MC/MCAsmInfoCOFF.h
@@ -828,23 +995,19 @@ include/llvm/MC/MCAsmInfoDarwin.h
 include/llvm/MC/MCAsmInfoELF.h
 include/llvm/MC/MCAsmLayout.h
 include/llvm/MC/MCAssembler.h
-include/llvm/MC/MCAtom.h
 include/llvm/MC/MCCodeEmitter.h
 include/llvm/MC/MCCodeGenInfo.h
 include/llvm/MC/MCContext.h
 include/llvm/MC/MCDirectives.h
 include/llvm/MC/MCDisassembler.h
 include/llvm/MC/MCDwarf.h
-include/llvm/MC/MCELF.h
 include/llvm/MC/MCELFObjectWriter.h
 include/llvm/MC/MCELFStreamer.h
-include/llvm/MC/MCELFSymbolFlags.h
 include/llvm/MC/MCExpr.h
 include/llvm/MC/MCExternalSymbolizer.h
 include/llvm/MC/MCFixedLenDisassembler.h
 include/llvm/MC/MCFixup.h
 include/llvm/MC/MCFixupKindInfo.h
-include/llvm/MC/MCFunction.h
 include/llvm/MC/MCInst.h
 include/llvm/MC/MCInstBuilder.h
 include/llvm/MC/MCInstPrinter.h
@@ -853,14 +1016,10 @@ include/llvm/MC/MCInstrDesc.h
 include/llvm/MC/MCInstrInfo.h
 include/llvm/MC/MCInstrItineraries.h
 include/llvm/MC/MCLabel.h
-include/llvm/MC/MCMachOSymbolFlags.h
+include/llvm/MC/MCLinkerOptimizationHint.h
 include/llvm/MC/MCMachObjectWriter.h
-include/llvm/MC/MCModule.h
-include/llvm/MC/MCModuleYAML.h
-include/llvm/MC/MCObjectDisassembler.h
 include/llvm/MC/MCObjectFileInfo.h
 include/llvm/MC/MCObjectStreamer.h
-include/llvm/MC/MCObjectSymbolizer.h
 include/llvm/MC/MCObjectWriter.h
 include/llvm/MC/MCParser/
 include/llvm/MC/MCParser/AsmCond.h
@@ -868,6 +1027,7 @@ include/llvm/MC/MCParser/AsmLexer.h
 include/llvm/MC/MCParser/MCAsmLexer.h
 include/llvm/MC/MCParser/MCAsmParser.h
 include/llvm/MC/MCParser/MCAsmParserExtension.h
+include/llvm/MC/MCParser/MCAsmParserUtils.h
 include/llvm/MC/MCParser/MCParsedAsmOperand.h
 include/llvm/MC/MCRegisterInfo.h
 include/llvm/MC/MCRelocationInfo.h
@@ -879,16 +1039,26 @@ include/llvm/MC/MCSectionMachO.h
 include/llvm/MC/MCStreamer.h
 include/llvm/MC/MCSubtargetInfo.h
 include/llvm/MC/MCSymbol.h
+include/llvm/MC/MCSymbolCOFF.h
+include/llvm/MC/MCSymbolELF.h
+include/llvm/MC/MCSymbolMachO.h
 include/llvm/MC/MCSymbolizer.h
 include/llvm/MC/MCTargetAsmParser.h
+include/llvm/MC/MCTargetOptions.h
+include/llvm/MC/MCTargetOptionsCommandFlags.h
 include/llvm/MC/MCValue.h
 include/llvm/MC/MCWin64EH.h
 include/llvm/MC/MCWinCOFFObjectWriter.h
+include/llvm/MC/MCWinCOFFStreamer.h
+include/llvm/MC/MCWinEH.h
 include/llvm/MC/MachineLocation.h
 include/llvm/MC/SectionKind.h
+include/llvm/MC/StringTableBuilder.h
 include/llvm/MC/SubtargetFeature.h
+include/llvm/MC/YAML.h
 include/llvm/Object/
 include/llvm/Object/Archive.h
+include/llvm/Object/ArchiveWriter.h
 include/llvm/Object/Binary.h
 include/llvm/Object/COFF.h
 include/llvm/Object/COFFYAML.h
@@ -902,8 +1072,9 @@ include/llvm/Object/MachO.h
 include/llvm/Object/MachOUniversal.h
 include/llvm/Object/ObjectFile.h
 include/llvm/Object/RelocVisitor.h
+include/llvm/Object/StackMapParser.h
+include/llvm/Object/SymbolSize.h
 include/llvm/Object/SymbolicFile.h
-include/llvm/Object/YAML.h
 include/llvm/Option/
 include/llvm/Option/Arg.h
 include/llvm/Option/ArgList.h
@@ -913,13 +1084,26 @@ include/llvm/Option/OptTable.h
 include/llvm/Option/Option.h
 include/llvm/Pass.h
 include/llvm/PassAnalysisSupport.h
-include/llvm/PassManager.h
+include/llvm/PassInfo.h
 include/llvm/PassRegistry.h
 include/llvm/PassSupport.h
+include/llvm/Passes/
+include/llvm/Passes/PassBuilder.h
+include/llvm/ProfileData/
+include/llvm/ProfileData/CoverageMapping.h
+include/llvm/ProfileData/CoverageMappingReader.h
+include/llvm/ProfileData/CoverageMappingWriter.h
+include/llvm/ProfileData/InstrProf.h
+include/llvm/ProfileData/InstrProfReader.h
+include/llvm/ProfileData/InstrProfWriter.h
+include/llvm/ProfileData/SampleProf.h
+include/llvm/ProfileData/SampleProfReader.h
+include/llvm/ProfileData/SampleProfWriter.h
 include/llvm/Support/
 include/llvm/Support/AIXDataTypesFix.h
 include/llvm/Support/ARMBuildAttributes.h
 include/llvm/Support/ARMEHABI.h
+include/llvm/Support/ARMWinEH.h
 include/llvm/Support/AlignOf.h
 include/llvm/Support/Allocator.h
 include/llvm/Support/ArrayRecycler.h
@@ -927,35 +1111,42 @@ include/llvm/Support/Atomic.h
 include/llvm/Support/BlockFrequency.h
 include/llvm/Support/BranchProbability.h
 include/llvm/Support/CBindingWrapping.h
-include/llvm/Support/CFG.h
 include/llvm/Support/COFF.h
-include/llvm/Support/CallSite.h
+include/llvm/Support/COM.h
 include/llvm/Support/Capacity.h
 include/llvm/Support/Casting.h
 include/llvm/Support/CodeGen.h
 include/llvm/Support/CommandLine.h
 include/llvm/Support/Compiler.h
 include/llvm/Support/Compression.h
-include/llvm/Support/ConstantFolder.h
-include/llvm/Support/ConstantRange.h
 include/llvm/Support/ConvertUTF.h
 include/llvm/Support/CrashRecoveryContext.h
 include/llvm/Support/DOTGraphTraits.h
 include/llvm/Support/DataExtractor.h
-include/llvm/Support/DataFlow.h
 include/llvm/Support/DataStream.h
 include/llvm/Support/DataTypes.h
 include/llvm/Support/Debug.h
-include/llvm/Support/DebugLoc.h
-include/llvm/Support/Disassembler.h
+include/llvm/Support/Dwarf.def
 include/llvm/Support/Dwarf.h
 include/llvm/Support/DynamicLibrary.h
 include/llvm/Support/ELF.h
+include/llvm/Support/ELFRelocs/
+include/llvm/Support/ELFRelocs/AArch64.def
+include/llvm/Support/ELFRelocs/ARM.def
+include/llvm/Support/ELFRelocs/Hexagon.def
+include/llvm/Support/ELFRelocs/Mips.def
+include/llvm/Support/ELFRelocs/PowerPC.def
+include/llvm/Support/ELFRelocs/PowerPC64.def
+include/llvm/Support/ELFRelocs/Sparc.def
+include/llvm/Support/ELFRelocs/SystemZ.def
+include/llvm/Support/ELFRelocs/i386.def
+include/llvm/Support/ELFRelocs/x86_64.def
 include/llvm/Support/Endian.h
+include/llvm/Support/EndianStream.h
+include/llvm/Support/Errc.h
 include/llvm/Support/Errno.h
 include/llvm/Support/ErrorHandling.h
 include/llvm/Support/ErrorOr.h
-include/llvm/Support/FEnv.h
 include/llvm/Support/FileOutputBuffer.h
 include/llvm/Support/FileSystem.h
 include/llvm/Support/FileUtilities.h
@@ -964,14 +1155,10 @@ include/llvm/Support/FormattedStream.h
 include/llvm/Support/GCOV.h
 include/llvm/Support/GenericDomTree.h
 include/llvm/Support/GenericDomTreeConstruction.h
-include/llvm/Support/GetElementPtrTypeIterator.h
 include/llvm/Support/GraphWriter.h
 include/llvm/Support/Host.h
-include/llvm/Support/IncludeFile.h
-include/llvm/Support/InstIterator.h
 include/llvm/Support/LEB128.h
 include/llvm/Support/LICENSE.TXT
-include/llvm/Support/LeakDetector.h
 include/llvm/Support/LineIterator.h
 include/llvm/Support/Locale.h
 include/llvm/Support/LockFileManager.h
@@ -982,20 +1169,20 @@ include/llvm/Support/MathExtras.h
 include/llvm/Support/Memory.h
 include/llvm/Support/MemoryBuffer.h
 include/llvm/Support/MemoryObject.h
+include/llvm/Support/MipsABIFlags.h
 include/llvm/Support/Mutex.h
 include/llvm/Support/MutexGuard.h
-include/llvm/Support/NoFolder.h
+include/llvm/Support/OnDiskHashTable.h
+include/llvm/Support/Options.h
 include/llvm/Support/OutputBuffer.h
-include/llvm/Support/PassNameParser.h
 include/llvm/Support/Path.h
-include/llvm/Support/PatternMatch.h
 include/llvm/Support/PluginLoader.h
 include/llvm/Support/PointerLikeTypeTraits.h
-include/llvm/Support/PredIteratorCache.h
 include/llvm/Support/PrettyStackTrace.h
 include/llvm/Support/Process.h
 include/llvm/Support/Program.h
 include/llvm/Support/RWMutex.h
+include/llvm/Support/RandomNumberGenerator.h
 include/llvm/Support/Recycler.h
 include/llvm/Support/RecyclingAllocator.h
 include/llvm/Support/Regex.h
@@ -1003,15 +1190,17 @@ include/llvm/Support/Registry.h
 include/llvm/Support/RegistryParser.h
 include/llvm/Support/SMLoc.h
 include/llvm/Support/SaveAndRestore.h
+include/llvm/Support/ScaledNumber.h
 include/llvm/Support/Signals.h
 include/llvm/Support/Solaris.h
 include/llvm/Support/SourceMgr.h
-include/llvm/Support/StreamableMemoryObject.h
+include/llvm/Support/SpecialCaseList.h
+include/llvm/Support/StreamingMemoryObject.h
 include/llvm/Support/StringPool.h
-include/llvm/Support/StringRefMemoryObject.h
+include/llvm/Support/StringSaver.h
 include/llvm/Support/SwapByteOrder.h
 include/llvm/Support/SystemUtils.h
-include/llvm/Support/TargetFolder.h
+include/llvm/Support/TargetParser.h
 include/llvm/Support/TargetRegistry.h
 include/llvm/Support/TargetSelect.h
 include/llvm/Support/ThreadLocal.h
@@ -1021,21 +1210,22 @@ include/llvm/Support/Timer.h
 include/llvm/Support/ToolOutputFile.h
 include/llvm/Support/Unicode.h
 include/llvm/Support/UnicodeCharRanges.h
+include/llvm/Support/UniqueLock.h
 include/llvm/Support/Valgrind.h
-include/llvm/Support/ValueHandle.h
 include/llvm/Support/Watchdog.h
 include/llvm/Support/Win64EH.h
+include/llvm/Support/WindowsError.h
 include/llvm/Support/YAMLParser.h
 include/llvm/Support/YAMLTraits.h
 include/llvm/Support/circular_raw_ostream.h
 include/llvm/Support/raw_os_ostream.h
 include/llvm/Support/raw_ostream.h
-include/llvm/Support/system_error.h
 include/llvm/Support/type_traits.h
 include/llvm/TableGen/
 include/llvm/TableGen/Error.h
 include/llvm/TableGen/Main.h
 include/llvm/TableGen/Record.h
+include/llvm/TableGen/SetTheory.h
 include/llvm/TableGen/StringMatcher.h
 include/llvm/TableGen/StringToOffsetTable.h
 include/llvm/TableGen/TableGenBackend.h
@@ -1048,13 +1238,12 @@ include/llvm/Target/TargetFrameLowering.
 include/llvm/Target/TargetInstrInfo.h
 include/llvm/Target/TargetIntrinsicInfo.h
 include/llvm/Target/TargetItinerary.td
-include/llvm/Target/TargetJITInfo.h
-include/llvm/Target/TargetLibraryInfo.h
 include/llvm/Target/TargetLowering.h
 include/llvm/Target/TargetLoweringObjectFile.h
 include/llvm/Target/TargetMachine.h
 include/llvm/Target/TargetOpcodes.h
 include/llvm/Target/TargetOptions.h
+include/llvm/Target/TargetRecip.h
 include/llvm/Target/TargetRegisterInfo.h
 include/llvm/Target/TargetSchedule.td
 include/llvm/Target/TargetSelectionDAG.td
@@ -1064,10 +1253,18 @@ include/llvm/Transforms/
 include/llvm/Transforms/IPO/
 include/llvm/Transforms/IPO.h
 include/llvm/Transforms/IPO/InlinerPass.h
+include/llvm/Transforms/IPO/LowerBitSets.h
 include/llvm/Transforms/IPO/PassManagerBuilder.h
+include/llvm/Transforms/InstCombine/
+include/llvm/Transforms/InstCombine/InstCombine.h
+include/llvm/Transforms/InstCombine/InstCombineWorklist.h
 include/llvm/Transforms/Instrumentation.h
 include/llvm/Transforms/ObjCARC.h
+include/llvm/Transforms/Scalar/
 include/llvm/Transforms/Scalar.h
+include/llvm/Transforms/Scalar/EarlyCSE.h
+include/llvm/Transforms/Scalar/LowerExpectIntrinsic.h
+include/llvm/Transforms/Scalar/SimplifyCFG.h
 include/llvm/Transforms/Utils/
 include/llvm/Transforms/Utils/ASanStackFrameLayout.h
 include/llvm/Transforms/Utils/BasicBlockUtils.h
@@ -1076,17 +1273,19 @@ include/llvm/Transforms/Utils/BypassSlow
 include/llvm/Transforms/Utils/Cloning.h
 include/llvm/Transforms/Utils/CmpInstAnalysis.h
 include/llvm/Transforms/Utils/CodeExtractor.h
+include/llvm/Transforms/Utils/CtorUtils.h
 include/llvm/Transforms/Utils/GlobalStatus.h
 include/llvm/Transforms/Utils/IntegerDivision.h
 include/llvm/Transforms/Utils/Local.h
 include/llvm/Transforms/Utils/LoopUtils.h
+include/llvm/Transforms/Utils/LoopVersioning.h
 include/llvm/Transforms/Utils/ModuleUtils.h
 include/llvm/Transforms/Utils/PromoteMemToReg.h
 include/llvm/Transforms/Utils/SSAUpdater.h
 include/llvm/Transforms/Utils/SSAUpdaterImpl.h
 include/llvm/Transforms/Utils/SimplifyIndVar.h
 include/llvm/Transforms/Utils/SimplifyLibCalls.h
-include/llvm/Transforms/Utils/SpecialCaseList.h
+include/llvm/Transforms/Utils/SymbolRewriter.h
 include/llvm/Transforms/Utils/UnifyFunctionExitNodes.h
 include/llvm/Transforms/Utils/UnrollLoop.h
 include/llvm/Transforms/Utils/ValueMapper.h
@@ -1097,39 +1296,58 @@ lib/clang/
 lib/clang/${LLVM_V}/
 ${CLANG_INCLUDE_PATH}/
 ${CLANG_INCLUDE_PATH}/Intrin.h
+${CLANG_INCLUDE_PATH}/__stddef_max_align_t.h
 ${CLANG_INCLUDE_PATH}/__wmmintrin_aes.h
 ${CLANG_INCLUDE_PATH}/__wmmintrin_pclmul.h
+${CLANG_INCLUDE_PATH}/adxintrin.h
 ${CLANG_INCLUDE_PATH}/altivec.h
 ${CLANG_INCLUDE_PATH}/ammintrin.h
+${CLANG_INCLUDE_PATH}/arm_acle.h
 ${CLANG_INCLUDE_PATH}/arm_neon.h
 ${CLANG_INCLUDE_PATH}/avx2intrin.h
+${CLANG_INCLUDE_PATH}/avx512bwintrin.h
+${CLANG_INCLUDE_PATH}/avx512cdintrin.h
+${CLANG_INCLUDE_PATH}/avx512dqintrin.h
+${CLANG_INCLUDE_PATH}/avx512erintrin.h
+${CLANG_INCLUDE_PATH}/avx512fintrin.h
+${CLANG_INCLUDE_PATH}/avx512vlbwintrin.h
+${CLANG_INCLUDE_PATH}/avx512vldqintrin.h
+${CLANG_INCLUDE_PATH}/avx512vlintrin.h
 ${CLANG_INCLUDE_PATH}/avxintrin.h
 ${CLANG_INCLUDE_PATH}/bmi2intrin.h
 ${CLANG_INCLUDE_PATH}/bmiintrin.h
 ${CLANG_INCLUDE_PATH}/cpuid.h
+${CLANG_INCLUDE_PATH}/cuda_builtin_vars.h
 ${CLANG_INCLUDE_PATH}/emmintrin.h
 ${CLANG_INCLUDE_PATH}/f16cintrin.h
 ${CLANG_INCLUDE_PATH}/float.h
 ${CLANG_INCLUDE_PATH}/fma4intrin.h
 ${CLANG_INCLUDE_PATH}/fmaintrin.h
+${CLANG_INCLUDE_PATH}/fxsrintrin.h
+${CLANG_INCLUDE_PATH}/htmintrin.h
+${CLANG_INCLUDE_PATH}/htmxlintrin.h
+${CLANG_INCLUDE_PATH}/ia32intrin.h
 ${CLANG_INCLUDE_PATH}/immintrin.h
+${CLANG_INCLUDE_PATH}/inttypes.h
 ${CLANG_INCLUDE_PATH}/iso646.h
 ${CLANG_INCLUDE_PATH}/limits.h
 ${CLANG_INCLUDE_PATH}/lzcntintrin.h
 ${CLANG_INCLUDE_PATH}/mm3dnow.h
 ${CLANG_INCLUDE_PATH}/mm_malloc.h
 ${CLANG_INCLUDE_PATH}/mmintrin.h
-${CLANG_INCLUDE_PATH}/module.map
+${CLANG_INCLUDE_PATH}/module.modulemap
 ${CLANG_INCLUDE_PATH}/nmmintrin.h
 ${CLANG_INCLUDE_PATH}/pmmintrin.h
 ${CLANG_INCLUDE_PATH}/popcntintrin.h
 ${CLANG_INCLUDE_PATH}/prfchwintrin.h
 ${CLANG_INCLUDE_PATH}/rdseedintrin.h
 ${CLANG_INCLUDE_PATH}/rtmintrin.h
+${CLANG_INCLUDE_PATH}/s390intrin.h
 ${CLANG_INCLUDE_PATH}/shaintrin.h
 ${CLANG_INCLUDE_PATH}/smmintrin.h
 ${CLANG_INCLUDE_PATH}/stdalign.h
 ${CLANG_INCLUDE_PATH}/stdarg.h
+${CLANG_INCLUDE_PATH}/stdatomic.h
 ${CLANG_INCLUDE_PATH}/stdbool.h
 ${CLANG_INCLUDE_PATH}/stddef.h
 ${CLANG_INCLUDE_PATH}/stdint.h
@@ -1138,11 +1356,14 @@ ${CLANG_INCLUDE_PATH}/tbmintrin.h
 ${CLANG_INCLUDE_PATH}/tgmath.h
 ${CLANG_INCLUDE_PATH}/tmmintrin.h
 ${CLANG_INCLUDE_PATH}/unwind.h
+${CLANG_INCLUDE_PATH}/vadefs.h
 ${CLANG_INCLUDE_PATH}/varargs.h
+${CLANG_INCLUDE_PATH}/vecintrin.h
 ${CLANG_INCLUDE_PATH}/wmmintrin.h
 ${CLANG_INCLUDE_PATH}/x86intrin.h
 ${CLANG_INCLUDE_PATH}/xmmintrin.h
 ${CLANG_INCLUDE_PATH}/xopintrin.h
+${CLANG_INCLUDE_PATH}/xtestintrin.h
 lib/libLLVMAArch64AsmParser.a
 lib/libLLVMAArch64AsmPrinter.a
 lib/libLLVMAArch64CodeGen.a
@@ -1150,6 +1371,12 @@ lib/libLLVMAArch64Desc.a
 lib/libLLVMAArch64Disassembler.a
 lib/libLLVMAArch64Info.a
 lib/libLLVMAArch64Utils.a
+lib/libLLVMAMDGPUAsmParser.a
+lib/libLLVMAMDGPUAsmPrinter.a
+lib/libLLVMAMDGPUCodeGen.a
+lib/libLLVMAMDGPUDesc.a
+lib/libLLVMAMDGPUInfo.a
+lib/libLLVMAMDGPUUtils.a
 lib/libLLVMARMAsmParser.a
 lib/libLLVMARMAsmPrinter.a
 lib/libLLVMARMCodeGen.a
@@ -1159,30 +1386,36 @@ lib/libLLVMARMInfo.a
 lib/libLLVMAnalysis.a
 lib/libLLVMAsmParser.a
 lib/libLLVMAsmPrinter.a
+lib/libLLVMBPFAsmPrinter.a
+lib/libLLVMBPFCodeGen.a
+lib/libLLVMBPFDesc.a
+lib/libLLVMBPFInfo.a
 lib/libLLVMBitReader.a
 lib/libLLVMBitWriter.a
 lib/libLLVMCodeGen.a
 lib/libLLVMCore.a
 lib/libLLVMCppBackendCodeGen.a
 lib/libLLVMCppBackendInfo.a
-lib/libLLVMDebugInfo.a
+lib/libLLVMDebugInfoDWARF.a
+lib/libLLVMDebugInfoPDB.a
 lib/libLLVMExecutionEngine.a
-lib/libLLVMHexagonAsmPrinter.a
 lib/libLLVMHexagonCodeGen.a
 lib/libLLVMHexagonDesc.a
+lib/libLLVMHexagonDisassembler.a
 lib/libLLVMHexagonInfo.a
 lib/libLLVMIRReader.a
 lib/libLLVMInstCombine.a
 lib/libLLVMInstrumentation.a
 lib/libLLVMInterpreter.a
-lib/libLLVMJIT.a
 lib/libLLVMLTO.a
+lib/libLLVMLibDriver.a
 lib/libLLVMLineEditor.a
 lib/libLLVMLinker.a
 lib/libLLVMMC.a
 lib/libLLVMMCDisassembler.a
 lib/libLLVMMCJIT.a
 lib/libLLVMMCParser.a
+lib/libLLVMMIRParser.a
 lib/libLLVMMSP430AsmPrinter.a
 lib/libLLVMMSP430CodeGen.a
 lib/libLLVMMSP430Desc.a
@@ -1200,16 +1433,15 @@ lib/libLLVMNVPTXInfo.a
 lib/libLLVMObjCARCOpts.a
 lib/libLLVMObject.a
 lib/libLLVMOption.a
+lib/libLLVMOrcJIT.a
+lib/libLLVMPasses.a
 lib/libLLVMPowerPCAsmParser.a
 lib/libLLVMPowerPCAsmPrinter.a
 lib/libLLVMPowerPCCodeGen.a
 lib/libLLVMPowerPCDesc.a
 lib/libLLVMPowerPCDisassembler.a
 lib/libLLVMPowerPCInfo.a
-lib/libLLVMR600AsmPrinter.a
-lib/libLLVMR600CodeGen.a
-lib/libLLVMR600Desc.a
-lib/libLLVMR600Info.a
+lib/libLLVMProfileData.a
 lib/libLLVMRuntimeDyld.a
 lib/libLLVMScalarOpts.a
 lib/libLLVMSelectionDAG.a
@@ -1244,7 +1476,7 @@ lib/libLLVMXCoreDisassembler.a
 lib/libLLVMXCoreInfo.a
 lib/libLLVMipa.a
 lib/libLLVMipo.a
-lib/libLTO.so
+@lib lib/libLTO.so.${LIBLTO_VERSION}
 @lib lib/libclang.so.${LIBclang_VERSION}
 lib/libclangARCMigrate.a
 lib/libclangAST.a
@@ -1261,7 +1493,7 @@ lib/libclangFrontendTool.a
 lib/libclangIndex.a
 lib/libclangLex.a
 lib/libclangParse.a
-lib/libclangRewriteCore.a
+lib/libclangRewrite.a
 lib/libclangRewriteFrontend.a
 lib/libclangSema.a
 lib/libclangSerialization.a
@@ -1271,7 +1503,7 @@ lib/libclangStaticAnalyzerFrontend.a
 lib/libclangTooling.a
 @comment lib/libgtest.a
 @comment lib/libgtest_main.a
-@man man/man1/FileCheck.1
+lib/libclangToolingCore.a
 @man man/man1/bugpoint.1
 @man man/man1/clang.1
 @man man/man1/llc.1
@@ -1284,6 +1516,7 @@ lib/libclangTooling.a
 @man man/man1/llvm-cov.1
 @man man/man1/llvm-diff.1
 @man man/man1/llvm-dis.1
+@man man/man1/llvm-dwarfdump.1
 @man man/man1/llvm-extract.1
 @man man/man1/llvm-link.1
 @man man/man1/llvm-nm.1
@@ -1304,16 +1537,20 @@ share/llvm/
 share/llvm/cmake/
 share/llvm/cmake/AddLLVM.cmake
 share/llvm/cmake/AddLLVMDefinitions.cmake
+share/llvm/cmake/AddOCaml.cmake
+share/llvm/cmake/AddSphinxTarget.cmake
 share/llvm/cmake/ChooseMSVCCRT.cmake
+share/llvm/cmake/CrossCompile.cmake
+share/llvm/cmake/FindOCaml.cmake
+share/llvm/cmake/FindSphinx.cmake
 share/llvm/cmake/GetSVN.cmake
 share/llvm/cmake/HandleLLVMOptions.cmake
 share/llvm/cmake/HandleLLVMStdlib.cmake
 share/llvm/cmake/LLVM-Config.cmake
 share/llvm/cmake/LLVMConfig.cmake
 share/llvm/cmake/LLVMConfigVersion.cmake
-share/llvm/cmake/LLVMExports-release.cmake
+share/llvm/cmake/LLVMExports${MODCMAKE_BUILD_SUFFIX}
 share/llvm/cmake/LLVMExports.cmake
-share/llvm/cmake/LLVMParseArguments.cmake
 share/llvm/cmake/LLVMProcessSources.cmake
 share/llvm/cmake/TableGen.cmake
 share/llvm/scanview.css

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Re: LLVM update (again)

Juan Francisco Cantero Hurtado
Can you modify the structure of devel/llvm/ to something like
devel/llvm/version/? With lang/gcc works pretty well, we can work with
the latest version while the ports tree uses the stable version by
default.


On Sat, Jan 23, 2016 at 07:39:22PM +0100, Pascal Stumpf wrote:

> So here's an updated diff for LLVM 3.7.1.  With landry@'s recent commit,
> xulrunner is no longer a showstopper.
>
>
> Index: Makefile
> ===================================================================
> RCS file: /cvs/ports/devel/llvm/Makefile,v
> retrieving revision 1.108
> diff -u -p -r1.108 Makefile
> --- Makefile 24 Aug 2015 07:45:56 -0000 1.108
> +++ Makefile 23 Jan 2016 18:38:51 -0000
> @@ -8,14 +8,17 @@ DPB_PROPERTIES = parallel
>  
>  COMMENT = modular, fast C/C++/ObjC compiler, static analyzer and tools
>  
> -LLVM_V = 3.5
> -DISTNAME = llvm-${LLVM_V}.20140228
> -REVISION = 35
> +LLVM_V = 3.7.1
> +DISTNAME = llvm-${LLVM_V}.src
> +PKGNAME = llvm-${LLVM_V}
>  CATEGORIES = devel
> -MASTER_SITES = http://comstyle.com/source/
> +DISTFILES = llvm-${LLVM_V}.src${EXTRACT_SUFX} \
> + cfe-${LLVM_V}.src${EXTRACT_SUFX}
> +MASTER_SITES = http://www.llvm.org/releases/${LLVM_V}/
>  EXTRACT_SUFX = .tar.xz
>  
> -SHARED_LIBS = clang 1.0
> +SHARED_LIBS = clang 2.0 \
> + LTO 0.0
>  
>  # packager notes in http://llvm.org/docs/Packaging.html
>  HOMEPAGE = http://www.llvm.org/
> @@ -25,15 +28,21 @@ MAINTAINER= Brad Smith <[hidden email]
>  # BSD
>  PERMIT_PACKAGE_CDROM = Yes
>  
> -WANTLIB = c m pthread stdc++ z
> +WANTLIB = c m pthread z
>  
>  MODULES = devel/cmake \
> - lang/python
> + lang/python \
> + gcc4
>  
> -TEST_DEPENDS = devel/dejagnu \
> - shells/bash
> +MODGCC4_LANGS = c c++
> +MODGCC4_ARCHS = *
> +
> +TEST_DEPENDS = devel/dejagnu \
> + shells/bash \
> + lang/gcc/${MODGCC4_VERSION},-c++
>  BUILD_DEPENDS += textproc/py-sphinx
> -RUN_DEPENDS += devel/gtest
> +RUN_DEPENDS += devel/gtest \
> + lang/gcc/${MODGCC4_VERSION},-c++
>  
>  SEPARATE_BUILD = Yes
>  CONFIGURE_ARGS = -DLLVM_ENABLE_FFI:Bool=False \
> @@ -47,22 +56,34 @@ CONFIGURE_ARGS = -DLLVM_ENABLE_FFI:Bool=
>  # introduced when PIE was enabled
>  .if ${MACHINE_ARCH} == "powerpc"
>  CONFIGURE_ARGS += -DCMAKE_EXE_LINKER_FLAGS="-Wl,--relax -nopie"
> +CONFIGURE_ARGS += -DCMAKE_SHARED_LINKER_FLAGS="-Wl,--relax -nopie"
>  .endif
>  
>  TEST_TARGET = check
>  
> +# XXX sync
> +GCC_VER = 4.9.3
> +.if ${MACHINE_ARCH} == "amd64"
> +GCC_CONFIG = x86_64-unknown-openbsd${OSREV}
> +.else
> +GCC_CONFIG = ${MACHINE_ARCH}-unknown-openbsd${OSREV}
> +.endif
>  CLANG_INCLUDE_PATH = lib/clang/${LLVM_V}/include
> -SUBST_VARS += CLANG_INCLUDE_PATH LLVM_V
> +SUBST_VARS += CLANG_INCLUDE_PATH LLVM_V GCC_VER GCC_CONFIG
> +
> +post-extract:
> + mv ${WRKDIR}/cfe-${LLVM_V}.src ${WRKSRC}/tools/clang
>  
>  pre-configure:
> - @${SUBST_CMD} ${WRKSRC}/tools/clang/tools/scan-build/scan-build
> + @${SUBST_CMD} ${WRKSRC}/tools/clang/tools/scan-build/scan-build \
> + ${WRKSRC}/tools/clang/lib/Driver/ToolChains.cpp
> + @${SUBST_CMD} ${WRKSRC}/tools/clang/tools/scan-build/scan-build \
> + ${WRKSRC}/tools/clang/lib/Driver/Tools.cpp
>   -@ln -s ${MODPY_BIN} ${WRKDIR}/bin/python
>  
>  post-build:
>   cd ${WRKSRC}/docs && make -f Makefile.sphinx man
> - pod2man --release=CVS --center="LLVM" \
> -    ${WRKSRC}/tools/clang/docs/tools/clang.pod \
> -    ${WRKSRC}/docs/_build/man/clang.1
> + cd ${WRKSRC}/tools/clang/docs && make -f Makefile.sphinx man
>  
>  post-install:
>   ${INSTALL_SCRIPT} ${WRKSRC}/tools/clang/tools/scan-build/ccc-analyzer \
> @@ -75,7 +96,10 @@ post-install:
>      ${PREFIX}/man/man1
>   ${INSTALL_DATA} ${WRKSRC}/tools/clang/tools/scan-build/scan-build.1 \
>      ${PREFIX}/man/man1
> - # lit is not installed anymore
> + ${INSTALL_DATA} ${WRKSRC}/tools/clang/docs/_build/man/clang.1 \
> +    ${PREFIX}/man/man1
> + # lit and FileCheck are not installed
>   @rm ${PREFIX}/man/man1/lit.1
> + @rm ${PREFIX}/man/man1/FileCheck.1
>  
>  .include <bsd.port.mk>
> Index: distinfo
> ===================================================================
> RCS file: /cvs/ports/devel/llvm/distinfo,v
> retrieving revision 1.13
> diff -u -p -r1.13 distinfo
> --- distinfo 18 Apr 2014 09:30:48 -0000 1.13
> +++ distinfo 23 Jan 2016 18:38:51 -0000
> @@ -1,2 +1,4 @@
> -SHA256 (llvm-3.5.20140228.tar.xz) = vBFmbVEiY2CQZf7Boqcebh+s+ejpfpoZ8vY5c3cxgXw=
> -SIZE (llvm-3.5.20140228.tar.xz) = 17945548
> +SHA256 (cfe-3.7.1.src.tar.xz) = VuIWTHwqF3LV7So+V0hf9z/wbJff8S7b7qGsxEErBnQ=
> +SHA256 (llvm-3.7.1.src.tar.xz) = vneU7QzsQtbGgsqONRdTW1RVWj3vq+yDVU28dNtUWtU=
> +SIZE (cfe-3.7.1.src.tar.xz) = 9110616
> +SIZE (llvm-3.7.1.src.tar.xz) = 14592544
> Index: patches/patch-CMakeLists_txt
> ===================================================================
> RCS file: patches/patch-CMakeLists_txt
> diff -N patches/patch-CMakeLists_txt
> --- patches/patch-CMakeLists_txt 18 Apr 2014 09:30:48 -0000 1.4
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,15 +0,0 @@
> -$OpenBSD: patch-CMakeLists_txt,v 1.4 2014/04/18 09:30:48 brad Exp $
> -
> -Don't confuse scripts who want the version with appended 'svn' goo.
> -
> ---- CMakeLists.txt.orig Sun Mar  2 21:57:43 2014
> -+++ CMakeLists.txt Sun Mar  2 22:13:02 2014
> -@@ -29,7 +29,7 @@ set(LLVM_VERSION_MAJOR 3)
> - set(LLVM_VERSION_MINOR 5)
> -
> - if (NOT PACKAGE_VERSION)
> --  set(PACKAGE_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}svn")
> -+  set(PACKAGE_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}")
> - endif()
> -
> - option(LLVM_INSTALL_TOOLCHAIN_ONLY "Only include toolchain files in the 'install' target." OFF)
> Index: patches/patch-Makefile_config_in
> ===================================================================
> RCS file: /cvs/ports/devel/llvm/patches/patch-Makefile_config_in,v
> retrieving revision 1.8
> diff -u -p -r1.8 patch-Makefile_config_in
> --- patches/patch-Makefile_config_in 18 Apr 2014 09:30:48 -0000 1.8
> +++ patches/patch-Makefile_config_in 23 Jan 2016 18:38:51 -0000
> @@ -1,7 +1,7 @@
>  $OpenBSD: patch-Makefile_config_in,v 1.8 2014/04/18 09:30:48 brad Exp $
> ---- Makefile.config.in.orig Sun Feb 16 19:19:46 2014
> -+++ Makefile.config.in Sun Feb 16 19:28:35 2014
> -@@ -99,11 +99,11 @@ endif
> +--- Makefile.config.in.orig Wed Aug 12 19:12:16 2015
> ++++ Makefile.config.in Tue Sep  8 21:53:49 2015
> +@@ -106,11 +106,11 @@ endif
>   PROJ_bindir     := $(PROJ_prefix)/bin
>   PROJ_libdir     := $(PROJ_prefix)/lib
>   PROJ_datadir    := $(PROJ_prefix)/share
> Index: patches/patch-cmake_modules_AddLLVM_cmake
> ===================================================================
> RCS file: patches/patch-cmake_modules_AddLLVM_cmake
> diff -N patches/patch-cmake_modules_AddLLVM_cmake
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ patches/patch-cmake_modules_AddLLVM_cmake 23 Jan 2016 18:38:51 -0000
> @@ -0,0 +1,12 @@
> +$OpenBSD$
> +--- cmake/modules/AddLLVM.cmake.orig Fri Sep 11 17:38:23 2015
> ++++ cmake/modules/AddLLVM.cmake Fri Sep 11 17:39:48 2015
> +@@ -178,7 +178,7 @@ function(add_link_opts target_name)
> +       elseif(${CMAKE_SYSTEM_NAME} MATCHES "SunOS")
> +         set_property(TARGET ${target_name} APPEND_STRING PROPERTY
> +                      LINK_FLAGS " -Wl,-z -Wl,discard-unused=sections")
> +-      elseif(NOT WIN32 AND NOT LLVM_LINKER_IS_GOLD)
> ++      elseif(NOT WIN32 AND NOT LLVM_LINKER_IS_GOLD AND NOT ${CMAKE_SYSTEM_NAME} MATCHES "OpenBSD")
> +         # Object files are compiled with -ffunction-data-sections.
> +         # Versions of bfd ld < 2.23.1 have a bug in --gc-sections that breaks
> +         # tools that use plugins. Always pass --gc-sections once we require
> Index: patches/patch-cmake_modules_HandleLLVMOptions_cmake
> ===================================================================
> RCS file: /cvs/ports/devel/llvm/patches/patch-cmake_modules_HandleLLVMOptions_cmake,v
> retrieving revision 1.1
> diff -u -p -r1.1 patch-cmake_modules_HandleLLVMOptions_cmake
> --- patches/patch-cmake_modules_HandleLLVMOptions_cmake 18 Apr 2014 09:30:48 -0000 1.1
> +++ patches/patch-cmake_modules_HandleLLVMOptions_cmake 23 Jan 2016 18:38:51 -0000
> @@ -1,49 +1,13 @@
> -$OpenBSD: patch-cmake_modules_HandleLLVMOptions_cmake,v 1.1 2014/04/18 09:30:48 brad Exp $
> ---- cmake/modules/HandleLLVMOptions.cmake.orig Sat Feb  8 15:05:05 2014
> -+++ cmake/modules/HandleLLVMOptions.cmake Sat Feb  8 15:05:17 2014
> -@@ -7,45 +7,6 @@ include(AddLLVMDefinitions)
> - include(CheckCCompilerFlag)
> - include(CheckCXXCompilerFlag)
> -
> --if(NOT LLVM_FORCE_USE_OLD_TOOLCHAIN)
> --  if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
> --    if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 4.7)
> --      message(FATAL_ERROR "Host GCC version must be at least 4.7!")
> --    endif()
> --  elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Clang")
> --    if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 3.1)
> --      message(FATAL_ERROR "Host Clang version must be at least 3.1!")
> --    endif()
> --
> --    # Also test that we aren't using too old of a version of libstdc++ with the
> --    # Clang compiler. This is tricky as there is no real way to check the
> --    # version of libstdc++ directly. Instead we test for a known bug in
> --    # libstdc++4.6 that is fixed in libstdc++4.7.
> --    if(NOT LLVM_ENABLE_LIBCXX)
> --      set(OLD_CMAKE_REQUIRED_FLAGS ${CMAKE_REQUIRED_FLAGS})
> --      set(OLD_CMAKE_REQUIRED_LIBRARIES ${CMAKE_REQUIRED_LIBRARIES})
> --      set(CMAKE_REQUIRED_FLAGS "-std=c++0x")
> --      if (ANDROID)
> --        set(CMAKE_REQUIRED_LIBRARIES "atomic")
> --      endif()
> --      check_cxx_source_compiles("
> --#include <atomic>
> --std::atomic<float> x(0.0f);
> --int main() { return (float)x; }"
> --        LLVM_NO_OLD_LIBSTDCXX)
> --      if(NOT LLVM_NO_OLD_LIBSTDCXX)
> --        message(FATAL_ERROR "Host Clang must be able to find libstdc++4.7 or newer!")
> --      endif()
> --      set(CMAKE_REQUIRED_FLAGS ${OLD_CMAKE_REQUIRED_FLAGS})
> --      set(CMAKE_REQUIRED_LIBRARIES ${OLD_CMAKE_REQUIRED_LIBRARIES})
> --    endif()
> --  elseif(CMAKE_CXX_COMPILER_ID MATCHES "MSVC")
> --    if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 17.0)
> --      message(FATAL_ERROR "Host Visual Studio must be at least 2012 (MSVC 17.0)")
> --    endif()
> --  endif()
> --endif()
> --
> - if( LLVM_ENABLE_ASSERTIONS )
> -   # MSVC doesn't like _DEBUG on release builds. See PR 4379.
> -   if( NOT MSVC )
> +$OpenBSD$
> +--- cmake/modules/HandleLLVMOptions.cmake.orig Wed Sep  9 14:34:05 2015
> ++++ cmake/modules/HandleLLVMOptions.cmake Wed Sep  9 14:34:55 2015
> +@@ -132,7 +132,8 @@ endif()
> + # Pass -Wl,-z,defs. This makes sure all symbols are defined. Otherwise a DSO
> + # build might work on ELF but fail on MachO/COFF.
> + if(NOT (${CMAKE_SYSTEM_NAME} MATCHES "Darwin" OR WIN32 OR CYGWIN OR
> +-        ${CMAKE_SYSTEM_NAME} MATCHES "FreeBSD") AND
> ++        ${CMAKE_SYSTEM_NAME} MATCHES "FreeBSD" OR
> ++ ${CMAKE_SYSTEM_NAME} MATCHES "OpenBSD") AND
> +    NOT LLVM_USE_SANITIZER)
> +   set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -Wl,-z,defs")
> + endif()
> Index: patches/patch-include_llvm_CodeGen_SelectionDAGISel_h
> ===================================================================
> RCS file: patches/patch-include_llvm_CodeGen_SelectionDAGISel_h
> diff -N patches/patch-include_llvm_CodeGen_SelectionDAGISel_h
> --- patches/patch-include_llvm_CodeGen_SelectionDAGISel_h 24 Aug 2015 07:45:56 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,59 +0,0 @@
> -$OpenBSD: patch-include_llvm_CodeGen_SelectionDAGISel_h,v 1.1 2015/08/24 07:45:56 ajacoutot Exp $
> -
> -r219009
> -[ISel] Keep matching state consistent when folding during X86 address match
> -
> -In the X86 backend, matching an address is initiated by the 'addr' complex
> -pattern and its friends.  During this process we may reassociate and-of-shift
> -into shift-of-and (FoldMaskedShiftToScaledMask) to allow folding of the
> -shift into the scale of the address.
> -
> -However as demonstrated by the testcase, this can trigger CSE of not only the
> -shift and the AND which the code is prepared for but also the underlying load
> -node.  In the testcase this node is sitting in the RecordedNode and MatchScope
> -data structures of the matcher and becomes a deleted node upon CSE.  Returning
> -from the complex pattern function, we try to access it again hitting an assert
> -because the node is no longer a load even though this was checked before.
> -
> -Now obviously changing the DAG this late is bending the rules but I think it
> -makes sense somewhat.  Outside of addresses we prefer and-of-shift because it
> -may lead to smaller immediates (FoldMaskAndShiftToScale is an even better
> -example because it create a non-canonical node).  We currently don't recognize
> -addresses during DAGCombiner where arguably this canonicalization should be
> -performed.  On the other hand, having this in the matcher allows us to cover
> -all the cases where an address can be used in an instruction.
> -
> -I've also talked a little bit to Dan Gohman on llvm-dev who added the RAUW for
> -the new shift node in FoldMaskedShiftToScaledMask.  This RAUW is responsible
> -for initiating the recursive CSE on users
> -(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-September/076903.html) but it
> -is not strictly necessary since the shift is hooked into the visited user.  Of
> -course it's safer to keep the DAG consistent at all times (e.g. for accurate
> -number of uses, etc.).
> -
> -So rather than changing the fundamentals, I've decided to continue along the
> -previous patches and detect the CSE.  This patch installs a very targeted
> -DAGUpdateListener for the duration of a complex-pattern match and updates the
> -matching state accordingly.  (Previous patches used HandleSDNode to detect the
> -CSE but that's not practical here).  The listener is only installed on X86.
> -
> -I tested that there is no measurable overhead due to this while running
> -through the spec2k BC files with llc.  The only thing we pay for is the
> -creation of the listener.  The callback never ever triggers in spec2k since
> -this is a corner case.
> -
> ---- include/llvm/CodeGen/SelectionDAGISel.h.orig Tue Aug  4 22:44:44 2015
> -+++ include/llvm/CodeGen/SelectionDAGISel.h Tue Aug  4 22:46:22 2015
> -@@ -238,6 +238,12 @@ class SelectionDAGISel : public MachineFunctionPass {
> -                            const unsigned char *MatcherTable,
> -                            unsigned TableSize);
> -
> -+  /// \brief Return true if complex patterns for this target can mutate the
> -+  /// DAG.
> -+  virtual bool ComplexPatternFuncMutatesDAG() const {
> -+    return false;
> -+  }
> -+
> - private:
> -
> -   // Calls to these functions are generated by tblgen.
> Index: patches/patch-include_llvm_CodeGen_SelectionDAG_h
> ===================================================================
> RCS file: patches/patch-include_llvm_CodeGen_SelectionDAG_h
> diff -N patches/patch-include_llvm_CodeGen_SelectionDAG_h
> --- patches/patch-include_llvm_CodeGen_SelectionDAG_h 15 Nov 2014 03:26:40 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,30 +0,0 @@
> -$OpenBSD: patch-include_llvm_CodeGen_SelectionDAG_h,v 1.1 2014/11/15 03:26:40 brad Exp $
> -
> -r221709  
> -Totally forget deallocated SDNodes in SDDbgInfo.
> -
> -What would happen before that commit is that the SDDbgValues associated with
> -a deallocated SDNode would be marked Invalidated, but SDDbgInfo would keep
> -a map entry keyed by the SDNode pointer pointing to this list of invalidated
> -SDDbgNodes. As the memory gets reused, the list might get wrongly associated
> -with another new SDNode. As the SDDbgValues are cloned when they are transfered,
> -this can lead to an exponential number of SDDbgValues being produced during
> -DAGCombine like in http://llvm.org/bugs/show_bug.cgi?id=20893
> -
> -Note that the previous behavior wasn't really buggy as the invalidation made
> -sure that the SDDbgValues won't be used. This commit can be considered a
> -memory optimization and as such is really hard to validate in a unit-test.
> -
> ---- include/llvm/CodeGen/SelectionDAG.h.orig Fri Nov 14 21:08:36 2014
> -+++ include/llvm/CodeGen/SelectionDAG.h Fri Nov 14 21:09:49 2014
> -@@ -126,6 +126,10 @@ class SDDbgInfo { (public)
> -       DbgValMap[Node].push_back(V);
> -   }
> -
> -+  /// \brief Invalidate all DbgValues attached to the node and remove
> -+  /// it from the Node-to-DbgValues map.
> -+  void erase(const SDNode *Node);
> -+
> -   void clear() {
> -     DbgValMap.clear();
> -     DbgValues.clear();
> Index: patches/patch-include_llvm_Config_config_h_cmake
> ===================================================================
> RCS file: patches/patch-include_llvm_Config_config_h_cmake
> diff -N patches/patch-include_llvm_Config_config_h_cmake
> --- patches/patch-include_llvm_Config_config_h_cmake 26 Jul 2014 09:27:29 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,16 +0,0 @@
> -$OpenBSD: patch-include_llvm_Config_config_h_cmake,v 1.1 2014/07/26 09:27:29 pascal Exp $
> -
> -r213966
> -Fix arc4random detection.
> -
> ---- include/llvm/Config/config.h.cmake.orig Wed Jul  9 15:45:23 2014
> -+++ include/llvm/Config/config.h.cmake Wed Jul  9 15:59:51 2014
> -@@ -34,7 +34,7 @@
> - #undef GCC_INSTALL_PREFIX
> -
> - /* Define to 1 if you have the `arc4random' function. */
> --#cmakedefine HAVE_ARC4RANDOM
> -+#cmakedefine HAVE_DECL_ARC4RANDOM ${HAVE_DECL_ARC4RANDOM}
> -
> - /* Define to 1 if you have the `backtrace' function. */
> - #cmakedefine HAVE_BACKTRACE ${HAVE_BACKTRACE}
> Index: patches/patch-include_llvm_Support_ELF_h
> ===================================================================
> RCS file: patches/patch-include_llvm_Support_ELF_h
> diff -N patches/patch-include_llvm_Support_ELF_h
> --- patches/patch-include_llvm_Support_ELF_h 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,19 +0,0 @@
> -$OpenBSD: patch-include_llvm_Support_ELF_h,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- include/llvm/Support/ELF.h.orig Sun Jul 27 00:01:21 2014
> -+++ include/llvm/Support/ELF.h Sun Jul 27 00:02:18 2014
> -@@ -437,6 +437,7 @@ enum {
> -   R_PPC_GOT16_LO              = 15,
> -   R_PPC_GOT16_HI              = 16,
> -   R_PPC_GOT16_HA              = 17,
> -+  R_PPC_PLTREL24              = 18,
> -   R_PPC_REL32                 = 26,
> -   R_PPC_TLS                   = 67,
> -   R_PPC_DTPMOD32              = 68,
> Index: patches/patch-include_llvm_Target_TargetInstrInfo_h
> ===================================================================
> RCS file: patches/patch-include_llvm_Target_TargetInstrInfo_h
> diff -N patches/patch-include_llvm_Target_TargetInstrInfo_h
> --- patches/patch-include_llvm_Target_TargetInstrInfo_h 18 Sep 2014 20:19:27 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,32 +0,0 @@
> -$OpenBSD: patch-include_llvm_Target_TargetInstrInfo_h,v 1.1 2014/09/18 20:19:27 brad Exp $
> -
> -r217801
> -Fix a lot of confusion around inserting nops on empty functions.
> -
> -On MachO, and MachO only, we cannot have a truly empty function since that
> -breaks the linker logic for atomizing the section.
> -
> -When we are emitting a frame pointer, the presence of an unreachable will
> -create a cfi instruction pointing past the last instruction. This is perfectly
> -fine. The FDE information encodes the pc range it applies to. If some tool
> -cannot handle this, we should explicitly say which bug we are working around
> -and only work around it when it is actually relevant (not for ELF for example).
> -
> -Given the unreachable we could omit the .cfi_def_cfa_register, but then
> -again, we could also omit the entire function prologue if we wanted to.
> -
> ---- include/llvm/Target/TargetInstrInfo.h.orig Mon Sep 15 16:00:35 2014
> -+++ include/llvm/Target/TargetInstrInfo.h Mon Sep 15 16:01:15 2014
> -@@ -661,10 +661,8 @@ class TargetInstrInfo : public MCInstrInfo { (public)
> -                           MachineBasicBlock::iterator MI) const;
> -
> -
> --  /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
> --  virtual void getNoopForMachoTarget(MCInst &NopInst) const {
> --    // Default to just using 'nop' string.
> --  }
> -+  /// Return the noop instruction to use for a noop.
> -+  virtual void getNoopForMachoTarget(MCInst &NopInst) const;
> -
> -
> -   /// isPredicated - Returns true if the instruction is already predicated.
> Index: patches/patch-lib_Analysis_IVUsers_cpp
> ===================================================================
> RCS file: patches/patch-lib_Analysis_IVUsers_cpp
> diff -N patches/patch-lib_Analysis_IVUsers_cpp
> --- patches/patch-lib_Analysis_IVUsers_cpp 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,45 +0,0 @@
> -$OpenBSD: patch-lib_Analysis_IVUsers_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r203719
> -PR17473: Don't normalize an expression during postinc transformation unless it's
> -invertible.
> -
> ---- lib/Analysis/IVUsers.cpp.orig Sun Mar  2 21:57:38 2014
> -+++ lib/Analysis/IVUsers.cpp Sat Jun 14 03:56:54 2014
> -@@ -186,15 +186,34 @@ bool IVUsers::AddUsersImpl(Instruction *I,
> -
> -     if (AddUserToIVUsers) {
> -       // Okay, we found a user that we cannot reduce.
> --      IVUses.push_back(new IVStrideUse(this, User, I));
> --      IVStrideUse &NewUse = IVUses.back();
> -+      IVStrideUse &NewUse = AddUser(User, I);
> -       // Autodetect the post-inc loop set, populating NewUse.PostIncLoops.
> -       // The regular return value here is discarded; instead of recording
> -       // it, we just recompute it when we need it.
> -+      const SCEV *OriginalISE = ISE;
> -       ISE = TransformForPostIncUse(NormalizeAutodetect,
> -                                    ISE, User, I,
> -                                    NewUse.PostIncLoops,
> -                                    *SE, *DT);
> -+
> -+      // PostIncNormalization effectively simplifies the expression under
> -+      // pre-increment assumptions. Those assumptions (no wrapping) might not
> -+      // hold for the post-inc value. Catch such cases by making sure the
> -+      // transformation is invertible.
> -+      if (OriginalISE != ISE) {
> -+        const SCEV *DenormalizedISE =
> -+          TransformForPostIncUse(Denormalize, ISE, User, I,
> -+              NewUse.PostIncLoops, *SE, *DT);
> -+
> -+        // If we normalized the expression, but denormalization doesn't give the
> -+        // original one, discard this user.
> -+        if (OriginalISE != DenormalizedISE) {
> -+          DEBUG(dbgs() << "   DISCARDING (NORMALIZATION ISN'T INVERTIBLE): "
> -+                       << *ISE << '\n');
> -+          IVUses.pop_back();
> -+          return false;
> -+        }
> -+      }
> -       DEBUG(if (SE->getSCEV(I) != ISE)
> -               dbgs() << "   NORMALIZED TO: " << *ISE << '\n');
> -     }
> Index: patches/patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp
> ===================================================================
> RCS file: patches/patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp
> diff -N patches/patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp
> --- patches/patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp 18 Sep 2014 20:19:27 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,68 +0,0 @@
> -$OpenBSD: patch-lib_CodeGen_AsmPrinter_AsmPrinter_cpp,v 1.1 2014/09/18 20:19:27 brad Exp $
> -
> -r217801
> -Fix a lot of confusion around inserting nops on empty functions.
> -
> -On MachO, and MachO only, we cannot have a truly empty function since that
> -breaks the linker logic for atomizing the section.
> -
> -When we are emitting a frame pointer, the presence of an unreachable will
> -create a cfi instruction pointing past the last instruction. This is perfectly
> -fine. The FDE information encodes the pc range it applies to. If some tool
> -cannot handle this, we should explicitly say which bug we are working around
> -and only work around it when it is actually relevant (not for ELF for example).
> -
> -Given the unreachable we could omit the .cfi_def_cfa_register, but then
> -again, we could also omit the entire function prologue if we wanted to.
> -
> -r217899
> -Add back a fallback case for targets that do not or cannot implement getNoopForMachoTarget().
> -
> ---- lib/CodeGen/AsmPrinter/AsmPrinter.cpp.orig Sun Mar  2 21:57:42 2014
> -+++ lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Sep 16 22:33:35 2014
> -@@ -739,14 +739,12 @@ void AsmPrinter::EmitFunctionBody() {
> -
> -   // Print out code for the function.
> -   bool HasAnyRealCode = false;
> --  const MachineInstr *LastMI = 0;
> -   for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
> -        I != E; ++I) {
> -     // Print a label for the basic block.
> -     EmitBasicBlockStart(I);
> -     for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
> -          II != IE; ++II) {
> --      LastMI = II;
> -
> -       // Print the assembly for the instruction.
> -       if (!II->isLabel() && !II->isImplicitDef() && !II->isKill() &&
> -@@ -807,24 +805,18 @@ void AsmPrinter::EmitFunctionBody() {
> -     }
> -   }
> -
> --  // If the last instruction was a prolog label, then we have a situation where
> --  // we emitted a prolog but no function body. This results in the ending prolog
> --  // label equaling the end of function label and an invalid "row" in the
> --  // FDE. We need to emit a noop in this situation so that the FDE's rows are
> --  // valid.
> --  bool RequiresNoop = LastMI && LastMI->isPrologLabel();
> --
> -   // If the function is empty and the object file uses .subsections_via_symbols,
> -   // then we need to emit *something* to the function body to prevent the
> -   // labels from collapsing together.  Just emit a noop.
> --  if ((MAI->hasSubsectionsViaSymbols() && !HasAnyRealCode) || RequiresNoop) {
> -+  if ((MAI->hasSubsectionsViaSymbols() && !HasAnyRealCode)) {
> -     MCInst Noop;
> -     TM.getInstrInfo()->getNoopForMachoTarget(Noop);
> --    if (Noop.getOpcode()) {
> --      OutStreamer.AddComment("avoids zero-length function");
> -+    OutStreamer.AddComment("avoids zero-length function");
> -+
> -+    // Targets can opt-out of emitting the noop here by leaving the opcode
> -+    // unspecified.
> -+    if (Noop.getOpcode())
> -       OutStreamer.EmitInstruction(Noop, getSubtargetInfo());
> --    } else  // Target not mc-ized yet.
> --      OutStreamer.EmitRawText(StringRef("\tnop\n"));
> -   }
> -
> -   const Function *F = MF->getFunction();
> Index: patches/patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h
> ===================================================================
> RCS file: patches/patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h
> diff -N patches/patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h
> --- patches/patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h 14 Aug 2014 01:08:09 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,21 +0,0 @@
> -$OpenBSD: patch-lib_CodeGen_SelectionDAG_LegalizeTypes_h,v 1.1 2014/08/14 01:08:09 brad Exp $
> -
> -r211435
> -Legalizer: Add support for splitting insert_subvectors.
> -
> -We handle this by spilling the whole thing to the stack and doing the
> -insertion as a store.
> -
> -PR19492. This happens in real code because the vectorizer creates v2i128 when AVX is
> -enabled.
> -
> ---- lib/CodeGen/SelectionDAG/LegalizeTypes.h.orig Thu Jul 17 01:03:52 2014
> -+++ lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Jul 17 01:04:56 2014
> -@@ -570,6 +570,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer { (priv
> -   void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
> -   void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
> -   void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
> -+  void SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
> -   void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
> -   void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
> -   void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
> Index: patches/patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp
> ===================================================================
> RCS file: patches/patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp
> diff -N patches/patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp
> --- patches/patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp 14 Aug 2014 01:08:09 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,92 +0,0 @@
> -$OpenBSD: patch-lib_CodeGen_SelectionDAG_LegalizeVectorTypes_cpp,v 1.2 2014/08/14 01:08:09 brad Exp $
> -
> -r211435
> -Legalizer: Add support for splitting insert_subvectors.
> -
> -We handle this by spilling the whole thing to the stack and doing the
> -insertion as a store.
> -
> -PR19492. This happens in real code because the vectorizer creates v2i128 when AVX is
> -enabled.
> -
> -r203311
> -ISel: Make VSELECT selection terminate in cases where the condition type has to
> -be split and the result type widened.
> -
> -When the condition of a vselect has to be split it makes no sense widening the
> -vselect and thereby widening the condition. We end up in an endless loop of
> -widening (vselect result type) and splitting (condition mask type) doing this.
> -Instead, split both the condition and the vselect and widen the result.
> -
> ---- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp.orig Sun Mar  2 21:57:42 2014
> -+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Jul 17 01:10:16 2014
> -@@ -518,6 +518,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, un
> -   case ISD::BUILD_VECTOR:      SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
> -   case ISD::CONCAT_VECTORS:    SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
> -   case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
> -+  case ISD::INSERT_SUBVECTOR:  SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
> -   case ISD::FP_ROUND_INREG:    SplitVecRes_InregOp(N, Lo, Hi); break;
> -   case ISD::FPOWI:             SplitVecRes_FPOWI(N, Lo, Hi); break;
> -   case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
> -@@ -737,6 +738,43 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(S
> -                                    TLI.getVectorIdxTy()));
> - }
> -
> -+void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
> -+                                                    SDValue &Hi) {
> -+  SDValue Vec = N->getOperand(0);
> -+  SDValue SubVec = N->getOperand(1);
> -+  SDValue Idx = N->getOperand(2);
> -+  SDLoc dl(N);
> -+  GetSplitVector(Vec, Lo, Hi);
> -+
> -+  // Spill the vector to the stack.
> -+  EVT VecVT = Vec.getValueType();
> -+  EVT SubVecVT = VecVT.getVectorElementType();
> -+  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
> -+  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
> -+                               MachinePointerInfo(), false, false, 0);
> -+
> -+  // Store the new subvector into the specified index.
> -+  SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
> -+  Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
> -+  unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
> -+  Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
> -+                       false, false, 0);
> -+
> -+  // Load the Lo part from the stack slot.
> -+  Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
> -+                   false, false, false, 0);
> -+
> -+  // Increment the pointer to the other part.
> -+  unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
> -+  StackPtr =
> -+      DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
> -+                  DAG.getConstant(IncrementSize, StackPtr.getValueType()));
> -+
> -+  // Load the Hi part from the stack slot.
> -+  Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
> -+                   false, false, false, MinAlign(Alignment, IncrementSize));
> -+}
> -+
> - void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
> -                                          SDValue &Hi) {
> -   SDLoc dl(N);
> -@@ -2191,6 +2229,17 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N
> -                                         CondEltVT, WidenNumElts);
> -     if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
> -       Cond1 = GetWidenedVector(Cond1);
> -+
> -+    // If we have to split the condition there is no point in widening the
> -+    // select. This would result in an cycle of widening the select ->
> -+    // widening the condition operand -> splitting the condition operand ->
> -+    // splitting the select -> widening the select. Instead split this select
> -+    // further and widen the resulting type.
> -+    if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
> -+      SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
> -+      SDValue Res = ModifyToType(SplitSelect, WidenVT);
> -+      return Res;
> -+    }
> -
> -     if (Cond1.getValueType() != CondWidenVT)
> -       Cond1 = ModifyToType(Cond1, CondWidenVT);
> Index: patches/patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp
> ===================================================================
> RCS file: patches/patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp
> diff -N patches/patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp
> --- patches/patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,43 +0,0 @@
> -$OpenBSD: patch-lib_CodeGen_SelectionDAG_ScheduleDAGSDNodes_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r205738
> -Put a limit on ScheduleDAGSDNodes::ClusterNeighboringLoads to avoid blowing up compile time.
> -
> -Fixes PR16365 - Extremely slow compilation in -O1 and -O2.
> -
> -The SD scheduler has a quadratic implementation of load clustering
> -which absolutely blows up compile time for large blocks with constant
> -pool loads. The MI scheduler has a better implementation of load
> -clustering. However, we have not done the work yet to completely
> -eliminate the SD scheduler. Some benchmarks still seem to benefit from
> -early load clustering, although maybe by chance.
> -
> -As an intermediate term fix, I just put a nice limit on the number of
> -DAG users to search before finding a match. With this limit there are no
> -binary differences in the LLVM test suite, and the PR16365 test case
> -does not suffer any compile time impact from this routine.
> -
> ---- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp.orig Sun Mar  2 21:57:42 2014
> -+++ lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Sat Jun 14 04:01:39 2014
> -@@ -219,8 +219,11 @@ void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNod
> -   DenseMap<long long, SDNode*> O2SMap;  // Map from offset to SDNode.
> -   bool Cluster = false;
> -   SDNode *Base = Node;
> -+  // This algorithm requires a reasonably low use count before finding a match
> -+  // to avoid uselessly blowing up compile time in large blocks.
> -+  unsigned UseCount = 0;
> -   for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
> --       I != E; ++I) {
> -+       I != E && UseCount < 100; ++I, ++UseCount) {
> -     SDNode *User = *I;
> -     if (User == Node || !Visited.insert(User))
> -       continue;
> -@@ -237,6 +240,8 @@ void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNod
> -     if (Offset2 < Offset1)
> -       Base = User;
> -     Cluster = true;
> -+    // Reset UseCount to allow more matches.
> -+    UseCount = 0;
> -   }
> -
> -   if (!Cluster)
> Index: patches/patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp
> ===================================================================
> RCS file: patches/patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp
> diff -N patches/patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp
> --- patches/patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp 24 Aug 2015 07:45:56 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,107 +0,0 @@
> -$OpenBSD: patch-lib_CodeGen_SelectionDAG_SelectionDAGISel_cpp,v 1.1 2015/08/24 07:45:56 ajacoutot Exp $
> -
> -r219009
> -[ISel] Keep matching state consistent when folding during X86 address match
> -
> -In the X86 backend, matching an address is initiated by the 'addr' complex
> -pattern and its friends.  During this process we may reassociate and-of-shift
> -into shift-of-and (FoldMaskedShiftToScaledMask) to allow folding of the
> -shift into the scale of the address.
> -
> -However as demonstrated by the testcase, this can trigger CSE of not only the
> -shift and the AND which the code is prepared for but also the underlying load
> -node.  In the testcase this node is sitting in the RecordedNode and MatchScope
> -data structures of the matcher and becomes a deleted node upon CSE.  Returning
> -from the complex pattern function, we try to access it again hitting an assert
> -because the node is no longer a load even though this was checked before.
> -
> -Now obviously changing the DAG this late is bending the rules but I think it
> -makes sense somewhat.  Outside of addresses we prefer and-of-shift because it
> -may lead to smaller immediates (FoldMaskAndShiftToScale is an even better
> -example because it create a non-canonical node).  We currently don't recognize
> -addresses during DAGCombiner where arguably this canonicalization should be
> -performed.  On the other hand, having this in the matcher allows us to cover
> -all the cases where an address can be used in an instruction.
> -
> -I've also talked a little bit to Dan Gohman on llvm-dev who added the RAUW for
> -the new shift node in FoldMaskedShiftToScaledMask.  This RAUW is responsible
> -for initiating the recursive CSE on users
> -(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-September/076903.html) but it
> -is not strictly necessary since the shift is hooked into the visited user.  Of
> -course it's safer to keep the DAG consistent at all times (e.g. for accurate
> -number of uses, etc.).
> -
> -So rather than changing the fundamentals, I've decided to continue along the
> -previous patches and detect the CSE.  This patch installs a very targeted
> -DAGUpdateListener for the duration of a complex-pattern match and updates the
> -matching state accordingly.  (Previous patches used HandleSDNode to detect the
> -CSE but that's not practical here).  The listener is only installed on X86.
> -
> -I tested that there is no measurable overhead due to this while running
> -through the spec2k BC files with llc.  The only thing we pay for is the
> -creation of the listener.  The callback never ever triggers in spec2k since
> -this is a corner case.
> -
> ---- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp.orig Tue Aug  4 22:47:10 2015
> -+++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug  4 22:52:46 2015
> -@@ -2363,6 +2363,45 @@ struct MatchScope {
> -   bool HasChainNodesMatched, HasGlueResultNodesMatched;
> - };
> -
> -+/// \\brief A DAG update listener to keep the matching state
> -+/// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
> -+/// change the DAG while matching.  X86 addressing mode matcher is an example
> -+/// for this.
> -+class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
> -+{
> -+      SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
> -+      SmallVectorImpl<MatchScope> &MatchScopes;
> -+public:
> -+  MatchStateUpdater(SelectionDAG &DAG,
> -+                    SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
> -+                    SmallVectorImpl<MatchScope> &MS) :
> -+    SelectionDAG::DAGUpdateListener(DAG),
> -+    RecordedNodes(RN), MatchScopes(MS) { }
> -+
> -+  void NodeDeleted(SDNode *N, SDNode *E) {
> -+    // Some early-returns here to avoid the search if we deleted the node or
> -+    // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
> -+    // do, so it's unnecessary to update matching state at that point).
> -+    // Neither of these can occur currently because we only install this
> -+    // update listener during matching a complex patterns.
> -+    if (!E || E->isMachineOpcode())
> -+      return;
> -+    // Performing linear search here does not matter because we almost never
> -+    // run this code.  You'd have to have a CSE during complex pattern
> -+    // matching.
> -+    for (SmallVectorImpl<std::pair<SDValue, SDNode*> >::iterator I =
> -+         RecordedNodes.begin(), IE = RecordedNodes.end(); I != IE; ++I)
> -+      if (I->first.getNode() == N)
> -+        I->first.setNode(E);
> -+
> -+    for (SmallVectorImpl<MatchScope>::iterator I = MatchScopes.begin(),
> -+         IE = MatchScopes.end(); I != IE; ++I)
> -+      for (SmallVector<SDValue, 4>::iterator J = I->NodeStack.begin(),
> -+           JE = I->NodeStack.end(); J != JE; ++J)
> -+        if (J->getNode() == N)
> -+          J->setNode(E);
> -+  }
> -+};
> - }
> -
> - SDNode *SelectionDAGISel::
> -@@ -2617,6 +2656,14 @@ SelectCodeCommon(SDNode *NodeToMatch, const unsigned c
> -       unsigned CPNum = MatcherTable[MatcherIndex++];
> -       unsigned RecNo = MatcherTable[MatcherIndex++];
> -       assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
> -+
> -+      // If target can modify DAG during matching, keep the matching state
> -+      // consistent.
> -+      OwningPtr<MatchStateUpdater> MSU;
> -+      if (ComplexPatternFuncMutatesDAG())
> -+        MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
> -+                                        MatchScopes));
> -+
> -       if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
> -                                RecordedNodes[RecNo].first, CPNum,
> -                                RecordedNodes))
> Index: patches/patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp
> ===================================================================
> RCS file: patches/patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp
> diff -N patches/patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp
> --- patches/patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp 15 Nov 2014 03:26:40 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,49 +0,0 @@
> -$OpenBSD: patch-lib_CodeGen_SelectionDAG_SelectionDAG_cpp,v 1.1 2014/11/15 03:26:40 brad Exp $
> -
> -r221709
> -Totally forget deallocated SDNodes in SDDbgInfo.
> -
> -What would happen before that commit is that the SDDbgValues associated with
> -a deallocated SDNode would be marked Invalidated, but SDDbgInfo would keep
> -a map entry keyed by the SDNode pointer pointing to this list of invalidated
> -SDDbgNodes. As the memory gets reused, the list might get wrongly associated
> -with another new SDNode. As the SDDbgValues are cloned when they are transfered,
> -this can lead to an exponential number of SDDbgValues being produced during
> -DAGCombine like in http://llvm.org/bugs/show_bug.cgi?id=20893
> -
> -Note that the previous behavior wasn't really buggy as the invalidation made
> -sure that the SDDbgValues won't be used. This commit can be considered a
> -memory optimization and as such is really hard to validate in a unit-test.
> -
> ---- lib/CodeGen/SelectionDAG/SelectionDAG.cpp.orig Fri Nov 14 21:02:43 2014
> -+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Nov 14 21:08:05 2014
> -@@ -642,6 +642,15 @@ void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) {
> -   DeallocateNode(N);
> - }
> -
> -+void SDDbgInfo::erase(const SDNode *Node) {
> -+  DbgValMapType::iterator I = DbgValMap.find(Node);
> -+  if (I == DbgValMap.end())
> -+    return;
> -+  for (unsigned J = 0, N = I->second.size(); J != N; ++J)
> -+    I->second[J]->setIsInvalidated();
> -+  DbgValMap.erase(I);
> -+}
> -+
> - void SelectionDAG::DeallocateNode(SDNode *N) {
> -   if (N->OperandsNeedDelete)
> -     delete[] N->OperandList;
> -@@ -652,10 +661,9 @@ void SelectionDAG::DeallocateNode(SDNode *N) {
> -
> -   NodeAllocator.Deallocate(AllNodes.remove(N));
> -
> --  // If any of the SDDbgValue nodes refer to this SDNode, invalidate them.
> --  ArrayRef<SDDbgValue*> DbgVals = DbgInfo->getSDDbgValues(N);
> --  for (unsigned i = 0, e = DbgVals.size(); i != e; ++i)
> --    DbgVals[i]->setIsInvalidated();
> -+  // If any of the SDDbgValue nodes refer to this SDNode, invalidate
> -+  // them and forget about that node.
> -+  DbgInfo->erase(N);
> - }
> -
> - /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
> Index: patches/patch-lib_CodeGen_StackProtector_cpp
> ===================================================================
> RCS file: patches/patch-lib_CodeGen_StackProtector_cpp
> diff -N patches/patch-lib_CodeGen_StackProtector_cpp
> --- patches/patch-lib_CodeGen_StackProtector_cpp 17 May 2014 11:41:15 -0000 1.5
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,25 +0,0 @@
> -$OpenBSD: patch-lib_CodeGen_StackProtector_cpp,v 1.5 2014/05/17 11:41:15 brad Exp $
> -
> -r206486
> -Make the StackProtector pass respect ssp-buffer-size.
> -
> ---- lib/CodeGen/StackProtector.cpp.orig Fri Apr 18 17:19:15 2014
> -+++ lib/CodeGen/StackProtector.cpp Fri Apr 18 17:20:13 2014
> -@@ -86,14 +86,14 @@ bool StackProtector::runOnFunction(Function &Fn) {
> -   DT = DTWP ? &DTWP->getDomTree() : 0;
> -   TLI = TM->getTargetLowering();
> -
> --  if (!RequiresStackProtector())
> --    return false;
> --
> -   Attribute Attr = Fn.getAttributes().getAttribute(
> -       AttributeSet::FunctionIndex, "stack-protector-buffer-size");
> -   if (Attr.isStringAttribute() &&
> -       Attr.getValueAsString().getAsInteger(10, SSPBufferSize))
> -       return false; // Invalid integer string
> -+
> -+  if (!RequiresStackProtector())
> -+    return false;
> -
> -   ++NumFunProtected;
> -   return InsertStackProtectors();
> Index: patches/patch-lib_CodeGen_TargetInstrInfo_cpp
> ===================================================================
> RCS file: patches/patch-lib_CodeGen_TargetInstrInfo_cpp
> diff -N patches/patch-lib_CodeGen_TargetInstrInfo_cpp
> --- patches/patch-lib_CodeGen_TargetInstrInfo_cpp 18 Sep 2014 20:19:27 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,30 +0,0 @@
> -$OpenBSD: patch-lib_CodeGen_TargetInstrInfo_cpp,v 1.1 2014/09/18 20:19:27 brad Exp $
> -
> -r217801
> -Fix a lot of confusion around inserting nops on empty functions.
> -
> -On MachO, and MachO only, we cannot have a truly empty function since that
> -breaks the linker logic for atomizing the section.
> -
> -When we are emitting a frame pointer, the presence of an unreachable will
> -create a cfi instruction pointing past the last instruction. This is perfectly
> -fine. The FDE information encodes the pc range it applies to. If some tool
> -cannot handle this, we should explicitly say which bug we are working around
> -and only work around it when it is actually relevant (not for ELF for example).
> -
> -Given the unreachable we could omit the .cfi_def_cfa_register, but then
> -again, we could also omit the entire function prologue if we wanted to.
> -
> ---- lib/CodeGen/TargetInstrInfo.cpp.orig Mon Sep 15 16:04:07 2014
> -+++ lib/CodeGen/TargetInstrInfo.cpp Mon Sep 15 16:04:33 2014
> -@@ -368,6 +368,10 @@ static const TargetRegisterClass *canFoldCopy(const Ma
> -   return 0;
> - }
> -
> -+void TargetInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
> -+  llvm_unreachable("Not a MachO target");
> -+}
> -+
> - bool TargetInstrInfo::
> - canFoldMemoryOperand(const MachineInstr *MI,
> -                      const SmallVectorImpl<unsigned> &Ops) const {
> Index: patches/patch-lib_MC_MCObjectFileInfo_cpp
> ===================================================================
> RCS file: patches/patch-lib_MC_MCObjectFileInfo_cpp
> diff -N patches/patch-lib_MC_MCObjectFileInfo_cpp
> --- patches/patch-lib_MC_MCObjectFileInfo_cpp 30 Dec 2014 05:23:32 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,16 +0,0 @@
> -$OpenBSD: patch-lib_MC_MCObjectFileInfo_cpp,v 1.1 2014/12/30 05:23:32 brad Exp $
> -
> -r213890
> -Use the same .eh_frame encoding for 32bit PPC as on i386.
> -
> ---- lib/MC/MCObjectFileInfo.cpp.orig Tue Dec 30 00:10:03 2014
> -+++ lib/MC/MCObjectFileInfo.cpp Tue Dec 30 00:19:28 2014
> -@@ -248,7 +248,7 @@ void MCObjectFileInfo::InitELFMCObjectFileInfo(Triple
> -   else
> -     FDECFIEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
> -
> --  if (T.getArch() == Triple::x86) {
> -+  if (T.getArch() == Triple::ppc || T.getArch() == Triple::x86) {
> -     PersonalityEncoding = (RelocM == Reloc::PIC_)
> -      ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
> -      : dwarf::DW_EH_PE_absptr;
> Index: patches/patch-lib_MC_MCParser_AsmParser_cpp
> ===================================================================
> RCS file: patches/patch-lib_MC_MCParser_AsmParser_cpp
> diff -N patches/patch-lib_MC_MCParser_AsmParser_cpp
> --- patches/patch-lib_MC_MCParser_AsmParser_cpp 4 Jun 2015 05:58:43 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,44 +0,0 @@
> -$OpenBSD: patch-lib_MC_MCParser_AsmParser_cpp,v 1.1 2015/06/04 05:58:43 ajacoutot Exp $
> -
> -r229911
> -MC: Allow multiple comma-separated expressions on the .uleb128 directive.
> -
> ---- lib/MC/MCParser/AsmParser.cpp.orig Thu Jun  4 00:34:57 2015
> -+++ lib/MC/MCParser/AsmParser.cpp Thu Jun  4 00:40:09 2015
> -@@ -3574,21 +3574,27 @@ bool AsmParser::parseDirectiveSpace(StringRef IDVal) {
> - }
> -
> - /// parseDirectiveLEB128
> --/// ::= (.sleb128 | .uleb128) expression
> -+/// ::= (.sleb128 | .uleb128) [ expression (, expression)* ]
> - bool AsmParser::parseDirectiveLEB128(bool Signed) {
> -   checkForValidSection();
> -   const MCExpr *Value;
> -
> --  if (parseExpression(Value))
> --    return true;
> -+  for (;;) {
> -+    if (parseExpression(Value))
> -+      return true;
> -
> --  if (getLexer().isNot(AsmToken::EndOfStatement))
> --    return TokError("unexpected token in directive");
> -+    if (Signed)
> -+      getStreamer().EmitSLEB128Value(Value);
> -+    else
> -+      getStreamer().EmitULEB128Value(Value);
> -
> --  if (Signed)
> --    getStreamer().EmitSLEB128Value(Value);
> --  else
> --    getStreamer().EmitULEB128Value(Value);
> -+    if (getLexer().is(AsmToken::EndOfStatement))
> -+      break;
> -+
> -+    if (getLexer().isNot(AsmToken::Comma))
> -+      return TokError("unexpected token in directive");
> -+    Lex();
> -+  }
> -
> -   return false;
> - }
> Index: patches/patch-lib_Object_ELF_cpp
> ===================================================================
> RCS file: patches/patch-lib_Object_ELF_cpp
> diff -N patches/patch-lib_Object_ELF_cpp
> --- patches/patch-lib_Object_ELF_cpp 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,19 +0,0 @@
> -$OpenBSD: patch-lib_Object_ELF_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- lib/Object/ELF.cpp.orig Sun Jul 27 00:02:32 2014
> -+++ lib/Object/ELF.cpp Sun Jul 27 00:02:56 2014
> -@@ -509,6 +509,7 @@ StringRef getELFRelocationTypeName(uint32_t Machine, u
> -       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_LO);
> -       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_HI);
> -       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_HA);
> -+      LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_PLTREL24);
> -       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL32);
> -       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_TLS);
> -       LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_DTPMOD32);
> Index: patches/patch-lib_Support_regcomp_c
> ===================================================================
> RCS file: patches/patch-lib_Support_regcomp_c
> diff -N patches/patch-lib_Support_regcomp_c
> --- patches/patch-lib_Support_regcomp_c 11 Feb 2015 00:29:05 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,57 +0,0 @@
> -$OpenBSD: patch-lib_Support_regcomp_c,v 1.1 2015/02/11 00:29:05 brad Exp $
> -
> -r228507
> -Avoid integer overflows around realloc calls resulting in potential
> -heap. Problem identified by Guido Vranken.
> -
> ---- lib/Support/regcomp.c.orig Mon Feb  9 17:08:17 2015
> -+++ lib/Support/regcomp.c Mon Feb  9 17:10:41 2015
> -@@ -49,6 +49,14 @@
> - #include "regcclass.h"
> - #include "regcname.h"
> -
> -+#include "llvm/Config/config.h"
> -+#if HAVE_STDINT_H
> -+#include <stdint.h>
> -+#else
> -+/* Pessimistically bound memory use */
> -+#define SIZE_MAX UINT_MAX
> -+#endif
> -+
> - /*
> -  * parse structure, passed up and down to avoid global variables and
> -  * other clumsinesses
> -@@ -1069,6 +1077,8 @@ allocset(struct parse *p)
> -
> - p->ncsalloc += CHAR_BIT;
> - nc = p->ncsalloc;
> -+ if (nc > SIZE_MAX / sizeof(cset))
> -+ goto nomem;
> - assert(nc % CHAR_BIT == 0);
> - nbytes = nc / CHAR_BIT * css;
> -
> -@@ -1412,6 +1422,11 @@ enlarge(struct parse *p, sopno size)
> - if (p->ssize >= size)
> - return;
> -
> -+ if ((unsigned long)size > SIZE_MAX / sizeof(sop)) {
> -+ SETERROR(REG_ESPACE);
> -+ return;
> -+ }
> -+
> - sp = (sop *)realloc(p->strip, size*sizeof(sop));
> - if (sp == NULL) {
> - SETERROR(REG_ESPACE);
> -@@ -1428,6 +1443,12 @@ static void
> - stripsnug(struct parse *p, struct re_guts *g)
> - {
> - g->nstates = p->slen;
> -+ if ((unsigned long)p->slen > SIZE_MAX / sizeof(sop)) {
> -+ g->strip = p->strip;
> -+ SETERROR(REG_ESPACE);
> -+ return;
> -+ }
> -+
> - g->strip = (sop *)realloc((char *)p->strip, p->slen * sizeof(sop));
> - if (g->strip == NULL) {
> - SETERROR(REG_ESPACE);
> Index: patches/patch-lib_Target_ARM_A15SDOptimizer_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_ARM_A15SDOptimizer_cpp
> diff -N patches/patch-lib_Target_ARM_A15SDOptimizer_cpp
> --- patches/patch-lib_Target_ARM_A15SDOptimizer_cpp 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,40 +0,0 @@
> -$OpenBSD: patch-lib_Target_ARM_A15SDOptimizer_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r204304
> -Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR.
> -
> ---- lib/Target/ARM/A15SDOptimizer.cpp.orig Sun Mar  2 21:57:40 2014
> -+++ lib/Target/ARM/A15SDOptimizer.cpp Sat Jun 14 04:09:54 2014
> -@@ -416,7 +416,8 @@ SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(M
> -     if (!MO.isReg() || !MO.isUse())
> -       continue;
> -     if (!usesRegClass(MO, &ARM::DPRRegClass) &&
> --        !usesRegClass(MO, &ARM::QPRRegClass))
> -+        !usesRegClass(MO, &ARM::QPRRegClass) &&
> -+        !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
> -       continue;
> -
> -     Defs.push_back(MO.getReg());
> -@@ -536,7 +537,10 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *
> -   InsertPt++;
> -   unsigned Out;
> -
> --  if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) {
> -+  // DPair has the same length as QPR and also has two DPRs as subreg.
> -+  // Treat DPair as QPR.
> -+  if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
> -+      MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
> -     unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
> -                                          ARM::dsub_0, &ARM::DPRRegClass);
> -     unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
> -@@ -569,7 +573,9 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *
> -       default: llvm_unreachable("Unknown preferred lane!");
> -     }
> -
> --    bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass);
> -+    // Treat DPair as QPR
> -+    bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
> -+                   usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
> -
> -     Out = createImplicitDef(MBB, InsertPt, DL);
> -     Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
> Index: patches/patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp
> diff -N patches/patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp
> --- patches/patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp 28 Dec 2014 00:30:17 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,16 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_AsmParser_PPCAsmParser_cpp,v 1.1 2014/12/28 00:30:17 brad Exp $
> -
> -r203699
> -Allow exclamation and tilde to be parsed as a part of the ppc asm operand.
> -
> ---- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp.orig Fri Dec 26 14:50:10 2014
> -+++ lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Fri Dec 26 14:50:56 2014
> -@@ -1205,6 +1205,8 @@ ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
> -   case AsmToken::Integer:
> -   case AsmToken::Dot:
> -   case AsmToken::Dollar:
> -+  case AsmToken::Exclaim:
> -+  case AsmToken::Tilde:
> -     if (!ParseExpression(EVal))
> -       break;
> -     /* fall through */
> Index: patches/patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp
> diff -N patches/patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp
> --- patches/patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,33 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_InstPrinter_PPCInstPrinter_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213960
> -[PowerPC] Support TLS on PPC32/ELF
> -
> ---- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp.orig Sun Jul 27 03:53:55 2014
> -+++ lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Sun Jul 27 03:56:03 2014
> -@@ -18,6 +18,7 @@
> - #include "llvm/MC/MCExpr.h"
> - #include "llvm/MC/MCInst.h"
> - #include "llvm/MC/MCInstrInfo.h"
> -+#include "llvm/MC/MCSymbol.h"
> - #include "llvm/Support/CommandLine.h"
> - #include "llvm/Support/raw_ostream.h"
> - #include "llvm/Target/TargetOpcodes.h"
> -@@ -300,10 +301,16 @@ void PPCInstPrinter::printMemRegReg(const MCInst *MI,
> -
> - void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
> -                                   raw_ostream &O) {
> --  printBranchOperand(MI, OpNo, O);
> -+  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
> -+  // come at the _end_ of the expression.
> -+  const MCOperand &Op = MI->getOperand(OpNo);
> -+  const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
> -+  O << refExp.getSymbol().getName();
> -   O << '(';
> -   printOperand(MI, OpNo+1, O);
> -   O << ')';
> -+  if (refExp.getKind() != MCSymbolRefExpr::VK_None)
> -+    O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
> - }
> -
> -
> Index: patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp
> diff -N patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp
> --- patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,81 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_MCTargetDesc_PPCELFObjectWriter_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> -r213960
> -[PowerPC] Support TLS on PPC32/ELF
> -
> ---- lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Sun Jul 27 04:00:37 2014
> -@@ -64,7 +64,15 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const M
> -       llvm_unreachable("Unimplemented");
> -     case PPC::fixup_ppc_br24:
> -     case PPC::fixup_ppc_br24abs:
> --      Type = ELF::R_PPC_REL24;
> -+      switch (Modifier) {
> -+      default: llvm_unreachable("Unsupported Modifier");
> -+      case MCSymbolRefExpr::VK_None:
> -+        Type = ELF::R_PPC_REL24;
> -+        break;
> -+      case MCSymbolRefExpr::VK_PLT:
> -+        Type = ELF::R_PPC_PLTREL24;
> -+        break;
> -+      }
> -       break;
> -     case PPC::fixup_ppc_brcond14:
> -     case PPC::fixup_ppc_brcond14abs:
> -@@ -205,7 +213,10 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const M
> -         Type = ELF::R_PPC64_DTPREL16_HIGHESTA;
> -         break;
> -       case MCSymbolRefExpr::VK_PPC_GOT_TLSGD:
> --        Type = ELF::R_PPC64_GOT_TLSGD16;
> -+        if (is64Bit())
> -+          Type = ELF::R_PPC64_GOT_TLSGD16;
> -+        else
> -+          Type = ELF::R_PPC_GOT_TLSGD16;
> -         break;
> -       case MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO:
> -         Type = ELF::R_PPC64_GOT_TLSGD16_LO;
> -@@ -217,7 +228,10 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const M
> -         Type = ELF::R_PPC64_GOT_TLSGD16_HA;
> -         break;
> -       case MCSymbolRefExpr::VK_PPC_GOT_TLSLD:
> --        Type = ELF::R_PPC64_GOT_TLSLD16;
> -+        if (is64Bit())
> -+          Type = ELF::R_PPC64_GOT_TLSLD16;
> -+        else
> -+          Type = ELF::R_PPC_GOT_TLSLD16;
> -         break;
> -       case MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO:
> -         Type = ELF::R_PPC64_GOT_TLSLD16_LO;
> -@@ -313,13 +327,22 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const M
> -       switch (Modifier) {
> -       default: llvm_unreachable("Unsupported Modifier");
> -       case MCSymbolRefExpr::VK_PPC_TLSGD:
> --        Type = ELF::R_PPC64_TLSGD;
> -+        if (is64Bit())
> -+          Type = ELF::R_PPC64_TLSGD;
> -+        else
> -+          Type = ELF::R_PPC_TLSGD;
> -         break;
> -       case MCSymbolRefExpr::VK_PPC_TLSLD:
> --        Type = ELF::R_PPC64_TLSLD;
> -+        if (is64Bit())
> -+          Type = ELF::R_PPC64_TLSLD;
> -+        else
> -+          Type = ELF::R_PPC_TLSLD;
> -         break;
> -       case MCSymbolRefExpr::VK_PPC_TLS:
> --        Type = ELF::R_PPC64_TLS;
> -+        if (is64Bit())
> -+          Type = ELF::R_PPC64_TLS;
> -+        else
> -+          Type = ELF::R_PPC_TLS;
> -         break;
> -       }
> -       break;
> Index: patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp
> diff -N patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp
> --- patches/patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp 11 Feb 2015 00:29:05 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,17 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_MCTargetDesc_PPCMCAsmInfo_cpp,v 1.2 2015/02/11 00:29:05 brad Exp $
> -
> -r225819
> -Use the integrated assembler as default on PowerPC
> -
> ---- lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp Mon Feb  2 11:12:15 2015
> -@@ -74,8 +74,6 @@ PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit, con
> -   Data64bitsDirective = is64Bit ? "\t.quad\t" : 0;
> -   AssemblerDialect = 1;           // New-Style mnemonics.
> -
> --  if (T.getOS() == llvm::Triple::FreeBSD ||
> --      (T.getOS() == llvm::Triple::NetBSD && !is64Bit))
> --    UseIntegratedAssembler = true;
> -+  UseIntegratedAssembler = true;
> - }
> -
> Index: patches/patch-lib_Target_PowerPC_PPCAsmPrinter_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCAsmPrinter_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCAsmPrinter_cpp
> --- patches/patch-lib_Target_PowerPC_PPCAsmPrinter_cpp 28 Dec 2014 00:30:18 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,487 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCAsmPrinter_cpp,v 1.2 2014/12/28 00:30:18 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> -r213960
> -[PowerPC] Support TLS on PPC32/ELF
> -
> -r209821
> -[PPC] Use alias symbols in address computation.
> -
> -This seems to match what gcc does for ppc and what every other llvm
> -backend does.
> -
> ---- lib/Target/PowerPC/PPCAsmPrinter.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Dec 26 15:31:43 2014
> -@@ -19,6 +19,7 @@
> - #define DEBUG_TYPE "asmprinter"
> - #include "PPC.h"
> - #include "InstPrinter/PPCInstPrinter.h"
> -+#include "PPCMachineFunctionInfo.h"
> - #include "MCTargetDesc/PPCMCExpr.h"
> - #include "MCTargetDesc/PPCPredicates.h"
> - #include "PPCSubtarget.h"
> -@@ -28,6 +29,7 @@
> - #include "llvm/ADT/SmallString.h"
> - #include "llvm/ADT/StringExtras.h"
> - #include "llvm/CodeGen/AsmPrinter.h"
> -+#include "llvm/CodeGen/MachineConstantPool.h"
> - #include "llvm/CodeGen/MachineFunctionPass.h"
> - #include "llvm/CodeGen/MachineInstr.h"
> - #include "llvm/CodeGen/MachineInstrBuilder.h"
> -@@ -99,6 +101,7 @@ namespace {
> -     }
> -
> -     bool doFinalization(Module &M);
> -+    void EmitStartOfAsmFile(Module &M);
> -
> -     virtual void EmitFunctionEntryLabel();
> -
> -@@ -326,6 +329,66 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
> -     OutStreamer.EmitLabel(PICBase);
> -     return;
> -   }
> -+  case PPC::GetGBRO: {
> -+    // Get the offset from the GOT Base Register to the GOT
> -+    LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
> -+    MCSymbol *PICOffset = MF->getInfo<PPCFunctionInfo>()->getPICOffsetSymbol();
> -+    TmpInst.setOpcode(PPC::LWZ);
> -+    const MCExpr *Exp =
> -+      MCSymbolRefExpr::Create(PICOffset, MCSymbolRefExpr::VK_None, OutContext);
> -+    const MCExpr *PB =
> -+      MCSymbolRefExpr::Create(MF->getPICBaseSymbol(),
> -+                              MCSymbolRefExpr::VK_None,
> -+                              OutContext);
> -+    const MCOperand MO = TmpInst.getOperand(1);
> -+    TmpInst.getOperand(1) = MCOperand::CreateExpr(MCBinaryExpr::CreateSub(Exp,
> -+                                                                          PB,
> -+                                                                          OutContext));
> -+    TmpInst.addOperand(MO);
> -+    EmitToStreamer(OutStreamer, TmpInst);
> -+    return;
> -+  }
> -+  case PPC::UpdateGBR: {
> -+    // Update the GOT Base Register to point to the GOT. It may be possible to
> -+    // merge this with the PPC::GetGBRO, doing it all in one step.
> -+    LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
> -+    TmpInst.setOpcode(PPC::ADD4);
> -+    TmpInst.addOperand(TmpInst.getOperand(0));
> -+    EmitToStreamer(OutStreamer, TmpInst);
> -+    return;
> -+  }
> -+  case PPC::LWZtoc: {
> -+    // Transform %X3 = LWZtoc <ga:@min1>, %X2
> -+    LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
> -+
> -+    // Change the opcode to LWZ, and the global address operand to be a
> -+    // reference to the GOT entry we will synthesize later.
> -+    TmpInst.setOpcode(PPC::LWZ);
> -+    const MachineOperand &MO = MI->getOperand(1);
> -+
> -+    // Map symbol -> label of TOC entry
> -+    assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
> -+    MCSymbol *MOSymbol = 0;
> -+    if (MO.isGlobal())
> -+      MOSymbol = getSymbol(MO.getGlobal());
> -+    else if (MO.isCPI())
> -+      MOSymbol = GetCPISymbol(MO.getIndex());
> -+    else if (MO.isJTI())
> -+      MOSymbol = GetJTISymbol(MO.getIndex());
> -+
> -+    MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol);
> -+
> -+    const MCExpr *Exp =
> -+      MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_None,
> -+                              OutContext);
> -+    const MCExpr *PB =
> -+      MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")),
> -+                                                           OutContext);
> -+    Exp = MCBinaryExpr::CreateSub(Exp, PB, OutContext);
> -+    TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
> -+    EmitToStreamer(OutStreamer, TmpInst);
> -+    return;
> -+  }
> -   case PPC::LDtocJTI:
> -   case PPC::LDtocCPT:
> -   case PPC::LDtoc: {
> -@@ -376,16 +439,12 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
> -     bool IsAvailExt = false;
> -
> -     if (MO.isGlobal()) {
> --      const GlobalValue *GValue = MO.getGlobal();
> --      const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
> --      const GlobalValue *RealGValue = GAlias ?
> --        GAlias->resolveAliasedGlobal(false) : GValue;
> --      MOSymbol = getSymbol(RealGValue);
> --      const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
> --      IsExternal = GVar && !GVar->hasInitializer();
> --      IsCommon = GVar && RealGValue->hasCommonLinkage();
> --      IsFunction = !GVar;
> --      IsAvailExt = GVar && RealGValue->hasAvailableExternallyLinkage();
> -+      const GlobalValue *GV = MO.getGlobal();
> -+      MOSymbol = getSymbol(GV);
> -+      IsExternal = GV->isDeclaration();
> -+      IsCommon = GV->hasCommonLinkage();
> -+      IsFunction = GV->getType()->getElementType()->isFunctionTy();
> -+      IsAvailExt = GV->hasAvailableExternallyLinkage();
> -     } else if (MO.isCPI())
> -       MOSymbol = GetCPISymbol(MO.getIndex());
> -     else if (MO.isJTI())
> -@@ -424,14 +483,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
> -     }
> -     else if (MO.isGlobal()) {
> -       const GlobalValue *GValue = MO.getGlobal();
> --      const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
> --      const GlobalValue *RealGValue = GAlias ?
> --        GAlias->resolveAliasedGlobal(false) : GValue;
> --      MOSymbol = getSymbol(RealGValue);
> --      const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
> --    
> --      if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() ||
> --          RealGValue->hasAvailableExternallyLinkage() ||
> -+      MOSymbol = getSymbol(GValue);
> -+      if (GValue->getType()->getElementType()->isFunctionTy() ||
> -+          GValue->isDeclaration() || GValue->hasCommonLinkage() ||
> -+          GValue->hasAvailableExternallyLinkage() ||
> -           TM.getCodeModel() == CodeModel::Large)
> -         MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
> -     }
> -@@ -458,14 +513,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
> -     bool IsFunction = false;
> -
> -     if (MO.isGlobal()) {
> --      const GlobalValue *GValue = MO.getGlobal();
> --      const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
> --      const GlobalValue *RealGValue = GAlias ?
> --        GAlias->resolveAliasedGlobal(false) : GValue;
> --      MOSymbol = getSymbol(RealGValue);
> --      const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
> --      IsExternal = GVar && !GVar->hasInitializer();
> --      IsFunction = !GVar;
> -+      const GlobalValue *GV = MO.getGlobal();
> -+      MOSymbol = getSymbol(GV);
> -+      IsExternal = GV->isDeclaration();
> -+      IsFunction = GV->getType()->getElementType()->isFunctionTy();
> -     } else if (MO.isCPI())
> -       MOSymbol = GetCPISymbol(MO.getIndex());
> -
> -@@ -513,6 +564,34 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
> -     return;
> -   }
> -
> -+  case PPC::PPC32PICGOT: {
> -+    MCSymbol *GOTSymbol = OutContext.GetOrCreateSymbol(StringRef("_GLOBAL_OFFSET_TABLE_"));
> -+    MCSymbol *GOTRef = OutContext.CreateTempSymbol();
> -+    MCSymbol *NextInstr = OutContext.CreateTempSymbol();
> -+
> -+    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL)
> -+      // FIXME: We would like an efficient form for this, so we don't have to do
> -+      // a lot of extra uniquing.
> -+      .addExpr(MCSymbolRefExpr::Create(NextInstr, OutContext)));
> -+    const MCExpr *OffsExpr =
> -+      MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(GOTSymbol, OutContext),
> -+                                MCSymbolRefExpr::Create(GOTRef, OutContext),
> -+        OutContext);
> -+    OutStreamer.EmitLabel(GOTRef);
> -+    OutStreamer.EmitValue(OffsExpr, 4);
> -+    OutStreamer.EmitLabel(NextInstr);
> -+    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MFLR)
> -+                                .addReg(MI->getOperand(0).getReg()));
> -+    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::LWZ)
> -+                                .addReg(MI->getOperand(1).getReg())
> -+                                .addImm(0)
> -+                                .addReg(MI->getOperand(0).getReg()));
> -+    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADD4)
> -+                                .addReg(MI->getOperand(0).getReg())
> -+                                .addReg(MI->getOperand(1).getReg())
> -+                                .addReg(MI->getOperand(0).getReg()));
> -+    return;
> -+  }
> -   case PPC::PPC32GOT: {
> -     MCSymbol *GOTSymbol = OutContext.GetOrCreateSymbol(StringRef("_GLOBAL_OFFSET_TABLE_"));
> -     const MCExpr *SymGotTlsL =
> -@@ -546,40 +625,54 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
> -                                 .addExpr(SymGotTlsGD));
> -     return;
> -   }
> --  case PPC::ADDItlsgdL: {
> -+  case PPC::ADDItlsgdL:
> -     // Transform: %Xd = ADDItlsgdL %Xs, <ga:@sym>
> -     // Into:      %Xd = ADDI8 %Xs, sym@got@tlsgd@l
> --    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
> -+  case PPC::ADDItlsgdL32: {
> -+    // Transform: %Rd = ADDItlsgdL32 %Rs, <ga:@sym>
> -+    // Into:      %Rd = ADDI %Rs, sym@got@tlsgd
> -     const MachineOperand &MO = MI->getOperand(2);
> -     const GlobalValue *GValue = MO.getGlobal();
> -     MCSymbol *MOSymbol = getSymbol(GValue);
> -     const MCExpr *SymGotTlsGD =
> --      MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO,
> -+      MCSymbolRefExpr::Create(MOSymbol, Subtarget.isPPC64() ?
> -+                                         MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO :
> -+                                         MCSymbolRefExpr::VK_PPC_GOT_TLSGD,
> -                               OutContext);
> --    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8)
> --                                .addReg(MI->getOperand(0).getReg())
> --                                .addReg(MI->getOperand(1).getReg())
> --                                .addExpr(SymGotTlsGD));
> -+    EmitToStreamer(OutStreamer,
> -+                   MCInstBuilder(Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI)
> -+                   .addReg(MI->getOperand(0).getReg())
> -+                   .addReg(MI->getOperand(1).getReg())
> -+                   .addExpr(SymGotTlsGD));
> -     return;
> -   }
> --  case PPC::GETtlsADDR: {
> -+  case PPC::GETtlsADDR:
> -     // Transform: %X3 = GETtlsADDR %X3, <ga:@sym>
> -     // Into:      BL8_NOP_TLS __tls_get_addr(sym@tlsgd)
> --    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
> -+  case PPC::GETtlsADDR32: {
> -+    // Transform: %R3 = GETtlsADDR32 %R3, <ga:@sym>
> -+    // Into:      BL_TLS __tls_get_addr(sym@tlsgd)@PLT
> -
> -     StringRef Name = "__tls_get_addr";
> -     MCSymbol *TlsGetAddr = OutContext.GetOrCreateSymbol(Name);
> -+    MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
> -+
> -+    if (!Subtarget.isPPC64() && !Subtarget.isDarwin() &&
> -+        TM.getRelocationModel() == Reloc::PIC_)
> -+      Kind = MCSymbolRefExpr::VK_PLT;
> -     const MCSymbolRefExpr *TlsRef =
> --      MCSymbolRefExpr::Create(TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
> -+      MCSymbolRefExpr::Create(TlsGetAddr, Kind, OutContext);
> -     const MachineOperand &MO = MI->getOperand(2);
> -     const GlobalValue *GValue = MO.getGlobal();
> -     MCSymbol *MOSymbol = getSymbol(GValue);
> -     const MCExpr *SymVar =
> -       MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSGD,
> -                               OutContext);
> --    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL8_NOP_TLS)
> --                                .addExpr(TlsRef)
> --                                .addExpr(SymVar));
> -+    EmitToStreamer(OutStreamer,
> -+                   MCInstBuilder(Subtarget.isPPC64() ?
> -+                                  PPC::BL8_NOP_TLS : PPC::BL_TLS)
> -+                   .addExpr(TlsRef)
> -+                   .addExpr(SymVar));
> -     return;
> -   }
> -   case PPC::ADDIStlsldHA: {
> -@@ -598,72 +691,93 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
> -                                 .addExpr(SymGotTlsLD));
> -     return;
> -   }
> --  case PPC::ADDItlsldL: {
> -+  case PPC::ADDItlsldL:
> -     // Transform: %Xd = ADDItlsldL %Xs, <ga:@sym>
> -     // Into:      %Xd = ADDI8 %Xs, sym@got@tlsld@l
> --    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
> -+  case PPC::ADDItlsldL32: {
> -+    // Transform: %Rd = ADDItlsldL32 %Rs, <ga:@sym>
> -+    // Into:      %Rd = ADDI %Rs, sym@got@tlsld
> -     const MachineOperand &MO = MI->getOperand(2);
> -     const GlobalValue *GValue = MO.getGlobal();
> -     MCSymbol *MOSymbol = getSymbol(GValue);
> -     const MCExpr *SymGotTlsLD =
> --      MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO,
> -+      MCSymbolRefExpr::Create(MOSymbol, Subtarget.isPPC64() ?
> -+                                         MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO :
> -+                                         MCSymbolRefExpr::VK_PPC_GOT_TLSLD,
> -                               OutContext);
> --    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8)
> --                                .addReg(MI->getOperand(0).getReg())
> --                                .addReg(MI->getOperand(1).getReg())
> --                                .addExpr(SymGotTlsLD));
> -+    EmitToStreamer(OutStreamer,
> -+                   MCInstBuilder(Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI)
> -+                   .addReg(MI->getOperand(0).getReg())
> -+                   .addReg(MI->getOperand(1).getReg())
> -+                   .addExpr(SymGotTlsLD));
> -     return;
> -   }
> --  case PPC::GETtlsldADDR: {
> -+  case PPC::GETtlsldADDR:
> -     // Transform: %X3 = GETtlsldADDR %X3, <ga:@sym>
> -     // Into:      BL8_NOP_TLS __tls_get_addr(sym@tlsld)
> --    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
> -+  case PPC::GETtlsldADDR32: {
> -+    // Transform: %R3 = GETtlsldADDR32 %R3, <ga:@sym>
> -+    // Into:      BL_TLS __tls_get_addr(sym@tlsld)@PLT
> -
> -     StringRef Name = "__tls_get_addr";
> -     MCSymbol *TlsGetAddr = OutContext.GetOrCreateSymbol(Name);
> -+    MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
> -+
> -+    if (!Subtarget.isPPC64() && !Subtarget.isDarwin() &&
> -+        TM.getRelocationModel() == Reloc::PIC_)
> -+      Kind = MCSymbolRefExpr::VK_PLT;
> -+
> -     const MCSymbolRefExpr *TlsRef =
> --      MCSymbolRefExpr::Create(TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
> -+      MCSymbolRefExpr::Create(TlsGetAddr, Kind, OutContext);
> -     const MachineOperand &MO = MI->getOperand(2);
> -     const GlobalValue *GValue = MO.getGlobal();
> -     MCSymbol *MOSymbol = getSymbol(GValue);
> -     const MCExpr *SymVar =
> -       MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSLD,
> -                               OutContext);
> --    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL8_NOP_TLS)
> --                                .addExpr(TlsRef)
> --                                .addExpr(SymVar));
> -+    EmitToStreamer(OutStreamer,
> -+                   MCInstBuilder(Subtarget.isPPC64() ?
> -+                                  PPC::BL8_NOP_TLS : PPC::BL_TLS)
> -+                   .addExpr(TlsRef)
> -+                   .addExpr(SymVar));
> -     return;
> -   }
> --  case PPC::ADDISdtprelHA: {
> -+  case PPC::ADDISdtprelHA:
> -     // Transform: %Xd = ADDISdtprelHA %X3, <ga:@sym>
> -     // Into:      %Xd = ADDIS8 %X3, sym@dtprel@ha
> --    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
> -+  case PPC::ADDISdtprelHA32: {
> -+    // Transform: %Rd = ADDISdtprelHA32 %R3, <ga:@sym>
> -+    // Into:      %Rd = ADDIS %R3, sym@dtprel@ha
> -     const MachineOperand &MO = MI->getOperand(2);
> -     const GlobalValue *GValue = MO.getGlobal();
> -     MCSymbol *MOSymbol = getSymbol(GValue);
> -     const MCExpr *SymDtprel =
> -       MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_HA,
> -                               OutContext);
> --    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8)
> --                                .addReg(MI->getOperand(0).getReg())
> --                                .addReg(PPC::X3)
> --                                .addExpr(SymDtprel));
> -+    EmitToStreamer(OutStreamer,
> -+                   MCInstBuilder(Subtarget.isPPC64() ? PPC::ADDIS8 : PPC::ADDIS)
> -+                   .addReg(MI->getOperand(0).getReg())
> -+                   .addReg(Subtarget.isPPC64() ? PPC::X3 : PPC::R3)
> -+                   .addExpr(SymDtprel));
> -     return;
> -   }
> --  case PPC::ADDIdtprelL: {
> -+  case PPC::ADDIdtprelL:
> -     // Transform: %Xd = ADDIdtprelL %Xs, <ga:@sym>
> -     // Into:      %Xd = ADDI8 %Xs, sym@dtprel@l
> --    assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
> -+  case PPC::ADDIdtprelL32: {
> -+    // Transform: %Rd = ADDIdtprelL32 %Rs, <ga:@sym>
> -+    // Into:      %Rd = ADDI %Rs, sym@dtprel@l
> -     const MachineOperand &MO = MI->getOperand(2);
> -     const GlobalValue *GValue = MO.getGlobal();
> -     MCSymbol *MOSymbol = getSymbol(GValue);
> -     const MCExpr *SymDtprel =
> -       MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_LO,
> -                               OutContext);
> --    EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8)
> --                                .addReg(MI->getOperand(0).getReg())
> --                                .addReg(MI->getOperand(1).getReg())
> --                                .addExpr(SymDtprel));
> -+    EmitToStreamer(OutStreamer,
> -+                   MCInstBuilder(Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI)
> -+                   .addReg(MI->getOperand(0).getReg())
> -+                   .addReg(MI->getOperand(1).getReg())
> -+                   .addExpr(SymDtprel));
> -     return;
> -   }
> -   case PPC::MFOCRF:
> -@@ -722,9 +836,60 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr
> -   EmitToStreamer(OutStreamer, TmpInst);
> - }
> -
> -+void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module &M) {
> -+  if (Subtarget.isPPC64() || TM.getRelocationModel() != Reloc::PIC_)
> -+    return AsmPrinter::EmitStartOfAsmFile(M);
> -+
> -+  // FIXME: The use of .got2 assumes large GOT model (-fPIC), which is not
> -+  // optimal for some cases. We should consider supporting small model (-fpic)
> -+  // as well in the future.
> -+  assert(TM.getCodeModel() != CodeModel::Small &&
> -+         "Small code model PIC is currently unsupported.");
> -+  OutStreamer.SwitchSection(OutContext.getELFSection(".got2",
> -+         ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,
> -+         SectionKind::getReadOnly()));
> -+
> -+  MCSymbol *TOCSym = OutContext.GetOrCreateSymbol(Twine(".L.TOC."));
> -+  MCSymbol *CurrentPos = OutContext.CreateTempSymbol();
> -+
> -+  OutStreamer.EmitLabel(CurrentPos);
> -+
> -+  // The GOT pointer points to the middle of the GOT, in order to reference the
> -+  // entire 64kB range. 0x8000 is the midpoint.
> -+  const MCExpr *tocExpr =
> -+    MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(CurrentPos, OutContext),
> -+                            MCConstantExpr::Create(0x8000, OutContext),
> -+                            OutContext);
> -+
> -+  OutStreamer.EmitAssignment(TOCSym, tocExpr);
> -+
> -+  OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
> -+}
> -+
> - void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() {
> --  if (!Subtarget.isPPC64())  // linux/ppc32 - Normal entry label.
> -+  // linux/ppc32 - Normal entry label.
> -+  if (!Subtarget.isPPC64() && TM.getRelocationModel() != Reloc::PIC_)
> -     return AsmPrinter::EmitFunctionEntryLabel();
> -+
> -+  if (!Subtarget.isPPC64()) {
> -+    const PPCFunctionInfo *PPCFI = MF->getInfo<PPCFunctionInfo>();
> -+   if (PPCFI->usesPICBase()) {
> -+      MCSymbol *RelocSymbol = PPCFI->getPICOffsetSymbol();
> -+      MCSymbol *PICBase = MF->getPICBaseSymbol();
> -+      OutStreamer.EmitLabel(RelocSymbol);
> -+
> -+      const MCExpr *OffsExpr =
> -+        MCBinaryExpr::CreateSub(
> -+          MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")),
> -+                                                               OutContext),
> -+                                  MCSymbolRefExpr::Create(PICBase, OutContext),
> -+          OutContext);
> -+        OutStreamer.EmitValue(OffsExpr, 4);
> -+        OutStreamer.EmitLabel(CurrentFnSym);
> -+        return;
> -+      } else
> -+        return AsmPrinter::EmitFunctionEntryLabel();
> -+  }
> -    
> -   // Emit an official procedure descriptor.
> -   MCSectionSubPair Current = OutStreamer.getCurrentSection();
> -@@ -764,17 +929,27 @@ bool PPCLinuxAsmPrinter::doFinalization(Module &M) {
> -   PPCTargetStreamer &TS =
> -       static_cast<PPCTargetStreamer &>(*OutStreamer.getTargetStreamer());
> -
> --  if (isPPC64 && !TOC.empty()) {
> --    const MCSectionELF *Section = OutStreamer.getContext().getELFSection(".toc",
> -+  if (!TOC.empty()) {
> -+    const MCSectionELF *Section;
> -+
> -+    if (isPPC64)
> -+      Section = OutStreamer.getContext().getELFSection(".toc",
> -         ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,
> -         SectionKind::getReadOnly());
> -+       else
> -+      Section = OutStreamer.getContext().getELFSection(".got2",
> -+        ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,
> -+        SectionKind::getReadOnly());
> -     OutStreamer.SwitchSection(Section);
> -
> -     for (MapVector<MCSymbol*, MCSymbol*>::iterator I = TOC.begin(),
> -          E = TOC.end(); I != E; ++I) {
> -       OutStreamer.EmitLabel(I->second);
> -       MCSymbol *S = OutContext.GetOrCreateSymbol(I->first->getName());
> --      TS.emitTCEntry(*S);
> -+      if (isPPC64)
> -+        TS.emitTCEntry(*S);
> -+      else
> -+        OutStreamer.EmitSymbolValue(S, 4);
> -     }
> -   }
> -
> Index: patches/patch-lib_Target_PowerPC_PPCCTRLoops_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCCTRLoops_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCCTRLoops_cpp
> --- patches/patch-lib_Target_PowerPC_PPCCTRLoops_cpp 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,29 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCCTRLoops_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r208501
> -On PPC32, 128-bit shifts might be runtime calls
> -
> -The counter-loops formation pass needs to know what operations might be
> -function calls (because they can't appear in counter-based loops). On PPC32,
> -128-bit shifts might be runtime calls (even though you can't use __int128 on
> -PPC32, it seems that SROA might form them).
> -
> -Fixes PR19709.
> -
> ---- lib/Target/PowerPC/PPCCTRLoops.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/PowerPC/PPCCTRLoops.cpp Sat Jun 14 04:38:11 2014
> -@@ -370,6 +370,14 @@ bool PPCCTRLoops::mightUseCTR(const Triple &TT, BasicB
> -                 J->getOpcode() == Instruction::URem ||
> -                 J->getOpcode() == Instruction::SRem)) {
> -       return true;
> -+    } else if (TT.isArch32Bit() &&
> -+               isLargeIntegerTy(false, J->getType()->getScalarType()) &&
> -+               (J->getOpcode() == Instruction::Shl ||
> -+                J->getOpcode() == Instruction::AShr ||
> -+                J->getOpcode() == Instruction::LShr)) {
> -+      // Only on PPC32, for 128-bit integers (specifically not 64-bit
> -+      // integers), these might be runtime calls.
> -+      return true;
> -     } else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) {
> -       // On PowerPC, indirect jumps use the counter register.
> -       return true;
> Index: patches/patch-lib_Target_PowerPC_PPCFastISel_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCFastISel_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCFastISel_cpp
> --- patches/patch-lib_Target_PowerPC_PPCFastISel_cpp 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,38 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCFastISel_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r204155
> -Fix PR19144: Incorrect offset generated for int-to-fp conversion at -O0.
> -
> -When converting a signed 32-bit integer to double-precision floating point on
> -hardware without a lfiwax instruction, we have to instead use a lfd followed
> -by fcfid.  We were erroneously offsetting the address by 4 bytes in
> -preparation for either a lfiwax or lfiwzx when generating the lfd.  This fixes
> -that silly error.
> -
> -This was not caught in the test suite since the conversion tests were run with
> --mcpu=pwr7, which implies availability of lfiwax.  I've added another test
> -case for older hardware that checks the code we expect in the absence of
> -lfiwax and other flavors of fcfid.  There are fewer tests in this test case
> -because we punt to DAG selection in more cases on older hardware.  (We must
> -generate complex fiddly sequences in those cases, and there is marginal
> -benefit in duplicating that logic in fast-isel.)
> -
> ---- lib/Target/PowerPC/PPCFastISel.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/PowerPC/PPCFastISel.cpp Sat Jun 14 04:07:38 2014
> -@@ -898,11 +898,13 @@ unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsign
> -   unsigned LoadOpc = PPC::LFD;
> -
> -   if (SrcVT == MVT::i32) {
> --    Addr.Offset = 4;
> --    if (!IsSigned)
> -+    if (!IsSigned) {
> -       LoadOpc = PPC::LFIWZX;
> --    else if (PPCSubTarget.hasLFIWAX())
> -+      Addr.Offset = 4;
> -+    } else if (PPCSubTarget.hasLFIWAX()) {
> -       LoadOpc = PPC::LFIWAX;
> -+      Addr.Offset = 4;
> -+    }
> -   }
> -
> -   const TargetRegisterClass *RC = &PPC::F8RCRegClass;
> Index: patches/patch-lib_Target_PowerPC_PPCFrameLowering_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCFrameLowering_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCFrameLowering_cpp
> --- patches/patch-lib_Target_PowerPC_PPCFrameLowering_cpp 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,93 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCFrameLowering_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- lib/Target/PowerPC/PPCFrameLowering.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/PowerPC/PPCFrameLowering.cpp Sun Jul 27 03:29:47 2014
> -@@ -299,7 +299,7 @@ void PPCFrameLowering::replaceFPWithRealFP(MachineFunc
> -   const PPCRegisterInfo *RegInfo =
> -     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
> -   bool HasBP = RegInfo->hasBasePointer(MF);
> --  unsigned BPReg  = HasBP ? (unsigned) PPC::R30 : FPReg;
> -+  unsigned BPReg  = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
> -   unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
> -
> -   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
> -@@ -344,6 +344,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &M
> -   DebugLoc dl;
> -   bool needsFrameMoves = MMI.hasDebugInfo() ||
> -     MF.getFunction()->needsUnwindTableEntry();
> -+  bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
> -
> -   // Get processor type.
> -   bool isPPC64 = Subtarget.isPPC64();
> -@@ -387,7 +388,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &M
> -   bool HasBP = RegInfo->hasBasePointer(MF);
> -
> -   unsigned SPReg       = isPPC64 ? PPC::X1  : PPC::R1;
> --  unsigned BPReg       = isPPC64 ? PPC::X30 : PPC::R30;
> -+  unsigned BPReg       = RegInfo->getBaseRegister(MF);
> -   unsigned FPReg       = isPPC64 ? PPC::X31 : PPC::R31;
> -   unsigned LRReg       = isPPC64 ? PPC::LR8 : PPC::LR;
> -   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
> -@@ -442,7 +443,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &M
> -       BPOffset = FFI->getObjectOffset(BPIndex);
> -     } else {
> -       BPOffset =
> --        PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
> -+        PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
> -+                                                   isDarwinABI,
> -+                                                   isPIC);
> -     }
> -   }
> -
> -@@ -675,6 +678,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &M
> -   // Get the ABI.
> -   bool isDarwinABI = Subtarget.isDarwinABI();
> -   bool isSVR4ABI = Subtarget.isSVR4ABI();
> -+  bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
> -
> -   // Check if the link register (LR) has been saved.
> -   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
> -@@ -685,7 +689,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &M
> -   bool HasBP = RegInfo->hasBasePointer(MF);
> -
> -   unsigned SPReg      = isPPC64 ? PPC::X1  : PPC::R1;
> --  unsigned BPReg      = isPPC64 ? PPC::X30 : PPC::R30;
> -+  unsigned BPReg      = RegInfo->getBaseRegister(MF);
> -   unsigned FPReg      = isPPC64 ? PPC::X31 : PPC::R31;
> -   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
> -   unsigned TempReg     = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
> -@@ -725,7 +729,9 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &M
> -       BPOffset = FFI->getObjectOffset(BPIndex);
> -     } else {
> -       BPOffset =
> --        PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
> -+        PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
> -+                                                   isDarwinABI,
> -+                                                   isPIC);
> -     }
> -   }
> -
> -@@ -902,6 +908,7 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan
> -   int FPSI = FI->getFramePointerSaveIndex();
> -   bool isPPC64 = Subtarget.isPPC64();
> -   bool isDarwinABI  = Subtarget.isDarwinABI();
> -+  bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
> -   MachineFrameInfo *MFI = MF.getFrameInfo();
> -
> -   // If the frame pointer save index hasn't been defined yet.
> -@@ -916,7 +923,7 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan
> -
> -   int BPSI = FI->getBasePointerSaveIndex();
> -   if (!BPSI && RegInfo->hasBasePointer(MF)) {
> --    int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI);
> -+    int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
> -     // Allocate the frame index for the base pointer save area.
> -     BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
> -     // Save the result.
> Index: patches/patch-lib_Target_PowerPC_PPCFrameLowering_h
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCFrameLowering_h
> diff -N patches/patch-lib_Target_PowerPC_PPCFrameLowering_h
> --- patches/patch-lib_Target_PowerPC_PPCFrameLowering_h 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,28 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCFrameLowering_h,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- lib/Target/PowerPC/PPCFrameLowering.h.orig Sun Jul 27 00:40:47 2014
> -+++ lib/Target/PowerPC/PPCFrameLowering.h Sun Jul 27 00:42:07 2014
> -@@ -96,12 +96,14 @@ class PPCFrameLowering: public TargetFrameLowering { (
> -
> -   /// getBasePointerSaveOffset - Return the previous frame offset to save the
> -   /// base pointer.
> --  static unsigned getBasePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
> -+  static unsigned getBasePointerSaveOffset(bool isPPC64,
> -+                                           bool isDarwinABI,
> -+                                           bool isPIC) {
> -     if (isDarwinABI)
> -       return isPPC64 ? -16U : -8U;
> -
> -     // SVR4 ABI: First slot in the general register save area.
> --    return isPPC64 ? -16U : -8U;
> -+    return isPPC64 ? -16U : isPIC ? -12U : -8U;
> -   }
> -
> -   /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
> Index: patches/patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp
> --- patches/patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp 28 Dec 2014 00:30:18 -0000 1.3
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,109 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCISelDAGToDAG_cpp,v 1.3 2014/12/28 00:30:18 brad Exp $
> -
> -r203054
> -The PPC global base register cannot be r0
> -
> -The global base register cannot be r0 because it might end up as the first
> -argument to addi or addis. Fixes PR18316.
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> -r213960
> -[PowerPC] Support TLS on PPC32/ELF
> -
> -r209821
> -[PPC] Use alias symbols in address computation.
> -
> -This seems to match what gcc does for ppc and what every other llvm
> -backend does.
> -
> ---- lib/Target/PowerPC/PPCISelDAGToDAG.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Dec 26 15:33:12 2014
> -@@ -15,6 +15,7 @@
> - #define DEBUG_TYPE "ppc-codegen"
> - #include "PPC.h"
> - #include "MCTargetDesc/PPCPredicates.h"
> -+#include "PPCMachineFunctionInfo.h"
> - #include "PPCTargetMachine.h"
> - #include "llvm/CodeGen/MachineFunction.h"
> - #include "llvm/CodeGen/MachineInstrBuilder.h"
> -@@ -272,11 +273,23 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
> -     DebugLoc dl;
> -
> -     if (PPCLowering.getPointerTy() == MVT::i32) {
> --      GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
> -+      if (PPCSubTarget.isTargetELF())
> -+        GlobalBaseReg = PPC::R30;
> -+      else
> -+        GlobalBaseReg =
> -+          RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
> -       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
> -       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
> -+      if (PPCSubTarget.isTargetELF()) {
> -+        unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
> -+        BuildMI(FirstMBB, MBBI, dl,
> -+                TII.get(PPC::GetGBRO), TempReg).addReg(GlobalBaseReg);
> -+        BuildMI(FirstMBB, MBBI, dl,
> -+                TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg).addReg(TempReg);
> -+        MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
> -+      }
> -     } else {
> --      GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass);
> -+      GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
> -       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
> -       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
> -     }
> -@@ -1373,7 +1386,13 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
> -     return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
> -   }
> -   case PPCISD::TOC_ENTRY: {
> --    assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI");
> -+    if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
> -+      SDValue GA = N->getOperand(0);
> -+      return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
> -+                                    N->getOperand(1));
> -+       }
> -+    assert (PPCSubTarget.isPPC64() &&
> -+            "Only supported for 64-bit ABI and 32-bit SVR4");
> -
> -     // For medium and large code model, we generate two instructions as
> -     // described below.  Otherwise we allow SelectCodeCommon to handle this,
> -@@ -1400,24 +1419,21 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
> -
> -     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
> -       const GlobalValue *GValue = G->getGlobal();
> --      const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
> --      const GlobalValue *RealGValue = GAlias ?
> --        GAlias->resolveAliasedGlobal(false) : GValue;
> --      const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
> --      assert((GVar || isa<Function>(RealGValue)) &&
> --             "Unexpected global value subclass!");
> --
> --      // An external variable is one without an initializer.  For these,
> --      // for variables with common linkage, and for Functions, generate
> --      // the LDtocL form.
> --      if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() ||
> --          RealGValue->hasAvailableExternallyLinkage())
> -+      if (GValue->getType()->getElementType()->isFunctionTy() ||
> -+          GValue->isDeclaration() || GValue->hasCommonLinkage() ||
> -+          GValue->hasAvailableExternallyLinkage())
> -         return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
> -                                       SDValue(Tmp, 0));
> -     }
> -
> -     return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
> -                                   SDValue(Tmp, 0), GA);
> -+  }
> -+  case PPCISD::PPC32_PICGOT: {
> -+    // Generate a PIC-safe GOT reference.
> -+    assert(!PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI() &&
> -+      "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
> -+    return CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT, PPCLowering.getPointerTy(), MVT::i32);
> -   }
> -   case PPCISD::VADD_SPLAT: {
> -     // This expands into one of three sequences, depending on whether
> Index: patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp
> --- patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp 30 Dec 2014 22:41:09 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,251 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCISelLowering_cpp,v 1.2 2014/12/30 22:41:09 brad Exp $
> -
> -r213899
> -Don't use 128bit functions on PPC32.
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> -r213960
> -[PowerPC] Support TLS on PPC32/ELF
> -
> -r223708
> -[PowerPC] Don't use a non-allocatable register to implement the 'cc' alias
> -
> -GCC accepts 'cc' as an alias for 'cr0', and we need to do the same when
> -processing inline asm constraints. This had previously been implemented using a
> -non-allocatable register, named 'cc', that was listed as an alias of 'cr0', but
> -the infrastructure does not seem to support this properly (neither the register
> -allocator nor the scheduler properly accounts for the alias). Instead, we can
> -just process this as a naming alias inside of the inline asm
> -constraint-processing code, so we'll do that instead.
> -
> -There are two regression tests, one where the post-RA scheduler did the wrong
> -thing with the non-allocatable alias, and one where the register allocator did
> -the wrong thing. Fixes PR21742.
> -
> ---- lib/Target/PowerPC/PPCISelLowering.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/PowerPC/PPCISelLowering.cpp Tue Dec 30 17:32:03 2014
> -@@ -543,6 +543,13 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine
> -   // Altivec instructions set fields to all zeros or all ones.
> -   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
> -
> -+  if (!isPPC64) {
> -+    // These libcalls are not available in 32-bit.
> -+    setLibcallName(RTLIB::SHL_I128, 0);
> -+    setLibcallName(RTLIB::SRL_I128, 0);
> -+    setLibcallName(RTLIB::SRA_I128, 0);
> -+  }
> -+
> -   if (isPPC64) {
> -     setStackPointerRegisterToSaveRestore(PPC::X1);
> -     setExceptionPointerRegister(PPC::X3);
> -@@ -1360,10 +1367,9 @@ static bool GetLabelAccessInfo(const TargetMachine &TM
> -   HiOpFlags = PPCII::MO_HA;
> -   LoOpFlags = PPCII::MO_LO;
> -
> --  // Don't use the pic base if not in PIC relocation model.  Or if we are on a
> --  // non-darwin platform.  We don't support PIC on other platforms yet.
> --  bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
> --               TM.getSubtarget<PPCSubtarget>().isDarwin();
> -+  // Don't use the pic base if not in PIC relocation model.
> -+  bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
> -+
> -   if (isPIC) {
> -     HiOpFlags |= PPCII::MO_PIC_FLAG;
> -     LoOpFlags |= PPCII::MO_PIC_FLAG;
> -@@ -1419,6 +1425,15 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue O
> -
> -   unsigned MOHiFlag, MOLoFlag;
> -   bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
> -+
> -+  if (isPIC && PPCSubTarget.isSVR4ABI()) {
> -+    SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
> -+                                           PPCII::MO_PIC_FLAG);
> -+    SDLoc DL(CP);
> -+    return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
> -+                       DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
> -+  }
> -+
> -   SDValue CPIHi =
> -     DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
> -   SDValue CPILo =
> -@@ -1440,6 +1455,15 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op,
> -
> -   unsigned MOHiFlag, MOLoFlag;
> -   bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
> -+
> -+  if (isPIC && PPCSubTarget.isSVR4ABI()) {
> -+    SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
> -+                                        PPCII::MO_PIC_FLAG);
> -+    SDLoc DL(GA);
> -+    return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
> -+                       DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
> -+  }
> -+
> -   SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
> -   SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
> -   return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
> -@@ -1502,47 +1526,61 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDVal
> -
> -   if (Model == TLSModel::GeneralDynamic) {
> -     SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
> --    SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
> --    SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
> --                                     GOTReg, TGA);
> -+    SDValue GOTPtr;
> -+    if (is64bit) {
> -+      SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
> -+      GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
> -+                                   GOTReg, TGA);
> -+    } else {
> -+      GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
> -+    }
> -     SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
> --                                   GOTEntryHi, TGA);
> -+                                   GOTPtr, TGA);
> -
> -     // We need a chain node, and don't have one handy.  The underlying
> -     // call has no side effects, so using the function entry node
> -     // suffices.
> -     SDValue Chain = DAG.getEntryNode();
> --    Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
> --    SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
> -+    Chain = DAG.getCopyToReg(Chain, dl,
> -+                             is64bit ? PPC::X3 : PPC::R3, GOTEntry);
> -+    SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
> -+                                      is64bit ? MVT::i64 : MVT::i32);
> -     SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
> -                                   PtrVT, ParmReg, TGA);
> -     // The return value from GET_TLS_ADDR really is in X3 already, but
> -     // some hacks are needed here to tie everything together.  The extra
> -     // copies dissolve during subsequent transforms.
> --    Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
> --    return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
> -+    Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
> -+    return DAG.getCopyFromReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, PtrVT);
> -   }
> -
> -   if (Model == TLSModel::LocalDynamic) {
> -     SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
> --    SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
> --    SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
> --                                     GOTReg, TGA);
> -+    SDValue GOTPtr;
> -+    if (is64bit) {
> -+      SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
> -+      GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
> -+                           GOTReg, TGA);
> -+    } else {
> -+      GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
> -+    }
> -     SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
> --                                   GOTEntryHi, TGA);
> -+                                   GOTPtr, TGA);
> -
> -     // We need a chain node, and don't have one handy.  The underlying
> -     // call has no side effects, so using the function entry node
> -     // suffices.
> -     SDValue Chain = DAG.getEntryNode();
> --    Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
> --    SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
> -+    Chain = DAG.getCopyToReg(Chain, dl,
> -+                             is64bit ? PPC::X3 : PPC::R3, GOTEntry);
> -+    SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
> -+                                      is64bit ? MVT::i64 : MVT::i32);
> -     SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
> -                                   PtrVT, ParmReg, TGA);
> -     // The return value from GET_TLSLD_ADDR really is in X3 already, but
> -     // some hacks are needed here to tie everything together.  The extra
> -     // copies dissolve during subsequent transforms.
> --    Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
> -+    Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
> -     SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
> -                                       Chain, ParmReg, TGA);
> -     return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
> -@@ -1569,6 +1607,14 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue
> -   unsigned MOHiFlag, MOLoFlag;
> -   bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
> -
> -+  if (isPIC && PPCSubTarget.isSVR4ABI()) {
> -+    SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
> -+                                            GSDN->getOffset(),
> -+                                            PPCII::MO_PIC_FLAG);
> -+    return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
> -+                       DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
> -+  }
> -+
> -   SDValue GAHi =
> -     DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
> -   SDValue GALo =
> -@@ -3276,15 +3322,18 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Calle
> -     // far-call stubs may be outside relocation limits for a BL instruction.
> -     if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
> -       unsigned OpFlags = 0;
> --      if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
> -+      if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
> -           (PPCSubTarget.getTargetTriple().isMacOSX() &&
> -            PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
> -           (G->getGlobal()->isDeclaration() ||
> --           G->getGlobal()->isWeakForLinker())) {
> -+           G->getGlobal()->isWeakForLinker())) ||
> -+          (PPCSubTarget.isTargetELF() && !isPPC64 &&
> -+           !G->getGlobal()->hasLocalLinkage() &&
> -+           DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
> -         // PC-relative references to external symbols should go through $stub,
> -         // unless we're building with the leopard linker or later, which
> -         // automatically synthesizes these stubs.
> --        OpFlags = PPCII::MO_DARWIN_STUB;
> -+        OpFlags = PPCII::MO_PLT_OR_STUB;
> -       }
> -
> -       // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
> -@@ -3300,13 +3349,15 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Calle
> -   if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
> -     unsigned char OpFlags = 0;
> -
> --    if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
> --        (PPCSubTarget.getTargetTriple().isMacOSX() &&
> --         PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
> -+    if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
> -+         (PPCSubTarget.getTargetTriple().isMacOSX() &&
> -+          PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
> -+        (PPCSubTarget.isTargetELF() && !isPPC64 &&
> -+         DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
> -       // PC-relative references to external symbols should go through $stub,
> -       // unless we're building with the leopard linker or later, which
> -       // automatically synthesizes these stubs.
> --      OpFlags = PPCII::MO_DARWIN_STUB;
> -+      OpFlags = PPCII::MO_PLT_OR_STUB;
> -     }
> -
> -     Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
> -@@ -6371,7 +6422,10 @@ PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
> -   // Since FP is only updated here but NOT referenced, it's treated as GPR.
> -   unsigned FP  = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
> -   unsigned SP  = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
> --  unsigned BP  = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
> -+  unsigned BP  = (PVT == MVT::i64) ? PPC::X30 :
> -+                  (PPCSubTarget.isSVR4ABI() &&
> -+                   MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
> -+                     PPC::R29 : PPC::R30);
> -
> -   MachineInstrBuilder MIB;
> -
> -@@ -8317,6 +8371,12 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const
> -     return std::make_pair(TRI->getMatchingSuperReg(R.first,
> -                             PPC::sub_32, &PPC::G8RCRegClass),
> -                           &PPC::G8RCRegClass);
> -+  }
> -+
> -+  // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
> -+  if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
> -+    R.first = PPC::CR0;
> -+    R.second = &PPC::CRRCRegClass;
> -   }
> -
> -   return R;
> Index: patches/patch-lib_Target_PowerPC_PPCISelLowering_h
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCISelLowering_h
> diff -N patches/patch-lib_Target_PowerPC_PPCISelLowering_h
> --- patches/patch-lib_Target_PowerPC_PPCISelLowering_h 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,18 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCISelLowering_h,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213960
> -[PowerPC] Support TLS on PPC32/ELF
> -
> ---- lib/Target/PowerPC/PPCISelLowering.h.orig Sun Jul 27 04:08:54 2014
> -+++ lib/Target/PowerPC/PPCISelLowering.h Sun Jul 27 04:09:34 2014
> -@@ -187,6 +187,10 @@ namespace llvm {
> -       /// on PPC32.
> -       PPC32_GOT,
> -
> -+      /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
> -+      /// local dynamic TLS on PPC32.
> -+      PPC32_PICGOT,
> -+
> -       /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
> -       /// TLS model, produces an ADDIS8 instruction that adds the GOT
> -       /// base to sym\@got\@tprel\@ha.
> Index: patches/patch-lib_Target_PowerPC_PPCInstrInfo_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCInstrInfo_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCInstrInfo_cpp
> --- patches/patch-lib_Target_PowerPC_PPCInstrInfo_cpp 11 Sep 2014 17:59:51 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,20 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCInstrInfo_cpp,v 1.1 2014/09/11 17:59:51 brad Exp $
> -
> -r215238
> -Provide an implementation of getNoopForMachoTarget for PPC, otherwise
> -empty functions will assert in the MC object writer.
> -
> ---- lib/Target/PowerPC/PPCInstrInfo.cpp.orig Fri Aug 29 23:39:36 2014
> -+++ lib/Target/PowerPC/PPCInstrInfo.cpp Fri Aug 29 23:41:26 2014
> -@@ -296,6 +296,11 @@ void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
> -   BuildMI(MBB, MI, DL, get(Opcode));
> - }
> -
> -+/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
> -+void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
> -+  NopInst.setOpcode(PPC::NOP);
> -+}
> -+
> - // Branch analysis.
> - // Note: If the condition register is set to CTR or CTR8 then this is a
> - // BDNZ (imm == 1) or BDZ (imm == 0) branch.
> Index: patches/patch-lib_Target_PowerPC_PPCInstrInfo_h
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCInstrInfo_h
> diff -N patches/patch-lib_Target_PowerPC_PPCInstrInfo_h
> --- patches/patch-lib_Target_PowerPC_PPCInstrInfo_h 11 Sep 2014 17:59:51 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,17 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCInstrInfo_h,v 1.1 2014/09/11 17:59:51 brad Exp $
> -
> -r215238
> -Provide an implementation of getNoopForMachoTarget for PPC, otherwise
> -empty functions will assert in the MC object writer.
> -
> ---- lib/Target/PowerPC/PPCInstrInfo.h.orig Fri Aug 29 23:39:27 2014
> -+++ lib/Target/PowerPC/PPCInstrInfo.h Fri Aug 29 23:40:50 2014
> -@@ -228,6 +228,8 @@ class PPCInstrInfo : public PPCGenInstrInfo { (public)
> -   /// instruction may be.  This returns the maximum number of bytes.
> -   ///
> -   virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
> -+
> -+  void getNoopForMachoTarget(MCInst &NopInst) const;
> - };
> -
> - }
> Index: patches/patch-lib_Target_PowerPC_PPCInstrInfo_td
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCInstrInfo_td
> diff -N patches/patch-lib_Target_PowerPC_PPCInstrInfo_td
> --- patches/patch-lib_Target_PowerPC_PPCInstrInfo_td 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,106 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCInstrInfo_td,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> -r213960
> -[PowerPC] Support TLS on PPC32/ELF
> -
> ---- lib/Target/PowerPC/PPCInstrInfo.td.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/PowerPC/PPCInstrInfo.td Sun Jul 27 04:42:32 2014
> -@@ -57,6 +57,9 @@ def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
> -   SDTCisPtrTy<0>, SDTCisVT<1, i32>
> - ]>;
> -
> -+def tocentry32 : Operand<iPTR> {
> -+  let MIOperandInfo = (ops i32imm:$imm);
> -+}
> -
> - //===----------------------------------------------------------------------===//
> - // PowerPC specific DAG Nodes.
> -@@ -580,6 +583,12 @@ def tlsreg32 : Operand<i32> {
> -   let EncoderMethod = "getTLSRegEncoding";
> -   let ParserMatchClass = PPCTLSRegOperand;
> - }
> -+def tlsgd32 : Operand<i32> {}
> -+def tlscall32 : Operand<i32> {
> -+  let PrintMethod = "printTLSCall";
> -+  let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
> -+  let EncoderMethod = "getTLSCallEncoding";
> -+}
> -
> - // PowerPC Predicate operand.
> - def pred : Operand<OtherVT> {
> -@@ -1063,6 +1072,8 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
> -                     "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
> -
> -     let isCodeGenOnly = 1 in {
> -+      def BL_TLS  : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
> -+                          "bl $func", IIC_BrB, []>;
> -       def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
> -                        "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
> -       def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
> -@@ -2369,12 +2380,56 @@ def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
> - def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
> -                 [(set i32:$rD, (PPCppc32GOT))]>;
> -
> -+// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
> -+// This uses two output registers, the first as the real output, the second as a
> -+// temporary register, used internally in code generation.
> -+def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
> -+                []>, NoEncode<"$rT">;
> -+
> - def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
> --                        "#LDgotTprelL32",
> --                        [(set i32:$rD,
> --                          (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
> -+                           "#LDgotTprelL32",
> -+                           [(set i32:$rD,
> -+                             (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
> - def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
> -           (ADD4TLS $in, tglobaltlsaddr:$g)>;
> -+
> -+def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
> -+                         "#ADDItlsgdL32",
> -+                         [(set i32:$rD,
> -+                           (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
> -+def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
> -+                          "#GETtlsADDR32",
> -+                          [(set i32:$rD,
> -+                            (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
> -+def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
> -+                          "#ADDItlsldL32",
> -+                          [(set i32:$rD,
> -+                            (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
> -+def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
> -+                            "#GETtlsldADDR32",
> -+                            [(set i32:$rD,
> -+                              (PPCgetTlsldAddr i32:$reg, tglobaltlsaddr:$sym))]>;
> -+def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
> -+                           "#ADDIdtprelL32",
> -+                           [(set i32:$rD,
> -+                             (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
> -+def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
> -+                            "#ADDISdtprelHA32",
> -+                            [(set i32:$rD,
> -+                              (PPCaddisDtprelHA i32:$reg,
> -+                                                tglobaltlsaddr:$disp))]>;
> -+
> -+// Support for Position-independent code
> -+def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
> -+                  "#LWZtoc",
> -+                  [(set i32:$rD,
> -+                     (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
> -+// Get Global (GOT) Base Register offset, from the word immediately preceding
> -+// the function label.
> -+def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
> -+// Update the Global(GOT) Base Register with the above offset.
> -+def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
> -+
> -
> - // Standard shifts.  These are represented separately from the real shifts above
> - // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
> Index: patches/patch-lib_Target_PowerPC_PPCMCInstLower_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCMCInstLower_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCMCInstLower_cpp
> --- patches/patch-lib_Target_PowerPC_PPCMCInstLower_cpp 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,56 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCMCInstLower_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- lib/Target/PowerPC/PPCMCInstLower.cpp.orig Sun Jul 27 01:32:18 2014
> -+++ lib/Target/PowerPC/PPCMCInstLower.cpp Sun Jul 27 01:34:48 2014
> -@@ -13,6 +13,7 @@
> - //===----------------------------------------------------------------------===//
> -
> - #include "PPC.h"
> -+#include "PPCSubtarget.h"
> - #include "MCTargetDesc/PPCMCExpr.h"
> - #include "llvm/ADT/SmallString.h"
> - #include "llvm/ADT/Twine.h"
> -@@ -39,12 +40,14 @@ static MCSymbol *GetSymbolFromOperand(const MachineOpe
> -   Mangler *Mang = AP.Mang;
> -   const DataLayout *DL = TM.getDataLayout();
> -   MCContext &Ctx = AP.OutContext;
> -+  bool isDarwin = TM.getSubtarget<PPCSubtarget>().isDarwin();
> -
> -   SmallString<128> Name;
> -   StringRef Suffix;
> --  if (MO.getTargetFlags() == PPCII::MO_DARWIN_STUB)
> --    Suffix = "$stub";
> --  else if (MO.getTargetFlags() & PPCII::MO_NLP_FLAG)
> -+  if (MO.getTargetFlags() == PPCII::MO_PLT_OR_STUB) {
> -+    if (isDarwin)
> -+      Suffix = "$stub";
> -+  } else if (MO.getTargetFlags() & PPCII::MO_NLP_FLAG)
> -     Suffix = "$non_lazy_ptr";
> -
> -   if (!Suffix.empty())
> -@@ -68,7 +71,7 @@ static MCSymbol *GetSymbolFromOperand(const MachineOpe
> -
> -   // If the target flags on the operand changes the name of the symbol, do that
> -   // before we return the symbol.
> --  if (MO.getTargetFlags() == PPCII::MO_DARWIN_STUB) {
> -+  if (MO.getTargetFlags() == PPCII::MO_PLT_OR_STUB && isDarwin) {
> -     MachineModuleInfoImpl::StubValueTy &StubSym =
> -       getMachOMMI(AP).getFnStubEntry(Sym);
> -     if (StubSym.getPointer())
> -@@ -135,6 +138,9 @@ static MCOperand GetSymbolRef(const MachineOperand &MO
> -       RefKind = MCSymbolRefExpr::VK_PPC_TLS;
> -       break;
> -   }
> -+
> -+  if (MO.getTargetFlags() == PPCII::MO_PLT_OR_STUB && !isDarwin)
> -+    RefKind = MCSymbolRefExpr::VK_PLT;
> -
> -   const MCExpr *Expr = MCSymbolRefExpr::Create(Symbol, RefKind, Ctx);
> -
> Index: patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp
> --- patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,28 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCMachineFunctionInfo_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- lib/Target/PowerPC/PPCMachineFunctionInfo.cpp.orig Sun Jul 27 01:35:45 2014
> -+++ lib/Target/PowerPC/PPCMachineFunctionInfo.cpp Sun Jul 27 01:37:10 2014
> -@@ -8,8 +8,16 @@
> - //===----------------------------------------------------------------------===//
> -
> - #include "PPCMachineFunctionInfo.h"
> -+#include "llvm/IR/DataLayout.h"
> -+#include "llvm/MC/MCContext.h"
> -+#include "llvm/Target/TargetMachine.h"
> -
> - using namespace llvm;
> -
> - void PPCFunctionInfo::anchor() { }
> -
> -+MCSymbol *PPCFunctionInfo::getPICOffsetSymbol() const {
> -+  const DataLayout *DL = MF.getTarget().getDataLayout();
> -+  return MF.getContext().GetOrCreateSymbol(Twine(DL->getPrivateGlobalPrefix())+
> -+    Twine(MF.getFunctionNumber())+"$poff");
> -+}
> Index: patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h
> diff -N patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h
> --- patches/patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,47 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCMachineFunctionInfo_h,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- lib/Target/PowerPC/PPCMachineFunctionInfo.h.orig Sun Jul 27 01:37:54 2014
> -+++ lib/Target/PowerPC/PPCMachineFunctionInfo.h Sun Jul 27 01:40:18 2014
> -@@ -92,6 +92,12 @@ class PPCFunctionInfo : public MachineFunctionInfo {
> -   /// 64-bit SVR4 ABI.
> -   SmallVector<unsigned, 3> MustSaveCRs;
> -
> -+  /// Hold onto our MachineFunction context.
> -+  MachineFunction &MF;
> -+
> -+  /// Whether this uses the PIC Base register or not.
> -+  bool UsesPICBase;
> -+
> - public:
> -   explicit PPCFunctionInfo(MachineFunction &MF)
> -     : FramePointerSaveIndex(0),
> -@@ -109,7 +115,9 @@ class PPCFunctionInfo : public MachineFunctionInfo {
> -       VarArgsStackOffset(0),
> -       VarArgsNumGPR(0),
> -       VarArgsNumFPR(0),
> --      CRSpillFrameIndex(0) {}
> -+      CRSpillFrameIndex(0),
> -+      MF(MF),
> -+      UsesPICBase(0) {}
> -
> -   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
> -   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
> -@@ -170,6 +178,11 @@ class PPCFunctionInfo : public MachineFunctionInfo {
> -   const SmallVectorImpl<unsigned> &
> -     getMustSaveCRs() const { return MustSaveCRs; }
> -   void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); }
> -+
> -+  void setUsesPICBase(bool uses) { UsesPICBase = uses; }
> -+  bool usesPICBase() const { return UsesPICBase; }
> -+
> -+  MCSymbol *getPICOffsetSymbol() const;
> - };
> -
> - } // end of namespace llvm
> Index: patches/patch-lib_Target_PowerPC_PPCRegisterInfo_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCRegisterInfo_cpp
> diff -N patches/patch-lib_Target_PowerPC_PPCRegisterInfo_cpp
> --- patches/patch-lib_Target_PowerPC_PPCRegisterInfo_cpp 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,45 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCRegisterInfo_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- lib/Target/PowerPC/PPCRegisterInfo.cpp.orig Sun Jul 27 01:40:38 2014
> -+++ lib/Target/PowerPC/PPCRegisterInfo.cpp Sun Jul 27 01:45:41 2014
> -@@ -199,7 +199,16 @@ BitVector PPCRegisterInfo::getReservedRegs(const Machi
> -   if (PPCFI->needsFP(MF))
> -     Reserved.set(PPC::R31);
> -
> --  if (hasBasePointer(MF))
> -+  if (hasBasePointer(MF)) {
> -+       if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
> -+        MF.getTarget().getRelocationModel() == Reloc::PIC_)
> -+      Reserved.set(PPC::R29);
> -+    else
> -+      Reserved.set(PPC::R30);
> -+  }
> -+
> -+  if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
> -+      MF.getTarget().getRelocationModel() == Reloc::PIC_)
> -     Reserved.set(PPC::R30);
> -
> -   // Reserve Altivec registers when Altivec is unavailable.
> -@@ -822,7 +831,14 @@ unsigned PPCRegisterInfo::getBaseRegister(const Machin
> -   if (!hasBasePointer(MF))
> -     return getFrameRegister(MF);
> -
> --  return Subtarget.isPPC64() ? PPC::X30 : PPC::R30;
> -+  if (Subtarget.isPPC64())
> -+    return PPC::X30;
> -+
> -+  if (Subtarget.isSVR4ABI() &&
> -+      MF.getTarget().getRelocationModel() == Reloc::PIC_)
> -+    return PPC::R29;
> -+
> -+  return PPC::R30;
> - }
> -
> - bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
> Index: patches/patch-lib_Target_PowerPC_PPCSubtarget_h
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPCSubtarget_h
> diff -N patches/patch-lib_Target_PowerPC_PPCSubtarget_h
> --- patches/patch-lib_Target_PowerPC_PPCSubtarget_h 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,21 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPCSubtarget_h,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- lib/Target/PowerPC/PPCSubtarget.h.orig Sun Jul 27 01:47:26 2014
> -+++ lib/Target/PowerPC/PPCSubtarget.h Sun Jul 27 01:47:59 2014
> -@@ -195,6 +195,9 @@ class PPCSubtarget : public PPCGenSubtargetInfo { (pub
> -   /// isBGQ - True if this is a BG/Q platform.
> -   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
> -
> -+  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
> -+  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
> -+
> -   bool isDarwinABI() const { return isDarwin(); }
> -   bool isSVR4ABI() const { return !isDarwin(); }
> -
> Index: patches/patch-lib_Target_PowerPC_PPC_h
> ===================================================================
> RCS file: patches/patch-lib_Target_PowerPC_PPC_h
> diff -N patches/patch-lib_Target_PowerPC_PPC_h
> --- patches/patch-lib_Target_PowerPC_PPC_h 11 Sep 2014 17:54:13 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,27 +0,0 @@
> -$OpenBSD: patch-lib_Target_PowerPC_PPC_h,v 1.1 2014/09/11 17:54:13 brad Exp $
> -
> -r213427
> -[PowerPC] 32-bit ELF PIC support
> -
> -This adds initial support for PPC32 ELF PIC (Position Independent Code; the
> --fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
> -backend.
> -
> ---- lib/Target/PowerPC/PPC.h.orig Sun Jul 27 00:05:08 2014
> -+++ lib/Target/PowerPC/PPC.h Sun Jul 27 00:06:13 2014
> -@@ -53,10 +53,11 @@ namespace llvm {
> -     // PPC Specific MachineOperand flags.
> -     MO_NO_FLAG,
> -    
> --    /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
> --    /// reference is actually to the "FOO$stub" symbol.  This is used for calls
> --    /// and jumps to external functions on Tiger and earlier.
> --    MO_DARWIN_STUB = 1,
> -+    /// MO_PLT_OR_STUB - On a symbol operand "FOO", this indicates that the
> -+    /// reference is actually to the "FOO$stub" or "FOO@plt" symbol. This is
> -+    /// used for calls and jumps to external functions on Tiger and earlier, and
> -+    /// for PIC calls on Linux and ELF systems.
> -+    MO_PLT_OR_STUB = 1,
> -    
> -     /// MO_PIC_FLAG - If this bit is set, the symbol reference is relative to
> -     /// the function's picbase, e.g. lo16(symbol-picbase).
> Index: patches/patch-lib_Target_R600_AMDGPUCallingConv_td
> ===================================================================
> RCS file: patches/patch-lib_Target_R600_AMDGPUCallingConv_td
> diff -N patches/patch-lib_Target_R600_AMDGPUCallingConv_td
> --- patches/patch-lib_Target_R600_AMDGPUCallingConv_td 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,18 +0,0 @@
> -$OpenBSD: patch-lib_Target_R600_AMDGPUCallingConv_td,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r207990
> -R600/SI: allow 5 more input SGPRs to a shader
> -
> -Our OpenGL driver needs 22 SGPRs (16 user SGPRs + 6 streamout non-user SGPRs).
> -
> ---- lib/Target/R600/AMDGPUCallingConv.td.orig Sun Mar  2 21:57:40 2014
> -+++ lib/Target/R600/AMDGPUCallingConv.td Sat Jun 14 04:35:50 2014
> -@@ -20,7 +20,7 @@ def CC_SI : CallingConv<[
> -   CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[
> -     SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
> -     SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
> --    SGPR16
> -+    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21
> -   ]>>>,
> -
> -   CCIfInReg<CCIfType<[i64] , CCAssignToRegWithShadow<
> Index: patches/patch-lib_Target_R600_R600Instructions_td
> ===================================================================
> RCS file: patches/patch-lib_Target_R600_R600Instructions_td
> diff -N patches/patch-lib_Target_R600_R600Instructions_td
> --- patches/patch-lib_Target_R600_R600Instructions_td 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,26 +0,0 @@
> -$OpenBSD: patch-lib_Target_R600_R600Instructions_td,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r203818
> -R600: LDS instructions shouldn't implicitly define OQAP
> -
> -LDS instructions are pseudo instructions which model
> -the OQAP defs and uses within a single instruction.
> -
> ---- lib/Target/R600/R600Instructions.td.orig Sat Jun 14 03:48:50 2014
> -+++ lib/Target/R600/R600Instructions.td Sat Jun 14 03:50:30 2014
> -@@ -1648,7 +1648,6 @@ class R600_LDS_1A <bits<6> lds_op, string name, list<d
> -   let src2 = 0;
> -   let src2_rel = 0;
> -
> --  let Defs = [OQAP];
> -   let usesCustomInserter = 1;
> -   let LDS_1A = 1;
> -   let DisableEncoding = "$dst";
> -@@ -1684,7 +1683,6 @@ class R600_LDS_1A1D_RET <bits<6> lds_op, string name,
> -   let BaseOp = name;
> -   let usesCustomInserter = 1;
> -   let DisableEncoding = "$dst";
> --  let Defs = [OQAP];
> - }
> -
> - class R600_LDS_1A2D <bits<6> lds_op, string name, list<dag> pattern> :
> Index: patches/patch-lib_Target_R600_SIInstrInfo_td
> ===================================================================
> RCS file: patches/patch-lib_Target_R600_SIInstrInfo_td
> diff -N patches/patch-lib_Target_R600_SIInstrInfo_td
> --- patches/patch-lib_Target_R600_SIInstrInfo_td 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,21 +0,0 @@
> -$OpenBSD: patch-lib_Target_R600_SIInstrInfo_td,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r203281
> -R600/SI: Using SGPRs is illegal for instructions that read carry-out
> -from VCC
> -
> ---- lib/Target/R600/SIInstrInfo.td.orig Sat Jun 14 03:42:53 2014
> -+++ lib/Target/R600/SIInstrInfo.td Sat Jun 14 03:44:40 2014
> -@@ -298,10 +298,10 @@ multiclass VOP2_64 <bits<6> op, string opName, list<da
> -   : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern, revOp>;
> -
> - multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
> --                     string revOp = opName> {
> -+                     RegisterClass src0_rc, string revOp = opName> {
> -
> -   def _e32 : VOP2 <
> --    op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
> -+    op, (outs VReg_32:$dst), (ins src0_rc:$src0, VReg_32:$src1),
> -     opName#"_e32 $dst, $src0, $src1", pattern
> -   >, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
> -
> Index: patches/patch-lib_Target_R600_SIInstructions_td
> ===================================================================
> RCS file: patches/patch-lib_Target_R600_SIInstructions_td
> diff -N patches/patch-lib_Target_R600_SIInstructions_td
> --- patches/patch-lib_Target_R600_SIInstructions_td 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,31 +0,0 @@
> -$OpenBSD: patch-lib_Target_R600_SIInstructions_td,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r203281
> -R600/SI: Using SGPRs is illegal for instructions that read carry-out
> -from VCC
> -
> ---- lib/Target/R600/SIInstructions.td.orig Sat Jun 14 03:44:53 2014
> -+++ lib/Target/R600/SIInstructions.td Sat Jun 14 03:46:43 2014
> -@@ -1007,14 +1007,16 @@ defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCN
> - let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
> - // No patterns so that the scalar instructions are always selected.
> - // The scalar versions will be replaced with vector when needed later.
> --defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", []>;
> --defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", []>;
> --defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">;
> -+defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", [], VSrc_32>;
> -+defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", [], VSrc_32>;
> -+defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
> -+                              "V_SUB_I32">;
> -
> - let Uses = [VCC] in { // Carry-in comes from VCC
> --defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
> --defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
> --defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">;
> -+defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", [], VReg_32>;
> -+defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", [], VReg_32>;
> -+defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
> -+                               "V_SUBB_U32">;
> - } // End Uses = [VCC]
> - } // End isCommutable = 1, Defs = [VCC]
> -
> Index: patches/patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp
> diff -N patches/patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp
> --- patches/patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp 19 May 2015 05:33:39 -0000 1.3
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,449 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp,v 1.3 2015/05/19 05:33:39 ajacoutot Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> -r236107
> -Sparc: Prefer reg+reg address encoding when only one register used.
> -
> -Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces.
> -
> -Futhermore, reg+imm is invalid for the (not yet supported) "alternate
> -address space" instructions.
> -
> -r236137
> -Make Sparc assembler accept parenthesized constant expressions.
> -
> -r237580
> -Add support for the Sparc implementation-defined "ASR" registers.
> -
> -r237581
> -Sparc: Add the "alternate address space" load/store instructions.
> -
> -- Adds support for the asm syntax, which has an immediate integer
> -  "ASI" (address space identifier) appearing after an address, before
> -  a comma.
> -
> -- Adds the various-width load, store, and swap in alternate address
> -  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
> -  sta, swapa)
> -
> -r237582
> -Sparc: Support PSR, TBR, WIM read/write instructions.
> -
> ---- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Mon May 18 19:47:25 2015
> -@@ -12,9 +12,11 @@
> - #include "llvm/ADT/STLExtras.h"
> - #include "llvm/MC/MCContext.h"
> - #include "llvm/MC/MCInst.h"
> -+#include "llvm/MC/MCObjectFileInfo.h"
> - #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
> - #include "llvm/MC/MCStreamer.h"
> - #include "llvm/MC/MCSubtargetInfo.h"
> -+#include "llvm/MC/MCSymbol.h"
> - #include "llvm/MC/MCTargetAsmParser.h"
> - #include "llvm/Support/TargetRegistry.h"
> -
> -@@ -66,14 +68,19 @@ class SparcAsmParser : public MCTargetAsmParser {
> -                StringRef Name);
> -
> -   OperandMatchResultTy
> --  parseSparcAsmOperand(SparcOperand *&Operand);
> -+  parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false);
> -
> -+  OperandMatchResultTy
> -+  parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
> -+
> -   // returns true if Tok is matched to a register and returns register in RegNo.
> -   bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
> -                          unsigned &RegKind);
> -
> -   bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
> -+  bool parseDirectiveWord(unsigned Size, SMLoc L);
> -
> -+  bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
> - public:
> -   SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
> -                 const MCInstrInfo &MII)
> -@@ -120,6 +127,15 @@ class SparcAsmParser : public MCTargetAsmParser {
> -     Sparc::Q8,  Sparc::Q9,  Sparc::Q10, Sparc::Q11,
> -     Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
> -
> -+  static unsigned ASRRegs[32] = {
> -+    SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
> -+    SP::ASR4,  SP::ASR5,  SP::ASR6, SP::ASR7,
> -+    SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
> -+    SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
> -+    SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
> -+    SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
> -+    SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
> -+    SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
> -
> - /// SparcOperand - Instances of this class represent a parsed Sparc machine
> - /// instruction.
> -@@ -131,9 +147,9 @@ class SparcOperand : public MCParsedAsmOperand { (publ
> -     rk_FloatReg,
> -     rk_DoubleReg,
> -     rk_QuadReg,
> --    rk_CCReg,
> --    rk_Y
> -+    rk_Special
> -   };
> -+
> - private:
> -   enum KindTy {
> -     k_Token,
> -@@ -354,13 +370,11 @@ class SparcOperand : public MCParsedAsmOperand { (publ
> -     return Op;
> -   }
> -
> --  static SparcOperand *CreateMEMri(unsigned Base,
> --                                 const MCExpr *Off,
> --                                 SMLoc S, SMLoc E) {
> --    SparcOperand *Op = new SparcOperand(k_MemoryImm);
> -+  static SparcOperand *CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
> -+    SparcOperand *Op = new SparcOperand(k_MemoryReg);
> -     Op->Mem.Base = Base;
> --    Op->Mem.OffsetReg = 0;
> --    Op->Mem.Off = Off;
> -+    Op->Mem.OffsetReg = Sparc::G0;  // always 0
> -+    Op->Mem.Off = 0;
> -     Op->StartLoc = S;
> -     Op->EndLoc = E;
> -     return Op;
> -@@ -415,7 +429,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
> -     return Error(ErrorLoc, "invalid operand for instruction");
> -   }
> -   case Match_MnemonicFail:
> --    return Error(IDLoc, "invalid instruction");
> -+    return Error(IDLoc, "invalid instruction mnemonic");
> -   }
> -   return true;
> - }
> -@@ -439,21 +453,30 @@ ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc
> -   return Error(StartLoc, "invalid register name");
> - }
> -
> -+static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
> -+                                 unsigned VariantID);
> -+
> - bool SparcAsmParser::
> - ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
> -                  SMLoc NameLoc,
> -                  SmallVectorImpl<MCParsedAsmOperand*> &Operands)
> - {
> --  // Check if we have valid mnemonic.
> --  if (!mnemonicIsValid(Name, 0)) {
> --    Parser.eatToEndOfStatement();
> --    return Error(NameLoc, "Unknown instruction");
> --  }
> -+
> -   // First operand in MCInst is instruction mnemonic.
> -   Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
> -
> -+  // apply mnemonic aliases, if any, so that we can parse operands correctly.
> -+  applyMnemonicAliases(Name, getAvailableFeatures(), 0);
> -+
> -   if (getLexer().isNot(AsmToken::EndOfStatement)) {
> -     // Read the first operand.
> -+    if (getLexer().is(AsmToken::Comma)) {
> -+      if (parseBranchModifiers(Operands) != MatchOperand_Success) {
> -+        SMLoc Loc = getLexer().getLoc();
> -+        Parser.eatToEndOfStatement();
> -+        return Error(Loc, "unexpected token");
> -+      }
> -+    }
> -     if (parseOperand(Operands, Name) != MatchOperand_Success) {
> -       SMLoc Loc = getLexer().getLoc();
> -       Parser.eatToEndOfStatement();
> -@@ -482,8 +505,52 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef
> - bool SparcAsmParser::
> - ParseDirective(AsmToken DirectiveID)
> - {
> --  // Ignore all directives for now.
> --  Parser.eatToEndOfStatement();
> -+  StringRef IDVal = DirectiveID.getString();
> -+
> -+  if (IDVal == ".byte")
> -+    return parseDirectiveWord(1, DirectiveID.getLoc());
> -+
> -+  if (IDVal == ".half")
> -+    return parseDirectiveWord(2, DirectiveID.getLoc());
> -+
> -+  if (IDVal == ".word")
> -+    return parseDirectiveWord(4, DirectiveID.getLoc());
> -+
> -+  if (IDVal == ".nword")
> -+    return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
> -+
> -+  if (is64Bit() && IDVal == ".xword")
> -+    return parseDirectiveWord(8, DirectiveID.getLoc());
> -+
> -+  if (IDVal == ".register") {
> -+    // For now, ignore .register directive.
> -+    Parser.eatToEndOfStatement();
> -+    return false;
> -+  }
> -+
> -+  // Let the MC layer to handle other directives.
> -+  return true;
> -+}
> -+
> -+bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
> -+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
> -+    for (;;) {
> -+      const MCExpr *Value;
> -+      if (getParser().parseExpression(Value))
> -+        return true;
> -+
> -+      getParser().getStreamer().EmitValue(Value, Size);
> -+
> -+      if (getLexer().is(AsmToken::EndOfStatement))
> -+        break;
> -+
> -+      // FIXME: Improve diagnostic.
> -+      if (getLexer().isNot(AsmToken::Comma))
> -+        return Error(L, "unexpected token in directive");
> -+      Parser.Lex();
> -+    }
> -+  }
> -+  Parser.Lex();
> -   return false;
> - }
> -
> -@@ -504,7 +571,7 @@ parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &
> -   case AsmToken::Comma:
> -   case AsmToken::RBrac:
> -   case AsmToken::EndOfStatement:
> --    Operands.push_back(SparcOperand::CreateMEMri(BaseReg, 0, S, E));
> -+    Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
> -     return MatchOperand_Success;
> -
> -   case AsmToken:: Plus:
> -@@ -573,11 +640,21 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
> -     Operands.push_back(SparcOperand::CreateToken("]",
> -                                                  Parser.getTok().getLoc()));
> -     Parser.Lex(); // Eat the ]
> -+
> -+    // Parse an optional address-space identifier after the address.
> -+    if (getLexer().is(AsmToken::Integer)) {
> -+      SparcOperand *Op = 0;
> -+      ResTy = parseSparcAsmOperand(Op, false);
> -+      if (ResTy != MatchOperand_Success || !Op)
> -+        return MatchOperand_ParseFail;
> -+      Operands.push_back(Op);
> -+    }
> -     return MatchOperand_Success;
> -   }
> -
> -   SparcOperand *Op = 0;
> --  ResTy = parseSparcAsmOperand(Op);
> -+
> -+  ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
> -   if (ResTy != MatchOperand_Success || !Op)
> -     return MatchOperand_ParseFail;
> -
> -@@ -588,7 +665,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
> - }
> -
> - SparcAsmParser::OperandMatchResultTy
> --SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op)
> -+SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall)
> - {
> -
> -   SMLoc S = Parser.getTok().getLoc();
> -@@ -611,21 +688,21 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
> -       default:
> -         Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
> -         break;
> --      case Sparc::Y:
> --        Op = SparcOperand::CreateToken("%y", S);
> -+      case Sparc::PSR:
> -+        Op = SparcOperand::CreateToken("%psr", S);
> -         break;
> --
> -+      case Sparc::WIM:
> -+        Op = SparcOperand::CreateToken("%wim", S);
> -+        break;
> -+      case Sparc::TBR:
> -+        Op = SparcOperand::CreateToken("%tbr", S);
> -+        break;
> -       case Sparc::ICC:
> -         if (name == "xcc")
> -           Op = SparcOperand::CreateToken("%xcc", S);
> -         else
> -           Op = SparcOperand::CreateToken("%icc", S);
> -         break;
> --
> --      case Sparc::FCC:
> --        assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
> --        Op = SparcOperand::CreateToken("%fcc0", S);
> --        break;
> -       }
> -       break;
> -     }
> -@@ -637,6 +714,7 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
> -
> -   case AsmToken::Minus:
> -   case AsmToken::Integer:
> -+  case AsmToken::LParen:
> -     if (!getParser().parseExpression(EVal, E))
> -       Op = SparcOperand::CreateImm(EVal, S, E);
> -     break;
> -@@ -649,6 +727,10 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
> -
> -       const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
> -                                                   getContext());
> -+      if (isCall &&
> -+          getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
> -+        Res = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_WPLT30, Res,
> -+                                  getContext());
> -       Op = SparcOperand::CreateImm(Res, S, E);
> -     }
> -     break;
> -@@ -657,6 +739,27 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
> -   return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
> - }
> -
> -+SparcAsmParser::OperandMatchResultTy SparcAsmParser::
> -+parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
> -+
> -+  // parse (,a|,pn|,pt)+
> -+
> -+  while (getLexer().is(AsmToken::Comma)) {
> -+
> -+    Parser.Lex(); // Eat the comma
> -+
> -+    if (!getLexer().is(AsmToken::Identifier))
> -+      return MatchOperand_ParseFail;
> -+    StringRef modName = Parser.getTok().getString();
> -+    if (modName == "a" || modName == "pn" || modName == "pt") {
> -+      Operands.push_back(SparcOperand::CreateToken(modName,
> -+                                                   Parser.getTok().getLoc()));
> -+      Parser.Lex(); // eat the identifier.
> -+    }
> -+  }
> -+  return MatchOperand_Success;
> -+}
> -+
> - bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
> -                                        unsigned &RegNo,
> -                                        unsigned &RegKind)
> -@@ -682,20 +785,46 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
> -
> -     if (name.equals("y")) {
> -       RegNo = Sparc::Y;
> --      RegKind = SparcOperand::rk_Y;
> -+      RegKind = SparcOperand::rk_Special;
> -       return true;
> -     }
> -
> -+    if (name.substr(0, 3).equals_lower("asr")
> -+        && !name.substr(3).getAsInteger(10, intVal)
> -+        && intVal > 0 && intVal < 32) {
> -+      RegNo = ASRRegs[intVal];
> -+      RegKind = SparcOperand::rk_Special;
> -+      return true;
> -+    }
> -+
> -     if (name.equals("icc")) {
> -       RegNo = Sparc::ICC;
> --      RegKind = SparcOperand::rk_CCReg;
> -+      RegKind = SparcOperand::rk_Special;
> -       return true;
> -     }
> -
> -+    if (name.equals("psr")) {
> -+      RegNo = Sparc::PSR;
> -+      RegKind = SparcOperand::rk_Special;
> -+      return true;
> -+    }
> -+
> -+    if (name.equals("wim")) {
> -+      RegNo = Sparc::WIM;
> -+      RegKind = SparcOperand::rk_Special;
> -+      return true;
> -+    }
> -+
> -+    if (name.equals("tbr")) {
> -+      RegNo = Sparc::TBR;
> -+      RegKind = SparcOperand::rk_Special;
> -+      return true;
> -+    }
> -+
> -     if (name.equals("xcc")) {
> -       // FIXME:: check 64bit.
> -       RegNo = Sparc::ICC;
> --      RegKind = SparcOperand::rk_CCReg;
> -+      RegKind = SparcOperand::rk_Special;
> -       return true;
> -     }
> -
> -@@ -704,8 +833,8 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
> -         && !name.substr(3).getAsInteger(10, intVal)
> -         && intVal < 4) {
> -       // FIXME: check 64bit and  handle %fcc1 - %fcc3
> --      RegNo = Sparc::FCC;
> --      RegKind = SparcOperand::rk_CCReg;
> -+      RegNo = Sparc::FCC0 + intVal;
> -+      RegKind = SparcOperand::rk_Special;
> -       return true;
> -     }
> -
> -@@ -767,7 +896,32 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
> -   return false;
> - }
> -
> -+static bool hasGOTReference(const MCExpr *Expr) {
> -+  switch (Expr->getKind()) {
> -+  case MCExpr::Target:
> -+    if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
> -+      return hasGOTReference(SE->getSubExpr());
> -+    break;
> -
> -+  case MCExpr::Constant:
> -+    break;
> -+
> -+  case MCExpr::Binary: {
> -+    const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
> -+    return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
> -+  }
> -+
> -+  case MCExpr::SymbolRef: {
> -+    const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
> -+    return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
> -+  }
> -+
> -+  case MCExpr::Unary:
> -+    return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
> -+  }
> -+  return false;
> -+}
> -+
> - bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
> -                                             SMLoc &EndLoc)
> - {
> -@@ -790,6 +944,23 @@ bool SparcAsmParser::matchSparcAsmModifiers(const MCEx
> -   const MCExpr *subExpr;
> -   if (Parser.parseParenExpression(subExpr, EndLoc))
> -     return false;
> -+
> -+  bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
> -+
> -+  switch(VK) {
> -+  default: break;
> -+  case SparcMCExpr::VK_Sparc_LO:
> -+    VK =  (hasGOTReference(subExpr)
> -+           ? SparcMCExpr::VK_Sparc_PC10
> -+           : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
> -+    break;
> -+  case SparcMCExpr::VK_Sparc_HI:
> -+    VK =  (hasGOTReference(subExpr)
> -+           ? SparcMCExpr::VK_Sparc_PC22
> -+           : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
> -+    break;
> -+  }
> -+
> -   EVal = SparcMCExpr::Create(VK, subExpr, getContext());
> -   return true;
> - }
> Index: patches/patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp
> diff -N patches/patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp
> --- patches/patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp 19 May 2015 05:33:39 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,325 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_Disassembler_SparcDisassembler_cpp,v 1.2 2015/05/19 05:33:39 ajacoutot Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> -r237580
> -Add support for the Sparc implementation-defined "ASR" registers.
> -
> -r237581
> -Sparc: Add the "alternate address space" load/store instructions.
> -
> -- Adds support for the asm syntax, which has an immediate integer
> -  "ASI" (address space identifier) appearing after an address, before
> -  a comma.
> -
> -- Adds the various-width load, store, and swap in alternate address
> -  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
> -  sta, swapa)
> -
> ---- lib/Target/Sparc/Disassembler/SparcDisassembler.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/Sparc/Disassembler/SparcDisassembler.cpp Mon May 18 17:43:53 2015
> -@@ -113,6 +113,19 @@ static const unsigned QFPRegDecoderTable[] = {
> -   SP::Q6,  SP::Q14,  ~0U,  ~0U,
> -   SP::Q7,  SP::Q15,  ~0U,  ~0U } ;
> -
> -+static const unsigned FCCRegDecoderTable[] = {
> -+  SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
> -+
> -+static const unsigned ASRRegDecoderTable[] = {
> -+  SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
> -+  SP::ASR4,  SP::ASR5,  SP::ASR6,  SP::ASR7,
> -+  SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
> -+  SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
> -+  SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
> -+  SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
> -+  SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
> -+  SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
> -+
> - static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
> -                                                unsigned RegNo,
> -                                                uint64_t Address,
> -@@ -174,7 +187,52 @@ static DecodeStatus DecodeQFPRegsRegisterClass(MCInst
> -   return MCDisassembler::Success;
> - }
> -
> -+static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
> -+                                               uint64_t Address,
> -+                                               const void *Decoder) {
> -+  if (RegNo > 3)
> -+    return MCDisassembler::Fail;
> -+  Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
> -+  return MCDisassembler::Success;
> -+}
> -
> -+static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
> -+                                               uint64_t Address,
> -+                                               const void *Decoder) {
> -+  if (RegNo > 31)
> -+    return MCDisassembler::Fail;
> -+  Inst.addOperand(MCOperand::CreateReg(ASRRegDecoderTable[RegNo]));
> -+  return MCDisassembler::Success;
> -+}
> -+
> -+
> -+static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                                  const void *Decoder);
> -+static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                                 const void *Decoder);
> -+static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                                  const void *Decoder);
> -+static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                                  const void *Decoder);
> -+static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
> -+                                   uint64_t Address, const void *Decoder);
> -+static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
> -+                                  uint64_t Address, const void *Decoder);
> -+static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
> -+                                   uint64_t Address, const void *Decoder);
> -+static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
> -+                                   uint64_t Address, const void *Decoder);
> -+static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
> -+                               uint64_t Address, const void *Decoder);
> -+static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
> -+                                 uint64_t Address, const void *Decoder);
> -+static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                               const void *Decoder);
> -+static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
> -+                                 const void *Decoder);
> -+static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                               const void *Decoder);
> -+
> - #include "SparcGenDisassemblerTables.inc"
> -
> - /// readInstruction - read four bytes from the MemoryObject
> -@@ -225,4 +283,231 @@ SparcDisassembler::getInstruction(MCInst &instr,
> -   }
> -
> -   return MCDisassembler::Fail;
> -+}
> -+
> -+
> -+typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
> -+                                   const void *Decoder);
> -+
> -+static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
> -+                              const void *Decoder,
> -+                              bool isLoad, DecodeFunc DecodeRD) {
> -+  unsigned rd = fieldFromInstruction(insn, 25, 5);
> -+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
> -+  bool isImm = fieldFromInstruction(insn, 13, 1);
> -+  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
> -+  unsigned asi = fieldFromInstruction(insn, 5, 8);
> -+  unsigned rs2 = 0;
> -+  unsigned simm13 = 0;
> -+  if (isImm)
> -+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
> -+  else
> -+    rs2 = fieldFromInstruction(insn, 0, 5);
> -+
> -+  DecodeStatus status;
> -+  if (isLoad) {
> -+    status = DecodeRD(MI, rd, Address, Decoder);
> -+    if (status != MCDisassembler::Success)
> -+      return status;
> -+  }
> -+
> -+  // Decode rs1.
> -+  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
> -+  if (status != MCDisassembler::Success)
> -+    return status;
> -+
> -+  // Decode imm|rs2.
> -+  if (isImm)
> -+    MI.addOperand(MCOperand::CreateImm(simm13));
> -+  else {
> -+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
> -+    if (status != MCDisassembler::Success)
> -+      return status;
> -+  }
> -+
> -+  if (hasAsi)
> -+    MI.addOperand(MCOperand::CreateImm(asi));
> -+
> -+  if (!isLoad) {
> -+    status = DecodeRD(MI, rd, Address, Decoder);
> -+    if (status != MCDisassembler::Success)
> -+      return status;
> -+  }
> -+  return MCDisassembler::Success;
> -+}
> -+
> -+static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                                  const void *Decoder) {
> -+  return DecodeMem(Inst, insn, Address, Decoder, true,
> -+                   DecodeIntRegsRegisterClass);
> -+}
> -+
> -+static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                                 const void *Decoder) {
> -+  return DecodeMem(Inst, insn, Address, Decoder, true,
> -+                   DecodeFPRegsRegisterClass);
> -+}
> -+
> -+static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                                  const void *Decoder) {
> -+  return DecodeMem(Inst, insn, Address, Decoder, true,
> -+                   DecodeDFPRegsRegisterClass);
> -+}
> -+
> -+static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                                  const void *Decoder) {
> -+  return DecodeMem(Inst, insn, Address, Decoder, true,
> -+                   DecodeQFPRegsRegisterClass);
> -+}
> -+
> -+static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
> -+                                   uint64_t Address, const void *Decoder) {
> -+  return DecodeMem(Inst, insn, Address, Decoder, false,
> -+                   DecodeIntRegsRegisterClass);
> -+}
> -+
> -+static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
> -+                                  const void *Decoder) {
> -+  return DecodeMem(Inst, insn, Address, Decoder, false,
> -+                   DecodeFPRegsRegisterClass);
> -+}
> -+
> -+static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
> -+                                   uint64_t Address, const void *Decoder) {
> -+  return DecodeMem(Inst, insn, Address, Decoder, false,
> -+                   DecodeDFPRegsRegisterClass);
> -+}
> -+
> -+static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
> -+                                   uint64_t Address, const void *Decoder) {
> -+  return DecodeMem(Inst, insn, Address, Decoder, false,
> -+                   DecodeQFPRegsRegisterClass);
> -+}
> -+
> -+static bool tryAddingSymbolicOperand(int64_t Value,  bool isBranch,
> -+                                     uint64_t Address, uint64_t Offset,
> -+                                     uint64_t Width, MCInst &MI,
> -+                                     const void *Decoder) {
> -+  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
> -+  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
> -+                                       Offset, Width);
> -+}
> -+
> -+static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
> -+                               uint64_t Address, const void *Decoder) {
> -+  unsigned tgt = fieldFromInstruction(insn, 0, 30);
> -+  tgt <<= 2;
> -+  if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
> -+                                0, 30, MI, Decoder))
> -+    MI.addOperand(MCOperand::CreateImm(tgt));
> -+  return MCDisassembler::Success;
> -+}
> -+
> -+static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
> -+                                 uint64_t Address, const void *Decoder) {
> -+  unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
> -+  MI.addOperand(MCOperand::CreateImm(tgt));
> -+  return MCDisassembler::Success;
> -+}
> -+
> -+static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
> -+                               const void *Decoder) {
> -+
> -+  unsigned rd = fieldFromInstruction(insn, 25, 5);
> -+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
> -+  unsigned isImm = fieldFromInstruction(insn, 13, 1);
> -+  unsigned rs2 = 0;
> -+  unsigned simm13 = 0;
> -+  if (isImm)
> -+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
> -+  else
> -+    rs2 = fieldFromInstruction(insn, 0, 5);
> -+
> -+  // Decode RD.
> -+  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
> -+  if (status != MCDisassembler::Success)
> -+    return status;
> -+
> -+  // Decode RS1.
> -+  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
> -+  if (status != MCDisassembler::Success)
> -+    return status;
> -+
> -+  // Decode RS1 | SIMM13.
> -+  if (isImm)
> -+    MI.addOperand(MCOperand::CreateImm(simm13));
> -+  else {
> -+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
> -+    if (status != MCDisassembler::Success)
> -+      return status;
> -+  }
> -+  return MCDisassembler::Success;
> -+}
> -+
> -+static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
> -+                                 const void *Decoder) {
> -+
> -+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
> -+  unsigned isImm = fieldFromInstruction(insn, 13, 1);
> -+  unsigned rs2 = 0;
> -+  unsigned simm13 = 0;
> -+  if (isImm)
> -+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
> -+  else
> -+    rs2 = fieldFromInstruction(insn, 0, 5);
> -+
> -+  // Decode RS1.
> -+  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
> -+  if (status != MCDisassembler::Success)
> -+    return status;
> -+
> -+  // Decode RS2 | SIMM13.
> -+  if (isImm)
> -+    MI.addOperand(MCOperand::CreateImm(simm13));
> -+  else {
> -+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
> -+    if (status != MCDisassembler::Success)
> -+      return status;
> -+  }
> -+  return MCDisassembler::Success;
> -+}
> -+
> -+static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
> -+                               const void *Decoder) {
> -+
> -+  unsigned rd = fieldFromInstruction(insn, 25, 5);
> -+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
> -+  unsigned isImm = fieldFromInstruction(insn, 13, 1);
> -+  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
> -+  unsigned asi = fieldFromInstruction(insn, 5, 8);
> -+  unsigned rs2 = 0;
> -+  unsigned simm13 = 0;
> -+  if (isImm)
> -+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
> -+  else
> -+    rs2 = fieldFromInstruction(insn, 0, 5);
> -+
> -+  // Decode RD.
> -+  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
> -+  if (status != MCDisassembler::Success)
> -+    return status;
> -+
> -+  // Decode RS1.
> -+  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
> -+  if (status != MCDisassembler::Success)
> -+    return status;
> -+
> -+  // Decode RS1 | SIMM13.
> -+  if (isImm)
> -+    MI.addOperand(MCOperand::CreateImm(simm13));
> -+  else {
> -+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
> -+    if (status != MCDisassembler::Success)
> -+      return status;
> -+  }
> -+
> -+  if (hasAsi)
> -+    MI.addOperand(MCOperand::CreateImm(asi));
> -+
> -+  return MCDisassembler::Success;
> - }
> Index: patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp
> diff -N patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp
> --- patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,99 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp.orig Sun Jun 15 02:44:25 2014
> -+++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp Sun Jun 15 03:02:07 2014
> -@@ -20,10 +20,22 @@
> - #include "llvm/Support/raw_ostream.h"
> - using namespace llvm;
> -
> -+// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
> -+// namespace. But SPARC backend uses "SP" as its namespace.
> -+namespace llvm {
> -+namespace Sparc {
> -+  using namespace SP;
> -+}
> -+}
> -+
> - #define GET_INSTRUCTION_NAME
> - #define PRINT_ALIAS_INSTR
> - #include "SparcGenAsmWriter.inc"
> -
> -+bool SparcInstPrinter::isV9() const {
> -+  return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
> -+}
> -+
> - void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
> - {
> -   OS << '%' << StringRef(getRegisterName(RegNo)).lower();
> -@@ -49,7 +61,15 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCIn
> -       return false;
> -     switch (MI->getOperand(0).getReg()) {
> -     default: return false;
> --    case SP::G0: // jmp $addr
> -+    case SP::G0: // jmp $addr | ret | retl
> -+      if (MI->getOperand(2).isImm() &&
> -+          MI->getOperand(2).getImm() == 8) {
> -+        switch(MI->getOperand(1).getReg()) {
> -+        default: break;
> -+        case SP::I7: O << "\tret"; return true;
> -+        case SP::O7: O << "\tretl"; return true;
> -+        }
> -+      }
> -       O << "\tjmp "; printMemOperand(MI, 1, O);
> -       return true;
> -     case SP::O7: // call $addr
> -@@ -57,7 +77,29 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCIn
> -       return true;
> -     }
> -   }
> -+  case SP::V9FCMPS:  case SP::V9FCMPD:  case SP::V9FCMPQ:
> -+  case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
> -+    if (isV9()
> -+        || (MI->getNumOperands() != 3)
> -+        || (!MI->getOperand(0).isReg())
> -+        || (MI->getOperand(0).getReg() != SP::FCC0))
> -+      return false;
> -+    // if V8, skip printing %fcc0.
> -+    switch(MI->getOpcode()) {
> -+    default:
> -+    case SP::V9FCMPS:  O << "\tfcmps "; break;
> -+    case SP::V9FCMPD:  O << "\tfcmpd "; break;
> -+    case SP::V9FCMPQ:  O << "\tfcmpq "; break;
> -+    case SP::V9FCMPES: O << "\tfcmpes "; break;
> -+    case SP::V9FCMPED: O << "\tfcmped "; break;
> -+    case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
> -+    }
> -+    printOperand(MI, 1, O);
> -+    O << ", ";
> -+    printOperand(MI, 2, O);
> -+    return true;
> -   }
> -+  }
> - }
> -
> - void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
> -@@ -109,11 +151,17 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI
> -   switch (MI->getOpcode()) {
> -   default: break;
> -   case SP::FBCOND:
> --  case SP::MOVFCCrr:
> --  case SP::MOVFCCri:
> --  case SP::FMOVS_FCC:
> --  case SP::FMOVD_FCC:
> --  case SP::FMOVQ_FCC:  // Make sure CC is a fp conditional flag.
> -+  case SP::FBCONDA:
> -+  case SP::BPFCC:
> -+  case SP::BPFCCA:
> -+  case SP::BPFCCNT:
> -+  case SP::BPFCCANT:
> -+  case SP::MOVFCCrr:  case SP::V9MOVFCCrr:
> -+  case SP::MOVFCCri:  case SP::V9MOVFCCri:
> -+  case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
> -+  case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
> -+  case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
> -+    // Make sure CC is a fp conditional flag.
> -     CC = (CC < 16) ? (CC + 16) : CC;
> -     break;
> -   }
> Index: patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h
> diff -N patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h
> --- patches/patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,34 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_InstPrinter_SparcInstPrinter_h,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/InstPrinter/SparcInstPrinter.h.orig Sun Jun 15 02:48:05 2014
> -+++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.h Sun Jun 15 03:02:09 2014
> -@@ -15,21 +15,25 @@
> - #define SparcINSTPRINTER_H
> -
> - #include "llvm/MC/MCInstPrinter.h"
> -+#include "llvm/MC/MCSubtargetInfo.h"
> -
> - namespace llvm {
> -
> - class MCOperand;
> -
> - class SparcInstPrinter : public MCInstPrinter {
> -+  const MCSubtargetInfo &STI;
> - public:
> -  SparcInstPrinter(const MCAsmInfo &MAI,
> -                   const MCInstrInfo &MII,
> --                  const MCRegisterInfo &MRI)
> --   : MCInstPrinter(MAI, MII, MRI) {}
> -+                  const MCRegisterInfo &MRI,
> -+                  const MCSubtargetInfo &sti)
> -+   : MCInstPrinter(MAI, MII, MRI), STI(sti) {}
> -
> -   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
> -   virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
> -   bool printSparcAliasInstr(const MCInst *MI, raw_ostream &OS);
> -+  bool isV9() const;
> -
> -   // Autogenerated by tblgen.
> -   void printInstruction(const MCInst *MI, raw_ostream &O);
> Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp
> diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp
> --- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,66 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcAsmBackend_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp.orig Sun Jun 15 02:50:32 2014
> -+++ lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp Sun Jun 15 03:01:21 2014
> -@@ -11,8 +11,10 @@
> - #include "MCTargetDesc/SparcFixupKinds.h"
> - #include "MCTargetDesc/SparcMCTargetDesc.h"
> - #include "llvm/MC/MCELFObjectWriter.h"
> -+#include "llvm/MC/MCExpr.h"
> - #include "llvm/MC/MCFixupKindInfo.h"
> - #include "llvm/MC/MCObjectWriter.h"
> -+#include "llvm/MC/MCValue.h"
> - #include "llvm/Support/TargetRegistry.h"
> -
> - using namespace llvm;
> -@@ -37,6 +39,12 @@ static unsigned adjustFixupValue(unsigned Kind, uint64
> -   case Sparc::fixup_sparc_br19:
> -     return (Value >> 2) & 0x7ffff;
> -
> -+  case Sparc::fixup_sparc_br16_2:
> -+    return (Value >> 2) & 0xc000;
> -+
> -+  case Sparc::fixup_sparc_br16_14:
> -+    return (Value >> 2) & 0x3fff;
> -+
> -   case Sparc::fixup_sparc_pc22:
> -   case Sparc::fixup_sparc_got22:
> -   case Sparc::fixup_sparc_tls_gd_hi22:
> -@@ -104,6 +112,8 @@ namespace {
> -         { "fixup_sparc_call30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
> -         { "fixup_sparc_br22",      10,     22,  MCFixupKindInfo::FKF_IsPCRel },
> -         { "fixup_sparc_br19",      13,     19,  MCFixupKindInfo::FKF_IsPCRel },
> -+        { "fixup_sparc_br16_2",    10,      2,  MCFixupKindInfo::FKF_IsPCRel },
> -+        { "fixup_sparc_br16_14",   18,     14,  MCFixupKindInfo::FKF_IsPCRel },
> -         { "fixup_sparc_hi22",      10,     22,  0 },
> -         { "fixup_sparc_lo10",      22,     10,  0 },
> -         { "fixup_sparc_h44",       10,     22,  0 },
> -@@ -154,6 +164,8 @@ namespace {
> -       switch ((Sparc::Fixups)Fixup.getKind()) {
> -       default: break;
> -       case Sparc::fixup_sparc_wplt30:
> -+        if (Target.getSymA()->getSymbol().isTemporary())
> -+          return;
> -       case Sparc::fixup_sparc_tls_gd_hi22:
> -       case Sparc::fixup_sparc_tls_gd_lo10:
> -       case Sparc::fixup_sparc_tls_gd_add:
> -@@ -196,9 +208,14 @@ namespace {
> -     }
> -
> -     bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
> --      // FIXME: Zero fill for now.
> --      for (uint64_t i = 0; i != Count; ++i)
> --        OW->Write8(0);
> -+      // Cannot emit NOP with size not multiple of 32 bits.
> -+      if (Count % 4 != 0)
> -+        return false;
> -+
> -+      uint64_t NumNops = Count / 4;
> -+      for (uint64_t i = 0; i != NumNops; ++i)
> -+        OW->Write32(0x01000000);
> -+
> -       return true;
> -     }
> -
> Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h
> diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h
> --- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,17 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcFixupKinds_h,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h.orig Sun Jun 15 02:50:50 2014
> -+++ lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h Sun Jun 15 03:01:26 2014
> -@@ -26,6 +26,10 @@ namespace llvm {
> -       /// branches on icc/xcc
> -       fixup_sparc_br19,
> -
> -+      /// fixup_sparc_bpr  - 16-bit fixup for bpr
> -+      fixup_sparc_br16_2,
> -+      fixup_sparc_br16_14,
> -+
> -       /// fixup_sparc_hi22  - 22-bit fixup corresponding to %hi(foo)
> -       /// for sethi
> -       fixup_sparc_hi22,
> Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp
> diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp
> --- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp 11 Feb 2015 00:29:05 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,17 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcMCAsmInfo_cpp,v 1.2 2015/02/11 00:29:05 brad Exp $
> -
> -r225957
> -Use the integrated assembler by default on SPARC.
> -
> ---- lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp Mon Feb  2 11:12:32 2015
> -@@ -43,8 +43,7 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) {
> -   SunStyleELFSectionSwitchSyntax = true;
> -   UsesELFSectionDirectiveForBSS = true;
> -
> --  if (TheTriple.getOS() == llvm::Triple::Solaris)
> --    UseIntegratedAssembler = true;
> -+  UseIntegratedAssembler = true;
> - }
> -
> - const MCExpr*
> Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp
> diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp
> --- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,63 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcMCCodeEmitter_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp.orig Sun Jun 15 02:44:51 2014
> -+++ lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp Sun Jun 15 03:01:21 2014
> -@@ -61,6 +61,12 @@ class SparcMCCodeEmitter : public MCCodeEmitter { (pub
> -   unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
> -                              SmallVectorImpl<MCFixup> &Fixups,
> -                              const MCSubtargetInfo &STI) const;
> -+  unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
> -+                                      SmallVectorImpl<MCFixup> &Fixups,
> -+                                      const MCSubtargetInfo &STI) const;
> -+  unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
> -+                                       SmallVectorImpl<MCFixup> &Fixups,
> -+                                       const MCSubtargetInfo &STI) const;
> -
> - };
> - } // end anonymous namespace
> -@@ -173,13 +179,39 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo
> -   if (MO.isReg() || MO.isImm())
> -     return getMachineOpValue(MI, MO, Fixups, STI);
> -
> --  Sparc::Fixups fixup = Sparc::fixup_sparc_br22;
> --  if (MI.getOpcode() == SP::BPXCC)
> --    fixup = Sparc::fixup_sparc_br19;
> -+  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
> -+                                   (MCFixupKind)Sparc::fixup_sparc_br22));
> -+  return 0;
> -+}
> -
> -+unsigned SparcMCCodeEmitter::
> -+getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
> -+                           SmallVectorImpl<MCFixup> &Fixups,
> -+                           const MCSubtargetInfo &STI) const {
> -+  const MCOperand &MO = MI.getOperand(OpNo);
> -+  if (MO.isReg() || MO.isImm())
> -+    return getMachineOpValue(MI, MO, Fixups, STI);
> -+
> -   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
> --                                   (MCFixupKind)fixup));
> -+                                   (MCFixupKind)Sparc::fixup_sparc_br19));
> -   return 0;
> - }
> -+unsigned SparcMCCodeEmitter::
> -+getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
> -+                           SmallVectorImpl<MCFixup> &Fixups,
> -+                           const MCSubtargetInfo &STI) const {
> -+  const MCOperand &MO = MI.getOperand(OpNo);
> -+  if (MO.isReg() || MO.isImm())
> -+    return getMachineOpValue(MI, MO, Fixups, STI);
> -+
> -+  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
> -+                                   (MCFixupKind)Sparc::fixup_sparc_br16_2));
> -+  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
> -+                                   (MCFixupKind)Sparc::fixup_sparc_br16_14));
> -+
> -+  return 0;
> -+}
> -+
> -+
> -
> - #include "SparcGenMCCodeEmitter.inc"
> Index: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp
> diff -N patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp
> --- patches/patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,25 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_MCTargetDesc_SparcMCTargetDesc_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp.orig Sun Jun 15 02:48:45 2014
> -+++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Sun Jun 15 03:01:21 2014
> -@@ -67,6 +67,9 @@ static MCRegisterInfo *createSparcMCRegisterInfo(Strin
> - static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
> -                                                    StringRef FS) {
> -   MCSubtargetInfo *X = new MCSubtargetInfo();
> -+  Triple TheTriple(TT);
> -+  if (CPU.empty())
> -+    CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8";
> -   InitSparcMCSubtargetInfo(X, TT, CPU, FS);
> -   return X;
> - }
> -@@ -150,7 +153,7 @@ static MCInstPrinter *createSparcMCInstPrinter(const T
> -                                               const MCInstrInfo &MII,
> -                                               const MCRegisterInfo &MRI,
> -                                               const MCSubtargetInfo &STI) {
> --  return new SparcInstPrinter(MAI, MII, MRI);
> -+  return new SparcInstPrinter(MAI, MII, MRI, STI);
> - }
> -
> - extern "C" void LLVMInitializeSparcTargetMC() {
> Index: patches/patch-lib_Target_Sparc_SparcCodeEmitter_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_SparcCodeEmitter_cpp
> diff -N patches/patch-lib_Target_Sparc_SparcCodeEmitter_cpp
> --- patches/patch-lib_Target_Sparc_SparcCodeEmitter_cpp 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,36 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_SparcCodeEmitter_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/SparcCodeEmitter.cpp.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/Sparc/SparcCodeEmitter.cpp Sun Jun 15 04:00:05 2014
> -@@ -76,6 +76,10 @@ class SparcCodeEmitter : public MachineFunctionPass {
> -                                 unsigned) const;
> -   unsigned getBranchTargetOpValue(const MachineInstr &MI,
> -                                   unsigned) const;
> -+  unsigned getBranchPredTargetOpValue(const MachineInstr &MI,
> -+                                      unsigned) const;
> -+  unsigned getBranchOnRegTargetOpValue(const MachineInstr &MI,
> -+                                       unsigned) const;
> -
> -   void emitWord(unsigned Word);
> -
> -@@ -194,6 +198,18 @@ unsigned SparcCodeEmitter::getCallTargetOpValue(const
> -
> - unsigned SparcCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI,
> -                                                   unsigned opIdx) const {
> -+  const MachineOperand MO = MI.getOperand(opIdx);
> -+  return getMachineOpValue(MI, MO);
> -+}
> -+
> -+unsigned SparcCodeEmitter::getBranchPredTargetOpValue(const MachineInstr &MI,
> -+                                                      unsigned opIdx) const {
> -+  const MachineOperand MO = MI.getOperand(opIdx);
> -+  return getMachineOpValue(MI, MO);
> -+}
> -+
> -+unsigned SparcCodeEmitter::getBranchOnRegTargetOpValue(const MachineInstr &MI,
> -+                                                       unsigned opIdx) const {
> -   const MachineOperand MO = MI.getOperand(opIdx);
> -   return getMachineOpValue(MI, MO);
> - }
> Index: patches/patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp
> diff -N patches/patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp
> --- patches/patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp 19 May 2015 05:33:39 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,31 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp,v 1.1 2015/05/19 05:33:39 ajacoutot Exp $
> -
> -r237580
> -Add support for the Sparc implementation-defined "ASR" registers.
> -
> ---- lib/Target/Sparc/SparcISelDAGToDAG.cpp.orig Mon May 18 16:07:47 2015
> -+++ lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon May 18 16:07:50 2015
> -@@ -168,8 +168,10 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
> -     } else {
> -       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
> -     }
> --    TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
> --                                     CurDAG->getRegister(SP::G0, MVT::i32)), 0);
> -+    TopPart = SDValue(CurDAG->getMachineNode(SP::WRASRrr, dl, MVT::i32,
> -+                                 TopPart,
> -+                                 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
> -+    TopPart = CurDAG->getCopyToReg(TopPart, dl, SP::Y, TopPart, SDValue()).getValue(1);
> -
> -     // FIXME: Handle div by immediate.
> -     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
> -@@ -185,7 +187,9 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
> -     SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
> -                                          MulLHS, MulRHS);
> -     // The high part is in the Y register.
> --    return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
> -+    return CurDAG->SelectNodeTo(N, SP::RDASR, MVT::i32,
> -+                                CurDAG->getRegister(SP::Y, MVT::i32),
> -+                                SDValue(Mul, 1));
> -   }
> -   }
> -
> Index: patches/patch-lib_Target_Sparc_SparcInstr64Bit_td
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_SparcInstr64Bit_td
> diff -N patches/patch-lib_Target_Sparc_SparcInstr64Bit_td
> --- patches/patch-lib_Target_Sparc_SparcInstr64Bit_td 19 May 2015 05:33:39 -0000 1.3
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,193 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_SparcInstr64Bit_td,v 1.3 2015/05/19 05:33:39 ajacoutot Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> -r208965
> -Sparc: disable printing on longer "brX,pt" aliases
> -
> -r237581
> -Sparc: Add the "alternate address space" load/store instructions.
> -
> -- Adds support for the asm syntax, which has an immediate integer
> -  "ASI" (address space identifier) appearing after an address, before
> -  a comma.
> -
> -- Adds the various-width load, store, and swap in alternate address
> -  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
> -  sta, swapa)
> -
> ---- lib/Target/Sparc/SparcInstr64Bit.td.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/Sparc/SparcInstr64Bit.td Mon May 18 16:33:33 2015
> -@@ -235,7 +235,8 @@ def UDIVXri : F3_2<2, 0b001101,
> - let Predicates = [Is64Bit] in {
> -
> - // 64-bit loads.
> --defm LDX   : Load<"ldx", 0b001011, load, I64Regs, i64>;
> -+let DecoderMethod = "DecodeLoadInt" in
> -+  defm LDX   : Load<"ldx", 0b001011, load, I64Regs, i64>;
> -
> - let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in
> -   def TLS_LDXrr : F3_1<3, 0b001011,
> -@@ -270,10 +271,12 @@ def : Pat<(i64 (extloadi32 ADDRrr:$addr)),  (LDrr ADDR
> - def : Pat<(i64 (extloadi32 ADDRri:$addr)),  (LDri ADDRri:$addr)>;
> -
> - // Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
> --defm LDSW   : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
> -+let DecoderMethod = "DecodeLoadInt" in
> -+  defm LDSW   : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
> -
> - // 64-bit stores.
> --defm STX    : Store<"stx", 0b001110, store,  I64Regs, i64>;
> -+let DecoderMethod = "DecodeStoreInt" in
> -+  defm STX    : Store<"stx", 0b001110, store,  I64Regs, i64>;
> -
> - // Truncating stores from i64 are identical to the i32 stores.
> - def : Pat<(truncstorei8  i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
> -@@ -294,14 +297,6 @@ def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:
> - // 64-bit Conditionals.
> - //===----------------------------------------------------------------------===//
> -
> --// Conditional branch class on %xcc:
> --class XBranchSP<dag ins, string asmstr, list<dag> pattern>
> --  : F2_3<0b001, 0b10, (outs), ins, asmstr, pattern> {
> --  let isBranch = 1;
> --  let isTerminator = 1;
> --  let hasDelaySlot = 1;
> --}
> --
> - //
> - // Flag-setting instructions like subcc and addcc set both icc and xcc flags.
> - // The icc flags correspond to the 32-bit result, and the xcc are for the
> -@@ -312,14 +307,12 @@ class XBranchSP<dag ins, string asmstr, list<dag> patt
> -
> - let Predicates = [Is64Bit] in {
> -
> --let Uses = [ICC] in
> --def BPXCC : XBranchSP<(ins brtarget:$imm19, CCOp:$cond),
> --                     "b$cond %xcc, $imm19",
> --                     [(SPbrxcc bb:$imm19, imm:$cond)]>;
> -+let Uses = [ICC], cc = 0b10 in
> -+  defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>;
> -
> - // Conditional moves on %xcc.
> - let Uses = [ICC], Constraints = "$f = $rd" in {
> --let cc = 0b110 in {
> -+let intcc = 1, cc = 0b10 in {
> - def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
> -                       (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
> -                       "mov$cond %xcc, $rs2, $rd",
> -@@ -332,7 +325,7 @@ def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
> -                        (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;
> - } // cc
> -
> --let opf_cc = 0b110 in {
> -+let intcc = 1, opf_cc = 0b10 in {
> - def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
> -                       (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
> -                       "fmovs$cond %xcc, $rs2, $rd",
> -@@ -351,6 +344,84 @@ def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs
> - } // opf_cc
> - } // Uses, Constraints
> -
> -+// Branch On integer register with Prediction (BPr).
> -+let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in
> -+multiclass BranchOnReg<bits<3> cond, string OpcStr> {
> -+  def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
> -+             !strconcat(OpcStr, " $rs1, $imm16"), []>;
> -+  def apt  : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
> -+             !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
> -+  def napn  : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
> -+             !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
> -+  def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
> -+             !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
> -+}
> -+
> -+multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
> -+  def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
> -+                  (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
> -+  def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
> -+                  (APT I64Regs:$rs1, bprtarget16:$imm16), 0>;
> -+}
> -+
> -+defm BPZ   : BranchOnReg<0b001, "brz">;
> -+defm BPLEZ : BranchOnReg<0b010, "brlez">;
> -+defm BPLZ  : BranchOnReg<0b011, "brlz">;
> -+defm BPNZ  : BranchOnReg<0b101, "brnz">;
> -+defm BPGZ  : BranchOnReg<0b110, "brgz">;
> -+defm BPGEZ : BranchOnReg<0b111, "brgez">;
> -+
> -+defm : bpr_alias<"brz",   BPZnapt,   BPZapt  >;
> -+defm : bpr_alias<"brlez", BPLEZnapt, BPLEZapt>;
> -+defm : bpr_alias<"brlz",  BPLZnapt,  BPLZapt >;
> -+defm : bpr_alias<"brnz",  BPNZnapt,  BPNZapt >;
> -+defm : bpr_alias<"brgz",  BPGZnapt,  BPGZapt >;
> -+defm : bpr_alias<"brgez", BPGEZnapt, BPGEZapt>;
> -+
> -+// Move integer register on register condition (MOVr).
> -+multiclass MOVR< bits<3> rcond,  string OpcStr> {
> -+  def rr : F4_4r<0b101111, 0b00000, rcond, (outs I64Regs:$rd),
> -+                   (ins I64Regs:$rs1, IntRegs:$rs2),
> -+                   !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
> -+
> -+  def ri : F4_4i<0b101111, rcond, (outs I64Regs:$rd),
> -+                   (ins I64Regs:$rs1, i64imm:$simm10),
> -+                   !strconcat(OpcStr, " $rs1, $simm10, $rd"), []>;
> -+}
> -+
> -+defm MOVRRZ  : MOVR<0b001, "movrz">;
> -+defm MOVRLEZ : MOVR<0b010, "movrlez">;
> -+defm MOVRLZ  : MOVR<0b011, "movrlz">;
> -+defm MOVRNZ  : MOVR<0b101, "movrnz">;
> -+defm MOVRGZ  : MOVR<0b110, "movrgz">;
> -+defm MOVRGEZ : MOVR<0b111, "movrgez">;
> -+
> -+// Move FP register on integer register condition (FMOVr).
> -+multiclass FMOVR<bits<3> rcond, string OpcStr> {
> -+
> -+  def S : F4_4r<0b110101, 0b00101, rcond,
> -+                (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
> -+                !strconcat(!strconcat("fmovrs", OpcStr)," $rs1, $rs2, $rd"),
> -+                []>;
> -+  def D : F4_4r<0b110101, 0b00110, rcond,
> -+                (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
> -+                !strconcat(!strconcat("fmovrd", OpcStr)," $rs1, $rs2, $rd"),
> -+                []>;
> -+  def Q : F4_4r<0b110101, 0b00111, rcond,
> -+                (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
> -+                !strconcat(!strconcat("fmovrq", OpcStr)," $rs1, $rs2, $rd"),
> -+                []>, Requires<[HasHardQuad]>;
> -+}
> -+
> -+let Predicates = [HasV9] in {
> -+  defm FMOVRZ   : FMOVR<0b001, "z">;
> -+  defm FMOVRLEZ : FMOVR<0b010, "lez">;
> -+  defm FMOVRLZ  : FMOVR<0b011, "lz">;
> -+  defm FMOVRNZ  : FMOVR<0b101, "nz">;
> -+  defm FMOVRGZ  : FMOVR<0b110, "gz">;
> -+  defm FMOVRGEZ : FMOVR<0b111, "gez">;
> -+}
> -+
> - //===----------------------------------------------------------------------===//
> - // 64-bit Floating Point Conversions.
> - //===----------------------------------------------------------------------===//
> -@@ -414,8 +485,8 @@ def SETHIXi : F2_1<0b100,
> - }
> -
> - // ATOMICS.
> --let Predicates = [Is64Bit], Constraints = "$swap = $rd" in {
> --  def CASXrr: F3_1_asi<3, 0b111110, 0b10000000,
> -+let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
> -+  def CASXrr: F3_1_asi<3, 0b111110,
> -                 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
> -                                      I64Regs:$swap),
> -                  "casx [$rs1], $rs2, $rd",
> -@@ -470,6 +541,9 @@ def ATOMIC_SWAP_64 : Pseudo<(outs I64Regs:$rd),
> -                             (ins ptr_rc:$addr, I64Regs:$rs2), "",
> -                             [(set i64:$rd,
> -                                   (atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
> -+
> -+let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in
> -+ defm TXCC : TRAP<"%xcc">;
> -
> - // Global addresses, constant pool entries
> - let Predicates = [Is64Bit] in {
> Index: patches/patch-lib_Target_Sparc_SparcInstrAliases_td
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_SparcInstrAliases_td
> diff -N patches/patch-lib_Target_Sparc_SparcInstrAliases_td
> --- patches/patch-lib_Target_Sparc_SparcInstrAliases_td 19 May 2015 05:33:39 -0000 1.4
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,340 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_SparcInstrAliases_td,v 1.4 2015/05/19 05:33:39 ajacoutot Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> -r208966
> -Sparc: disable printing of jmp/call aliases (C++ does it)
> -
> -These aliases are handled entirely in C++ and only having TableGen InstAliases
> -for some of them was confusing LLVM.
> -
> -r236042
> -Sparc: Add alternate aliases for conditional branch instructions.
> -
> ---- lib/Target/Sparc/SparcInstrAliases.td.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/Sparc/SparcInstrAliases.td Mon May 18 19:45:10 2015
> -@@ -13,32 +13,53 @@
> - // Instruction aliases for conditional moves.
> -
> - // mov<cond> <ccreg> rs2, rd
> --multiclass cond_mov_alias<string cond, int condVal, string ccreg,
> -+multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
> -                           Instruction movrr, Instruction movri,
> -                           Instruction fmovs, Instruction fmovd> {
> -
> --  // mov<cond> (%icc|%xcc|%fcc0), rs2, rd
> -+  // mov<cond> (%icc|%xcc), rs2, rd
> -   def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
> -                              ", $rs2, $rd"),
> -                   (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
> -
> --  // mov<cond> (%icc|%xcc|%fcc0), simm11, rd
> -+  // mov<cond> (%icc|%xcc), simm11, rd
> -   def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
> -                              ", $simm11, $rd"),
> -                   (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
> -
> --  // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd
> -+  // fmovs<cond> (%icc|%xcc), $rs2, $rd
> -   def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
> -                              ", $rs2, $rd"),
> -                   (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
> -
> --  // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd
> -+  // fmovd<cond> (%icc|%xcc), $rs2, $rd
> -   def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
> -                              ", $rs2, $rd"),
> -                   (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
> - }
> -
> -+// mov<cond> <ccreg> rs2, rd
> -+multiclass fpcond_mov_alias<string cond, int condVal,
> -+                           Instruction movrr, Instruction movri,
> -+                           Instruction fmovs, Instruction fmovd> {
> -
> -+  // mov<cond> %fcc[0-3], rs2, rd
> -+  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
> -+                  (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
> -+
> -+  // mov<cond> %fcc[0-3], simm11, rd
> -+  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
> -+                  (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
> -+
> -+  // fmovs<cond> %fcc[0-3], $rs2, $rd
> -+  def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
> -+                  (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
> -+
> -+  // fmovd<cond> %fcc[0-3], $rs2, $rd
> -+  def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
> -+                  (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
> -+}
> -+
> - // Instruction aliases for integer conditional branches and moves.
> - multiclass int_cond_alias<string cond, int condVal> {
> -
> -@@ -46,15 +67,64 @@ multiclass int_cond_alias<string cond, int condVal> {
> -   def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
> -                   (BCOND brtarget:$imm, condVal)>;
> -
> -+  // b<cond>,a $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
> -+                  (BCONDA brtarget:$imm, condVal)>;
> -+
> -+  // b<cond> %icc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
> -+                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
> -+
> -+  // b<cond>,pt %icc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
> -+                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
> -+
> -+  // b<cond>,a %icc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
> -+                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
> -+
> -+  // b<cond>,a,pt %icc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
> -+                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
> -+
> -+  // b<cond>,pn %icc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
> -+                  (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
> -+
> -+  // b<cond>,a,pn %icc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
> -+                  (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
> -+
> -   // b<cond> %xcc, $imm
> -   def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
> -                   (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
> -
> --  defm : cond_mov_alias<cond, condVal, " %icc",
> -+  // b<cond>,pt %xcc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
> -+                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
> -+
> -+  // b<cond>,a %xcc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
> -+                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
> -+
> -+  // b<cond>,a,pt %xcc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
> -+                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
> -+
> -+  // b<cond>,pn %xcc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
> -+                  (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
> -+
> -+  // b<cond>,a,pn %xcc, $imm
> -+  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
> -+                  (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
> -+
> -+
> -+  defm : intcond_mov_alias<cond, condVal, " %icc",
> -                             MOVICCrr, MOVICCri,
> -                             FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
> -
> --  defm : cond_mov_alias<cond, condVal, " %xcc",
> -+  defm : intcond_mov_alias<cond, condVal, " %xcc",
> -                             MOVXCCrr, MOVXCCri,
> -                             FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
> -
> -@@ -66,6 +136,59 @@ multiclass int_cond_alias<string cond, int condVal> {
> -                   (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
> -                   Requires<[Is64Bit, HasHardQuad]>;
> -
> -+  // t<cond> %icc, rs1 + rs2
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
> -+                  (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
> -+                  Requires<[HasV9]>;
> -+
> -+  // t<cond> %icc,  rs => t<cond> %icc, G0 + rs
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
> -+                  (TICCrr G0, IntRegs:$rs2, condVal)>,
> -+                  Requires<[HasV9]>;
> -+
> -+  // t<cond> %xcc, rs1 + rs2
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
> -+                  (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
> -+                  Requires<[HasV9]>;
> -+
> -+  // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
> -+                  (TXCCrr G0, IntRegs:$rs2, condVal)>,
> -+                  Requires<[HasV9]>;
> -+
> -+  // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
> -+                  (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
> -+
> -+  // t<cond> rs=> t<cond> %icc,  G0 + rs2
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
> -+                  (TICCrr G0, IntRegs:$rs2, condVal)>;
> -+
> -+  // t<cond> %icc, rs1 + imm
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
> -+                  (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
> -+                  Requires<[HasV9]>;
> -+  // t<cond> %icc, imm => t<cond> %icc, G0 + imm
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
> -+                  (TICCri G0, i32imm:$imm, condVal)>,
> -+                  Requires<[HasV9]>;
> -+  // t<cond> %xcc, rs1 + imm
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
> -+                  (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
> -+                  Requires<[HasV9]>;
> -+  // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
> -+                  (TXCCri G0, i32imm:$imm, condVal)>,
> -+                  Requires<[HasV9]>;
> -+
> -+  // t<cond> rs1 + imm => t<cond> %icc, rs1 + imm
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
> -+                  (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>;
> -+
> -+  // t<cond> imm => t<cond> %icc, G0 + imm
> -+  def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
> -+                  (TICCri G0, i32imm:$imm, condVal)>;
> -+
> - }
> -
> -
> -@@ -76,20 +199,57 @@ multiclass fp_cond_alias<string cond, int condVal> {
> -   def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
> -                   (FBCOND brtarget:$imm, condVal), 0>;
> -
> --  defm : cond_mov_alias<cond, condVal, " %fcc0",
> --                        MOVFCCrr, MOVFCCri,
> --                        FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>;
> -+  // fb<cond>,a $imm
> -+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
> -+                  (FBCONDA brtarget:$imm, condVal), 0>;
> -
> -+  // fb<cond> %fcc0, $imm
> -+  def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
> -+                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
> -+                  Requires<[HasV9]>;
> -+
> -+  // fb<cond>,pt %fcc0, $imm
> -+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
> -+                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
> -+                  Requires<[HasV9]>;
> -+
> -+  // fb<cond>,a %fcc0, $imm
> -+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
> -+                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
> -+                  Requires<[HasV9]>;
> -+
> -+  // fb<cond>,a,pt %fcc0, $imm
> -+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
> -+                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
> -+                   Requires<[HasV9]>;
> -+
> -+  // fb<cond>,pn %fcc0, $imm
> -+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
> -+                  (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
> -+                   Requires<[HasV9]>;
> -+
> -+  // fb<cond>,a,pn %fcc0, $imm
> -+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
> -+                  (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
> -+                  Requires<[HasV9]>;
> -+
> -+  defm : fpcond_mov_alias<cond, condVal,
> -+                          V9MOVFCCrr, V9MOVFCCri,
> -+                          V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
> -+
> -   // fmovq<cond> %fcc0, $rs2, $rd
> --  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"),
> --                  (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
> -+  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
> -+                  (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
> -+                                                          condVal)>,
> -                   Requires<[HasV9, HasHardQuad]>;
> - }
> -
> - defm : int_cond_alias<"a",    0b1000>;
> - defm : int_cond_alias<"n",    0b0000>;
> - defm : int_cond_alias<"ne",   0b1001>;
> -+defm : int_cond_alias<"nz",   0b1001>; // same as ne
> - defm : int_cond_alias<"e",    0b0001>;
> -+defm : int_cond_alias<"z",    0b0001>; // same as e
> - defm : int_cond_alias<"g",    0b1010>;
> - defm : int_cond_alias<"le",   0b0010>;
> - defm : int_cond_alias<"ge",   0b1011>;
> -@@ -97,12 +257,16 @@ defm : int_cond_alias<"l",    0b0011>;
> - defm : int_cond_alias<"gu",   0b1100>;
> - defm : int_cond_alias<"leu",  0b0100>;
> - defm : int_cond_alias<"cc",   0b1101>;
> -+defm : int_cond_alias<"geu",  0b1101>; // same as cc
> - defm : int_cond_alias<"cs",   0b0101>;
> -+defm : int_cond_alias<"lu",   0b0101>; // same as cs
> - defm : int_cond_alias<"pos",  0b1110>;
> - defm : int_cond_alias<"neg",  0b0110>;
> - defm : int_cond_alias<"vc",   0b1111>;
> - defm : int_cond_alias<"vs",   0b0111>;
> -
> -+defm : fp_cond_alias<"a",     0b0000>;
> -+defm : fp_cond_alias<"n",     0b1000>;
> - defm : fp_cond_alias<"u",     0b0111>;
> - defm : fp_cond_alias<"g",     0b0110>;
> - defm : fp_cond_alias<"ug",    0b0101>;
> -@@ -110,7 +274,9 @@ defm : fp_cond_alias<"l",     0b0100>;
> - defm : fp_cond_alias<"ul",    0b0011>;
> - defm : fp_cond_alias<"lg",    0b0010>;
> - defm : fp_cond_alias<"ne",    0b0001>;
> -+defm : fp_cond_alias<"nz",    0b0001>; // same as ne
> - defm : fp_cond_alias<"e",     0b1001>;
> -+defm : fp_cond_alias<"z",     0b1001>; // same as e
> - defm : fp_cond_alias<"ue",    0b1010>;
> - defm : fp_cond_alias<"ge",    0b1011>;
> - defm : fp_cond_alias<"uge",   0b1100>;
> -@@ -118,16 +284,15 @@ defm : fp_cond_alias<"le",    0b1101>;
> - defm : fp_cond_alias<"ule",   0b1110>;
> - defm : fp_cond_alias<"o",     0b1111>;
> -
> --
> - // Instruction aliases for JMPL.
> -
> - // jmp addr -> jmpl addr, %g0
> --def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr)>;
> --def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr)>;
> -+def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
> -+def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
> -
> - // call addr -> jmpl addr, %o7
> --def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>;
> --def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>;
> -+def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
> -+def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
> -
> - // retl -> RETL 8
> - def : InstAlias<"retl", (RETL 8)>;
> -@@ -140,3 +305,27 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0
> -
> - // mov simm13, rd -> or %g0, simm13, rd
> - def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
> -+
> -+// restore -> restore %g0, %g0, %g0
> -+def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
> -+
> -+def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
> -+
> -+def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
> -+def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
> -+
> -+def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
> -+def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
> -+
> -+
> -+def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
> -+def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
> -+def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
> -+                Requires<[HasHardQuad]>;
> -+
> -+def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
> -+def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
> -+                                                     DFPRegs:$rs2)>;
> -+def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
> -+                                                     QFPRegs:$rs2)>,
> -+                Requires<[HasHardQuad]>;
> Index: patches/patch-lib_Target_Sparc_SparcInstrFormats_td
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_SparcInstrFormats_td
> diff -N patches/patch-lib_Target_Sparc_SparcInstrFormats_td
> --- patches/patch-lib_Target_Sparc_SparcInstrFormats_td 19 May 2015 05:33:39 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,225 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_SparcInstrFormats_td,v 1.2 2015/05/19 05:33:39 ajacoutot Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> -r237581
> -Sparc: Add the "alternate address space" load/store instructions.
> -
> -- Adds support for the asm syntax, which has an immediate integer
> -  "ASI" (address space identifier) appearing after an address, before
> -  a comma.
> -
> -- Adds the various-width load, store, and swap in alternate address
> -  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
> -  sta, swapa)
> -
> ---- lib/Target/Sparc/SparcInstrFormats.td.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/Sparc/SparcInstrFormats.td Mon May 18 19:44:39 2015
> -@@ -51,38 +51,51 @@ class F2_1<bits<3> op2Val, dag outs, dag ins, string a
> -   let Inst{29-25} = rd;
> - }
> -
> --class F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr,
> -+class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
> -            list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
> -   bits<4>   cond;
> --  bit       annul = 0;     // currently unused
> --
> -   let op2         = op2Val;
> -
> -   let Inst{29}    = annul;
> -   let Inst{28-25} = cond;
> - }
> -
> --class F2_3<bits<3> op2Val, bits<2> ccVal, dag outs, dag ins, string asmstr,
> --           list<dag> pattern>
> --   : InstSP<outs, ins, asmstr, pattern> {
> --  bit      annul;
> -+class F2_3<bits<3> op2Val, bit annul, bit pred,
> -+           dag outs, dag ins, string asmstr, list<dag> pattern>
> -+      : InstSP<outs, ins, asmstr, pattern> {
> -+  bits<2>  cc;
> -   bits<4>  cond;
> --  bit      pred;
> -   bits<19> imm19;
> -
> -   let op          = 0;    // op = 0
> -
> --  bit annul       = 0;    // currently unused
> --  let pred        = 1;    // default is predict taken
> --
> -   let Inst{29}    = annul;
> -   let Inst{28-25} = cond;
> -   let Inst{24-22} = op2Val;
> --  let Inst{21-20} = ccVal;
> -+  let Inst{21-20} = cc;
> -   let Inst{19}    = pred;
> -   let Inst{18-0}  = imm19;
> - }
> -
> -+class F2_4<bits<3> cond, bit annul, bit pred,
> -+           dag outs, dag ins, string asmstr, list<dag> pattern>
> -+      : InstSP<outs, ins, asmstr, pattern> {
> -+  bits<16> imm16;
> -+  bits<5>  rs1;
> -+
> -+  let op          = 0;    // op = 0
> -+
> -+  let Inst{29}    = annul;
> -+  let Inst{28}    = 0;
> -+  let Inst{27-25} = cond;
> -+  let Inst{24-22} = 0b011;
> -+  let Inst{21-20} = imm16{15-14};
> -+  let Inst{19}    = pred;
> -+  let Inst{18-14} = rs1;
> -+  let Inst{13-0}  = imm16{13-0};
> -+}
> -+
> -+
> - //===----------------------------------------------------------------------===//
> - // Format #3 instruction classes in the Sparc
> - //===----------------------------------------------------------------------===//
> -@@ -100,8 +113,9 @@ class F3<dag outs, dag ins, string asmstr, list<dag> p
> -
> - // Specific F3 classes: SparcV8 manual, page 44
> - //
> --class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins,
> -+class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
> -            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
> -+  bits<8> asi;
> -   bits<5> rs2;
> -
> -   let op         = opVal;
> -@@ -113,8 +127,10 @@ class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8>
> - }
> -
> - class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
> --       list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins,
> --                                                     asmstr, pattern>;
> -+       list<dag> pattern> : F3_1_asi<opVal, op3val, outs, ins,
> -+                                                     asmstr, pattern> {
> -+  let asi = 0;
> -+}
> -
> - class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
> -            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
> -@@ -159,7 +175,6 @@ class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opf
> -
> -   let op         = opVal;
> -   let op3        = op3val;
> --  let rd         = 0;
> -
> -   let Inst{13-5} = opfval;   // fp opcode
> -   let Inst{4-0}  = rs2;
> -@@ -218,44 +233,101 @@ class F4_1<bits<6> op3, dag outs, dag ins,
> -             string asmstr, list<dag> pattern>
> -       : F4<op3, outs, ins, asmstr, pattern> {
> -
> --  bits<3> cc;
> -+  bit    intcc;
> -+  bits<2> cc;
> -   bits<4> cond;
> -   bits<5> rs2;
> -
> -   let Inst{4-0}   = rs2;
> --  let Inst{11}    = cc{0};
> --  let Inst{12}    = cc{1};
> -+  let Inst{12-11} = cc;
> -   let Inst{13}    = 0;
> -   let Inst{17-14} = cond;
> --  let Inst{18}    = cc{2};
> -+  let Inst{18}    = intcc;
> -
> - }
> -
> - class F4_2<bits<6> op3, dag outs, dag ins,
> -             string asmstr, list<dag> pattern>
> -       : F4<op3, outs, ins, asmstr, pattern> {
> --  bits<3>  cc;
> -+  bit      intcc;
> -+  bits<2>  cc;
> -   bits<4>  cond;
> -   bits<11> simm11;
> -
> -   let Inst{10-0}  = simm11;
> --  let Inst{11}    = cc{0};
> --  let Inst{12}    = cc{1};
> -+  let Inst{12-11} = cc;
> -   let Inst{13}    = 1;
> -   let Inst{17-14} = cond;
> --  let Inst{18}    = cc{2};
> -+  let Inst{18}    = intcc;
> - }
> -
> - class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
> -            string asmstr, list<dag> pattern>
> -       : F4<op3, outs, ins, asmstr, pattern> {
> -   bits<4> cond;
> --  bits<3> opf_cc;
> -+  bit     intcc;
> -+  bits<2> opf_cc;
> -   bits<5> rs2;
> -
> -   let Inst{18}     = 0;
> -   let Inst{17-14}  = cond;
> --  let Inst{13-11}  = opf_cc;
> -+  let Inst{13}     = intcc;
> -+  let Inst{12-11}  = opf_cc;
> -   let Inst{10-5}   = opf_low;
> -   let Inst{4-0}    = rs2;
> -+}
> -+
> -+class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins,
> -+            string asmstr, list<dag> pattern>
> -+       : F4<op3, outs, ins, asmstr, pattern> {
> -+  bits <5> rs1;
> -+  bits <5> rs2;
> -+  let Inst{18-14} = rs1;
> -+  let Inst{13}    = 0;  // IsImm
> -+  let Inst{12-10} = rcond;
> -+  let Inst{9-5}   = opf_low;
> -+  let Inst{4-0}   = rs2;
> -+}
> -+
> -+
> -+class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins,
> -+            string asmstr, list<dag> pattern>
> -+       : F4<op3, outs, ins, asmstr, pattern> {
> -+  bits<5> rs1;
> -+  bits<10> simm10;
> -+  let Inst{18-14} = rs1;
> -+  let Inst{13}    = 1;  // IsImm
> -+  let Inst{12-10} = rcond;
> -+  let Inst{9-0}   = simm10;
> -+}
> -+
> -+
> -+class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, string asmstr,
> -+       list<dag> pattern>: F3<outs, ins, asmstr, pattern> {
> -+
> -+   bits<4> cond;
> -+   bits<2> cc;
> -+
> -+   let op = 0b10;
> -+   let rd{4} = 0;
> -+   let rd{3-0} = cond;
> -+   let op3 = op3Val;
> -+   let Inst{13} = isimm;
> -+   let Inst{12-11} = cc;
> -+
> -+}
> -+
> -+class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, string asmstr,
> -+    list<dag> pattern>: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern> {
> -+   bits<5> rs2;
> -+
> -+   let Inst{10-5} = 0;
> -+   let Inst{4-0}  = rs2;
> -+}
> -+class TRAPSPri<bits<6> op3Val, dag outs, dag ins, string asmstr,
> -+    list<dag> pattern>: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern> {
> -+   bits<8> imm;
> -+
> -+   let Inst{10-8} = 0;
> -+   let Inst{7-0}  = imm;
> - }
> Index: patches/patch-lib_Target_Sparc_SparcInstrInfo_td
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_SparcInstrInfo_td
> diff -N patches/patch-lib_Target_Sparc_SparcInstrInfo_td
> --- patches/patch-lib_Target_Sparc_SparcInstrInfo_td 19 May 2015 05:33:39 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,722 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_SparcInstrInfo_td,v 1.2 2015/05/19 05:33:39 ajacoutot Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> -r237580
> -Add support for the Sparc implementation-defined "ASR" registers.
> -
> -r237581
> -Sparc: Add the "alternate address space" load/store instructions.
> -
> -- Adds support for the asm syntax, which has an immediate integer
> -  "ASI" (address space identifier) appearing after an address, before
> -  a comma.
> -
> -- Adds the various-width load, store, and swap in alternate address
> -  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
> -  sta, swapa)
> -
> -r237582
> -Sparc: Support PSR, TBR, WIM read/write instructions.
> -
> ---- lib/Target/Sparc/SparcInstrInfo.td.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/Sparc/SparcInstrInfo.td Mon May 18 18:31:25 2015
> -@@ -29,7 +29,8 @@ def Is64Bit : Predicate<"Subtarget.is64Bit()">;
> -
> - // HasV9 - This predicate is true when the target processor supports V9
> - // instructions.  Note that the machine may be running in 32-bit mode.
> --def HasV9   : Predicate<"Subtarget.isV9()">;
> -+def HasV9   : Predicate<"Subtarget.isV9()">,
> -+              AssemblerPredicate<"FeatureV9">;
> -
> - // HasNoV9 - This predicate is true when the target doesn't have V9
> - // instructions.  Use of this is just a hack for the isel not having proper
> -@@ -37,7 +38,12 @@ def HasV9   : Predicate<"Subtarget.isV9()">;
> - def HasNoV9 : Predicate<"!Subtarget.isV9()">;
> -
> - // HasVIS - This is true when the target processor has VIS extensions.
> --def HasVIS : Predicate<"Subtarget.isVIS()">;
> -+def HasVIS : Predicate<"Subtarget.isVIS()">,
> -+             AssemblerPredicate<"FeatureVIS">;
> -+def HasVIS2 : Predicate<"Subtarget.isVIS2()">,
> -+             AssemblerPredicate<"FeatureVIS2">;
> -+def HasVIS3 : Predicate<"Subtarget.isVIS3()">,
> -+             AssemblerPredicate<"FeatureVIS3">;
> -
> - // HasHardQuad - This is true when the target processor supports quad floating
> - // point instructions.
> -@@ -104,10 +110,23 @@ def brtarget : Operand<OtherVT> {
> -   let EncoderMethod = "getBranchTargetOpValue";
> - }
> -
> -+def bprtarget : Operand<OtherVT> {
> -+  let EncoderMethod = "getBranchPredTargetOpValue";
> -+}
> -+
> -+def bprtarget16 : Operand<OtherVT> {
> -+  let EncoderMethod = "getBranchOnRegTargetOpValue";
> -+}
> -+
> - def calltarget : Operand<i32> {
> -   let EncoderMethod = "getCallTargetOpValue";
> -+  let DecoderMethod = "DecodeCall";
> - }
> -
> -+def simm13Op : Operand<i32> {
> -+  let DecoderMethod = "DecodeSIMM13";
> -+}
> -+
> - // Operand for printing out a condition code.
> - let PrintMethod = "printCCOperand" in
> -   def CCOp : Operand<i32>;
> -@@ -246,7 +265,7 @@ multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
> -                  (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
> -                  !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
> -   def ri  : F3_2<2, Op3Val,
> --                 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
> -+                 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
> -                  !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
> - }
> -
> -@@ -263,6 +282,17 @@ multiclass Load<string OpcStr, bits<6> Op3Val, SDPatte
> -                  [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
> - }
> -
> -+// LoadA multiclass - As above, but also define alternate address space variant
> -+multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
> -+                 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
> -+             Load<OpcStr, Op3Val, OpNode, RC, Ty> {
> -+  // TODO: The LD*Arr instructions are currently asm only; hooking up
> -+  // CodeGen's address spaces to use these is a future task.
> -+  def Arr  : F3_1_asi<3, LoadAOp3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
> -+                !strconcat(OpcStr, "a [$addr] $asi, $dst"),
> -+                []>;
> -+}
> -+
> - // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
> - multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
> -            RegisterClass RC, ValueType Ty> {
> -@@ -276,6 +306,16 @@ multiclass Store<string OpcStr, bits<6> Op3Val, SDPatt
> -                  [(OpNode Ty:$rd, ADDRri:$addr)]>;
> - }
> -
> -+multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
> -+                  SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
> -+             Store<OpcStr, Op3Val, OpNode, RC, Ty> {
> -+  // TODO: The ST*Arr instructions are currently asm only; hooking up
> -+  // CodeGen's address spaces to use these is a future task.
> -+  def Arr  : F3_1_asi<3, StoreAOp3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
> -+                  !strconcat(OpcStr, "a $rd, [$addr] $asi"),
> -+                  []>;
> -+}
> -+
> - //===----------------------------------------------------------------------===//
> - // Instructions
> - //===----------------------------------------------------------------------===//
> -@@ -316,8 +356,8 @@ let isBarrier = 1, isTerminator = 1, rd = 0b1000, rs1
> -   def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
> -
> - let rd = 0 in
> --  def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
> --                  "unimp $val", []>;
> -+  def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
> -+                  "unimp $imm22", []>;
> -
> - // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
> - // instruction selection into a branch sequence.  This has to handle all
> -@@ -344,7 +384,7 @@ let Uses = [ICC], usesCustomInserter = 1 in {
> -             [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
> - }
> -
> --let usesCustomInserter = 1, Uses = [FCC] in {
> -+let usesCustomInserter = 1, Uses = [FCC0] in {
> -
> -   def SELECT_CC_Int_FCC
> -    : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
> -@@ -366,7 +406,8 @@ let usesCustomInserter = 1, Uses = [FCC] in {
> - }
> -
> - // JMPL Instruction.
> --let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
> -+let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
> -+    DecoderMethod = "DecodeJMPL" in {
> -   def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
> -                   "jmpl $addr, $dst", []>;
> -   def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
> -@@ -386,29 +427,47 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
> -                   "jmp %i7+$val", []>;
> - }
> -
> -+let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
> -+     isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
> -+  def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
> -+                       "rett $addr", []>;
> -+  def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
> -+                       "rett $addr", []>;
> -+}
> -+
> - // Section B.1 - Load Integer Instructions, p. 90
> --defm LDSB : Load<"ldsb", 0b001001, sextloadi8,  IntRegs, i32>;
> --defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
> --defm LDUB : Load<"ldub", 0b000001, zextloadi8,  IntRegs, i32>;
> --defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
> --defm LD   : Load<"ld",   0b000000, load,        IntRegs, i32>;
> -+let DecoderMethod = "DecodeLoadInt" in {
> -+  defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8,  IntRegs, i32>;
> -+  defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
> -+  defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8,  IntRegs, i32>;
> -+  defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
> -+  defm LD   : LoadA<"ld",   0b000000, 0b010000, load,        IntRegs, i32>;
> -+}
> -
> - // Section B.2 - Load Floating-point Instructions, p. 92
> --defm LDF   : Load<"ld",  0b100000, load, FPRegs,  f32>;
> --defm LDDF  : Load<"ldd", 0b100011, load, DFPRegs, f64>;
> --defm LDQF  : Load<"ldq", 0b100010, load, QFPRegs, f128>,
> --             Requires<[HasV9, HasHardQuad]>;
> -+let DecoderMethod = "DecodeLoadFP" in
> -+  defm LDF   : Load<"ld",  0b100000, load, FPRegs,  f32>;
> -+let DecoderMethod = "DecodeLoadDFP" in
> -+  defm LDDF  : Load<"ldd", 0b100011, load, DFPRegs, f64>;
> -+let DecoderMethod = "DecodeLoadQFP" in
> -+  defm LDQF  : Load<"ldq", 0b100010, load, QFPRegs, f128>,
> -+               Requires<[HasV9, HasHardQuad]>;
> -
> - // Section B.4 - Store Integer Instructions, p. 95
> --defm STB   : Store<"stb", 0b000101, truncstorei8,  IntRegs, i32>;
> --defm STH   : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
> --defm ST    : Store<"st",  0b000100, store,         IntRegs, i32>;
> -+let DecoderMethod = "DecodeStoreInt" in {
> -+  defm STB   : StoreA<"stb", 0b000101, 0b010101, truncstorei8,  IntRegs, i32>;
> -+  defm STH   : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
> -+  defm ST    : StoreA<"st",  0b000100, 0b010100, store,         IntRegs, i32>;
> -+}
> -
> - // Section B.5 - Store Floating-point Instructions, p. 97
> --defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
> --defm STDF  : Store<"std", 0b100111, store,         DFPRegs, f64>;
> --defm STQF  : Store<"stq", 0b100110, store,         QFPRegs, f128>,
> --             Requires<[HasV9, HasHardQuad]>;
> -+let DecoderMethod = "DecodeStoreFP" in
> -+  defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
> -+let DecoderMethod = "DecodeStoreDFP" in
> -+  defm STDF  : Store<"std", 0b100111, store,         DFPRegs, f64>;
> -+let DecoderMethod = "DecodeStoreQFP" in
> -+  defm STQF  : Store<"stq", 0b100110, store,         QFPRegs, f128>,
> -+               Requires<[HasV9, HasHardQuad]>;
> -
> - // Section B.9 - SETHI Instruction, p. 104
> - def SETHIi: F2_1<0b100,
> -@@ -422,42 +481,51 @@ let rd = 0, imm22 = 0 in
> -   def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
> -
> - // Section B.11 - Logical Instructions, p. 106
> --defm AND    : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
> -+defm AND    : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
> -
> - def ANDNrr  : F3_1<2, 0b000101,
> -                    (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
> -                    "andn $rs1, $rs2, $rd",
> -                    [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
> - def ANDNri  : F3_2<2, 0b000101,
> --                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
> -+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
> -                    "andn $rs1, $simm13, $rd", []>;
> -
> --defm OR     : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
> -+defm OR     : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
> -
> - def ORNrr   : F3_1<2, 0b000110,
> -                    (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
> -                    "orn $rs1, $rs2, $rd",
> -                    [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
> - def ORNri   : F3_2<2, 0b000110,
> --                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
> -+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
> -                    "orn $rs1, $simm13, $rd", []>;
> --defm XOR    : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
> -+defm XOR    : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
> -
> - def XNORrr  : F3_1<2, 0b000111,
> -                    (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
> -                    "xnor $rs1, $rs2, $rd",
> -                    [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
> - def XNORri  : F3_2<2, 0b000111,
> --                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
> -+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
> -                    "xnor $rs1, $simm13, $rd", []>;
> -
> -+let Defs = [ICC] in {
> -+  defm ANDCC  : F3_12np<"andcc",  0b010001>;
> -+  defm ANDNCC : F3_12np<"andncc", 0b010101>;
> -+  defm ORCC   : F3_12np<"orcc",   0b010010>;
> -+  defm ORNCC  : F3_12np<"orncc",  0b010110>;
> -+  defm XORCC  : F3_12np<"xorcc",  0b010011>;
> -+  defm XNORCC : F3_12np<"xnorcc", 0b010111>;
> -+}
> -+
> - // Section B.12 - Shift Instructions, p. 107
> --defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
> --defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
> --defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
> -+defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
> -+defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
> -+defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
> -
> - // Section B.13 - Add Instructions, p. 108
> --defm ADD   : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
> -+defm ADD   : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
> -
> - // "LEA" forms of add (patterns to make tblgen happy)
> - let Predicates = [Is32Bit], isCodeGenOnly = 1 in
> -@@ -467,26 +535,32 @@ let Predicates = [Is32Bit], isCodeGenOnly = 1 in
> -                      [(set iPTR:$dst, ADDRri:$addr)]>;
> -
> - let Defs = [ICC] in
> --  defm ADDCC  : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
> -+  defm ADDCC  : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
> -
> -+let Uses = [ICC] in
> -+  defm ADDC   : F3_12np<"addx", 0b001000>;
> -+
> - let Uses = [ICC], Defs = [ICC] in
> --  defm ADDE  : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
> -+  defm ADDE  : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
> -
> - // Section B.15 - Subtract Instructions, p. 110
> --defm SUB    : F3_12  <"sub"  , 0b000100, sub, IntRegs, i32, i32imm>;
> -+defm SUB    : F3_12  <"sub"  , 0b000100, sub, IntRegs, i32, simm13Op>;
> - let Uses = [ICC], Defs = [ICC] in
> --  defm SUBE   : F3_12  <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
> -+  defm SUBE   : F3_12  <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
> -
> - let Defs = [ICC] in
> --  defm SUBCC  : F3_12  <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
> -+  defm SUBCC  : F3_12  <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
> -
> -+let Uses = [ICC] in
> -+  defm SUBC   : F3_12np <"subx", 0b001100>;
> -+
> - let Defs = [ICC], rd = 0 in {
> -   def CMPrr   : F3_1<2, 0b010100,
> -                      (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
> -                      "cmp $rs1, $rs2",
> -                      [(SPcmpicc i32:$rs1, i32:$rs2)]>;
> -   def CMPri   : F3_2<2, 0b010100,
> --                     (outs), (ins IntRegs:$rs1, i32imm:$simm13),
> -+                     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
> -                      "cmp $rs1, $simm13",
> -                      [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
> - }
> -@@ -494,15 +568,25 @@ let Defs = [ICC], rd = 0 in {
> - // Section B.18 - Multiply Instructions, p. 113
> - let Defs = [Y] in {
> -   defm UMUL : F3_12np<"umul", 0b001010>;
> --  defm SMUL : F3_12  <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
> -+  defm SMUL : F3_12  <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
> - }
> -
> -+let Defs = [Y, ICC] in {
> -+  defm UMULCC : F3_12np<"umulcc", 0b011010>;
> -+  defm SMULCC : F3_12np<"smulcc", 0b011011>;
> -+}
> -+
> - // Section B.19 - Divide Instructions, p. 115
> - let Defs = [Y] in {
> -   defm UDIV : F3_12np<"udiv", 0b001110>;
> -   defm SDIV : F3_12np<"sdiv", 0b001111>;
> - }
> -
> -+let Defs = [Y, ICC] in {
> -+  defm UDIVCC : F3_12np<"udivcc", 0b011110>;
> -+  defm SDIVCC : F3_12np<"sdivcc", 0b011111>;
> -+}
> -+
> - // Section B.20 - SAVE and RESTORE, p. 117
> - defm SAVE    : F3_12np<"save"   , 0b111100>;
> - defm RESTORE : F3_12np<"restore", 0b111101>;
> -@@ -511,7 +595,7 @@ defm RESTORE : F3_12np<"restore", 0b111101>;
> -
> - // unconditional branch class.
> - class BranchAlways<dag ins, string asmstr, list<dag> pattern>
> --  : F2_2<0b010, (outs), ins, asmstr, pattern> {
> -+  : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
> -   let isBranch     = 1;
> -   let isTerminator = 1;
> -   let hasDelaySlot = 1;
> -@@ -521,14 +605,36 @@ class BranchAlways<dag ins, string asmstr, list<dag> p
> - let cond = 8 in
> -   def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
> -
> -+
> -+let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
> -+
> - // conditional branch class:
> - class BranchSP<dag ins, string asmstr, list<dag> pattern>
> -- : F2_2<0b010, (outs), ins, asmstr, pattern> {
> --  let isBranch = 1;
> --  let isTerminator = 1;
> --  let hasDelaySlot = 1;
> -+ : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
> -+
> -+// conditional branch with annul class:
> -+class BranchSPA<dag ins, string asmstr, list<dag> pattern>
> -+ : F2_2<0b010, 1, (outs), ins, asmstr, pattern>;
> -+
> -+// Conditional branch class on %icc|%xcc with predication:
> -+multiclass IPredBranch<string regstr, list<dag> CCPattern> {
> -+  def CC    : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
> -+                  !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
> -+                   CCPattern>;
> -+  def CCA   : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
> -+                  !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
> -+                   []>;
> -+  def CCNT  : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
> -+                   !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
> -+                   []>;
> -+  def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
> -+                   !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
> -+                   []>;
> - }
> -
> -+} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
> -+
> -+
> - // Indirect branch instructions.
> - let isTerminator = 1, isBarrier = 1,  hasDelaySlot = 1, isBranch =1,
> -      isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
> -@@ -542,33 +648,64 @@ let isTerminator = 1, isBarrier = 1,  hasDelaySlot = 1
> -                    [(brind ADDRri:$ptr)]>;
> - }
> -
> --let Uses = [ICC] in
> -+let Uses = [ICC] in {
> -   def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
> -                          "b$cond $imm22",
> -                         [(SPbricc bb:$imm22, imm:$cond)]>;
> -+  def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
> -+                         "b$cond,a $imm22", []>;
> -
> -+  let Predicates = [HasV9], cc = 0b00 in
> -+    defm BPI : IPredBranch<"%icc", []>;
> -+}
> -+
> - // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
> -
> -+let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
> -+
> - // floating-point conditional branch class:
> - class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
> -- : F2_2<0b110, (outs), ins, asmstr, pattern> {
> --  let isBranch = 1;
> --  let isTerminator = 1;
> --  let hasDelaySlot = 1;
> -+ : F2_2<0b110, 0, (outs), ins, asmstr, pattern>;
> -+
> -+// floating-point conditional branch with annul class:
> -+class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
> -+ : F2_2<0b110, 1, (outs), ins, asmstr, pattern>;
> -+
> -+// Conditional branch class on %fcc0-%fcc3 with predication:
> -+multiclass FPredBranch {
> -+  def CC    : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
> -+                                         FCCRegs:$cc),
> -+                  "fb$cond $cc, $imm19", []>;
> -+  def CCA   : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
> -+                                         FCCRegs:$cc),
> -+                  "fb$cond,a $cc, $imm19", []>;
> -+  def CCNT  : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
> -+                                         FCCRegs:$cc),
> -+                  "fb$cond,pn $cc, $imm19", []>;
> -+  def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
> -+                                         FCCRegs:$cc),
> -+                  "fb$cond,a,pn $cc, $imm19", []>;
> - }
> -+} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
> -
> --let Uses = [FCC] in
> -+let Uses = [FCC0] in {
> -   def FBCOND  : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
> -                               "fb$cond $imm22",
> -                               [(SPbrfcc bb:$imm22, imm:$cond)]>;
> -+  def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
> -+                             "fb$cond,a $imm22", []>;
> -+}
> -
> -+let Predicates = [HasV9] in
> -+  defm BPF : FPredBranch;
> -
> -+
> - // Section B.24 - Call and Link Instruction, p. 125
> - // This is the only Format 1 instruction
> - let Uses = [O6],
> -     hasDelaySlot = 1, isCall = 1 in {
> --  def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
> --                    "call $dst", []> {
> -+  def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
> -+                    "call $disp", []> {
> -     bits<30> disp;
> -     let op = 1;
> -     let Inst{29-0} = disp;
> -@@ -588,20 +725,37 @@ let Uses = [O6],
> - }
> -
> - // Section B.28 - Read State Register Instructions
> --let Uses = [Y], rs1 = 0, rs2 = 0 in
> --  def RDY : F3_1<2, 0b101000,
> --                 (outs IntRegs:$dst), (ins),
> --                 "rd %y, $dst", []>;
> -+let rs2 = 0 in
> -+  def RDASR : F3_1<2, 0b101000,
> -+                 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
> -+                 "rd $rs1, $rd", []>;
> -
> --// Section B.29 - Write State Register Instructions
> --let Defs = [Y], rd = 0 in {
> --  def WRYrr : F3_1<2, 0b110000,
> --                   (outs), (ins IntRegs:$b, IntRegs:$c),
> --                   "wr $b, $c, %y", []>;
> --  def WRYri : F3_2<2, 0b110000,
> --                   (outs), (ins IntRegs:$b, i32imm:$c),
> --                   "wr $b, $c, %y", []>;
> -+// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
> -+let Predicates = [HasNoV9] in {
> -+  let rs2 = 0, rs1 = 0, Uses=[PSR] in
> -+    def RDPSR : F3_1<2, 0b101001,
> -+     (outs IntRegs:$rd), (ins),
> -+     "rd %psr, $rd", []>;
> -+
> -+  let rs2 = 0, rs1 = 0, Uses=[WIM] in
> -+    def RDWIM : F3_1<2, 0b101010,
> -+     (outs IntRegs:$rd), (ins),
> -+     "rd %wim, $rd", []>;
> -+
> -+  let rs2 = 0, rs1 = 0, Uses=[TBR] in
> -+    def RDTBR : F3_1<2, 0b101011,
> -+     (outs IntRegs:$rd), (ins),
> -+     "rd %tbr, $rd", []>;
> - }
> -+
> -+// Section B.29 - Write State Register Instructions
> -+def WRASRrr : F3_1<2, 0b110000,
> -+                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
> -+                 "wr $rs1, $rs2, $rd", []>;
> -+def WRASRri : F3_2<2, 0b110000,
> -+                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
> -+                 "wr $rs1, $simm13, $rd", []>;
> -+
> - // Convert Integer to Floating-point Instructions, p. 141
> - def FITOS : F3_3u<2, 0b110100, 0b011000100,
> -                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
> -@@ -617,6 +771,36 @@ def FITOQ : F3_3u<2, 0b110100, 0b011001100,
> -                  [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
> -                  Requires<[HasHardQuad]>;
> -
> -+// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
> -+let Predicates = [HasNoV9] in {
> -+  let Defs = [PSR], rd=0 in {
> -+    def WRPSRrr : F3_1<2, 0b110001,
> -+     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
> -+     "wr $rs1, $rs2, %psr", []>;
> -+    def WRPSRri : F3_2<2, 0b110001,
> -+     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
> -+     "wr $rs1, $simm13, %psr", []>;
> -+  }
> -+
> -+  let Defs = [WIM], rd=0 in {
> -+    def WRWIMrr : F3_1<2, 0b110010,
> -+     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
> -+     "wr $rs1, $rs2, %wim", []>;
> -+    def WRWIMri : F3_2<2, 0b110010,
> -+     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
> -+     "wr $rs1, $simm13, %wim", []>;
> -+  }
> -+
> -+  let Defs = [TBR], rd=0 in {
> -+    def WRTBRrr : F3_1<2, 0b110011,
> -+     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
> -+     "wr $rs1, $rs2, %tbr", []>;
> -+    def WRTBRri : F3_2<2, 0b110011,
> -+     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
> -+     "wr $rs1, $simm13, %tbr", []>;
> -+  }
> -+}
> -+
> - // Convert Floating-point to Integer Instructions, p. 142
> - def FSTOI : F3_3u<2, 0b110100, 0b011010001,
> -                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
> -@@ -771,7 +955,7 @@ def FDIVQ  : F3_3<2, 0b110100, 0b001001111,
> - // This behavior is modeled with a forced noop after the instruction in
> - // DelaySlotFiller.
> -
> --let Defs = [FCC] in {
> -+let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
> -   def FCMPS  : F3_3c<2, 0b110101, 0b001010001,
> -                    (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
> -                    "fcmps $rs1, $rs2",
> -@@ -823,7 +1007,7 @@ let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
> - // V9 Conditional Moves.
> - let Predicates = [HasV9], Constraints = "$f = $rd" in {
> -   // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
> --  let Uses = [ICC], cc = 0b100 in {
> -+  let Uses = [ICC], intcc = 1, cc = 0b00 in {
> -     def MOVICCrr
> -       : F4_1<0b101100, (outs IntRegs:$rd),
> -              (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
> -@@ -838,7 +1022,7 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in
> -                     (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
> -   }
> -
> --  let Uses = [FCC], cc = 0b000 in {
> -+  let Uses = [FCC0], intcc = 0, cc = 0b00 in {
> -     def MOVFCCrr
> -       : F4_1<0b101100, (outs IntRegs:$rd),
> -              (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
> -@@ -852,7 +1036,7 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in
> -                     (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
> -   }
> -
> --  let Uses = [ICC], opf_cc = 0b100 in {
> -+  let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
> -     def FMOVS_ICC
> -       : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
> -              (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
> -@@ -871,7 +1055,7 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in
> -                Requires<[HasHardQuad]>;
> -   }
> -
> --  let Uses = [FCC], opf_cc = 0b000 in {
> -+  let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
> -     def FMOVS_FCC
> -       : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
> -              (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
> -@@ -921,6 +1105,59 @@ let Predicates = [HasV9] in {
> -                    Requires<[HasHardQuad]>;
> - }
> -
> -+// Floating-point compare instruction with %fcc0-%fcc3.
> -+def V9FCMPS  : F3_3c<2, 0b110101, 0b001010001,
> -+               (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
> -+               "fcmps $rd, $rs1, $rs2", []>;
> -+def V9FCMPD  : F3_3c<2, 0b110101, 0b001010010,
> -+                (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                "fcmpd $rd, $rs1, $rs2", []>;
> -+def V9FCMPQ  : F3_3c<2, 0b110101, 0b001010011,
> -+                (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
> -+                "fcmpq $rd, $rs1, $rs2", []>,
> -+                 Requires<[HasHardQuad]>;
> -+
> -+let hasSideEffects = 1 in {
> -+  def V9FCMPES  : F3_3c<2, 0b110101, 0b001010101,
> -+                   (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
> -+                   "fcmpes $rd, $rs1, $rs2", []>;
> -+  def V9FCMPED  : F3_3c<2, 0b110101, 0b001010110,
> -+                   (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                   "fcmped $rd, $rs1, $rs2", []>;
> -+  def V9FCMPEQ  : F3_3c<2, 0b110101, 0b001010111,
> -+                   (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
> -+                   "fcmpeq $rd, $rs1, $rs2", []>,
> -+                   Requires<[HasHardQuad]>;
> -+}
> -+
> -+// Floating point conditional move instrucitons with %fcc0-%fcc3.
> -+let Predicates = [HasV9] in {
> -+  let Constraints = "$f = $rd", intcc = 0 in {
> -+    def V9MOVFCCrr
> -+      : F4_1<0b101100, (outs IntRegs:$rd),
> -+             (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
> -+             "mov$cond $cc, $rs2, $rd", []>;
> -+    def V9MOVFCCri
> -+      : F4_2<0b101100, (outs IntRegs:$rd),
> -+             (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
> -+             "mov$cond $cc, $simm11, $rd", []>;
> -+    def V9FMOVS_FCC
> -+      : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
> -+             (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
> -+             "fmovs$cond $opf_cc, $rs2, $rd", []>;
> -+    def V9FMOVD_FCC
> -+      : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
> -+             (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
> -+             "fmovd$cond $opf_cc, $rs2, $rd", []>;
> -+    def V9FMOVQ_FCC
> -+      : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
> -+             (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
> -+             "fmovq$cond $opf_cc, $rs2, $rd", []>,
> -+             Requires<[HasHardQuad]>;
> -+  } // Constraints = "$f = $rd", ...
> -+} // let Predicates = [hasV9]
> -+
> -+
> - // POPCrr - This does a ctpop of a 64-bit register.  As such, we have to clear
> - // the top 32-bits before using it.  To do this clearing, we use a SRLri X,0.
> - let rs1 = 0 in
> -@@ -935,10 +1172,10 @@ let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0
> -   def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
> -
> - let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
> -- def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
> -+ def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
> -                     "membar $simm13", []>;
> -
> --let Constraints = "$val = $dst" in {
> -+let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
> -   def SWAPrr : F3_1<3, 0b001111,
> -                  (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
> -                  "swap [$addr], $dst",
> -@@ -947,16 +1184,48 @@ let Constraints = "$val = $dst" in {
> -                  (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
> -                  "swap [$addr], $dst",
> -                  [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
> -+  def SWAPArr : F3_1_asi<3, 0b011111,
> -+                 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
> -+                 "swapa [$addr] $asi, $dst",
> -+                 [/*FIXME: pattern?*/]>;
> - }
> -
> --let Predicates = [HasV9], Constraints = "$swap = $rd" in
> --  def CASrr: F3_1_asi<3, 0b111100, 0b10000000,
> -+// TODO: Should add a CASArr variant. In fact, the CAS instruction,
> -+// unlike other instructions, only comes in a form which requires an
> -+// ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the
> -+// default unprivileged ASI for SparcV9.  (Also of note: some modern
> -+// SparcV8 implementations provide CASA as an extension, but require
> -+// the use of SparcV8's default ASI, 0xA ("User Data") instead.)
> -+let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
> -+  def CASrr: F3_1_asi<3, 0b111100,
> -                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
> -                                      IntRegs:$swap),
> -                  "cas [$rs1], $rs2, $rd",
> -                  [(set i32:$rd,
> -                      (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
> -
> -+let Defs = [ICC] in {
> -+defm TADDCC   : F3_12np<"taddcc",   0b100000>;
> -+defm TSUBCC   : F3_12np<"tsubcc",   0b100001>;
> -+
> -+let hasSideEffects = 1 in {
> -+  defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
> -+  defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
> -+}
> -+}
> -+
> -+multiclass TRAP<string regStr> {
> -+  def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
> -+                                       CCOp:$cond),
> -+              !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
> -+  def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
> -+                                      CCOp:$cond),
> -+              !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
> -+}
> -+
> -+let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
> -+  defm TICC : TRAP<"%icc">;
> -+
> - //===----------------------------------------------------------------------===//
> - // Non-Instruction Patterns
> - //===----------------------------------------------------------------------===//
> -@@ -1032,4 +1301,5 @@ def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri
> -
> -
> - include "SparcInstr64Bit.td"
> -+include "SparcInstrVIS.td"
> - include "SparcInstrAliases.td"
> Index: patches/patch-lib_Target_Sparc_SparcInstrVIS_td
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_SparcInstrVIS_td
> diff -N patches/patch-lib_Target_Sparc_SparcInstrVIS_td
> --- patches/patch-lib_Target_Sparc_SparcInstrVIS_td 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,270 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_SparcInstrVIS_td,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/SparcInstrVIS.td.orig Sun Jun 15 02:52:10 2014
> -+++ lib/Target/Sparc/SparcInstrVIS.td Sun Jun 15 02:57:59 2014
> -@@ -0,0 +1,263 @@
> -+//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
> -+//
> -+//                     The LLVM Compiler Infrastructure
> -+//
> -+// This file is distributed under the University of Illinois Open Source
> -+// License. See LICENSE.TXT for details.
> -+//
> -+//===----------------------------------------------------------------------===//
> -+//
> -+// This file contains instruction formats, definitions and patterns needed for
> -+// VIS, VIS II, VIS II instructions on SPARC.
> -+//===----------------------------------------------------------------------===//
> -+
> -+// VIS Instruction Format.
> -+class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
> -+      list<dag> pattern>
> -+      : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
> -+
> -+class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
> -+       : VISInstFormat<opfval,
> -+        (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
> -+        !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
> -+
> -+// VIS Instruction with integer destination register.
> -+class VISInstID<bits<9> opfval, string OpcStr>
> -+       : VISInstFormat<opfval,
> -+        (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+        !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
> -+
> -+// For VIS Instructions with no operand.
> -+let rd = 0, rs1 = 0, rs2 = 0 in
> -+class VISInst0<bits<9> opfval, string asmstr>
> -+       : VISInstFormat<opfval, (outs), (ins), asmstr, []>;
> -+
> -+// For VIS Instructions with only rs1, rd operands.
> -+let rs2 = 0 in
> -+class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
> -+       : VISInstFormat<opfval,
> -+        (outs RC:$rd), (ins RC:$rs1),
> -+        !strconcat(OpcStr, " $rs1, $rd"), []>;
> -+
> -+// For VIS Instructions with only rs2, rd operands.
> -+let rs1 = 0 in
> -+class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
> -+       : VISInstFormat<opfval,
> -+        (outs RC:$rd), (ins RC:$rs2),
> -+        !strconcat(OpcStr, " $rs2, $rd"), []>;
> -+
> -+// For VIS Instructions with only rd operand.
> -+let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
> -+class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
> -+       : VISInstFormat<opfval,
> -+        (outs RC:$rd), (ins RC:$f),
> -+        !strconcat(OpcStr, " $rd"), []>;
> -+
> -+// VIS 1 Instructions
> -+let Predicates = [HasVIS] in {
> -+
> -+def FPADD16     : VISInst<0b001010000, "fpadd16">;
> -+def FPADD16S    : VISInst<0b001010001, "fpadd16s">;
> -+def FPADD32     : VISInst<0b001010010, "fpadd32">;
> -+def FPADD32S    : VISInst<0b001010011, "fpadd32s">;
> -+def FPSUB16     : VISInst<0b001010100, "fpsub16">;
> -+def FPSUB16S    : VISInst<0b001010101, "fpsub16S">;
> -+def FPSUB32     : VISInst<0b001010110, "fpsub32">;
> -+def FPSUB32S    : VISInst<0b001010111, "fpsub32S">;
> -+
> -+def FPACK16     : VISInst2<0b000111011, "fpack16">;
> -+def FPACK32     : VISInst <0b000111010, "fpack32">;
> -+def FPACKFIX    : VISInst2<0b000111101, "fpackfix">;
> -+def FEXPAND     : VISInst2<0b001001101, "fexpand">;
> -+def FPMERGE     : VISInst <0b001001011, "fpmerge">;
> -+
> -+def FMUL8X16    : VISInst<0b00110001, "fmul8x16">;
> -+def FMUL8X16AU  : VISInst<0b00110011, "fmul8x16au">;
> -+def FMUL8X16AL  : VISInst<0b00110101, "fmul8x16al">;
> -+def FMUL8SUX16  : VISInst<0b00110110, "fmul8sux16">;
> -+def FMUL8ULX16  : VISInst<0b00110111, "fmul8ulx16">;
> -+def FMULD8SUX16 : VISInst<0b00111000, "fmuld8sux16">;
> -+def FMULD8ULX16 : VISInst<0b00111001, "fmuld8ulx16">;
> -+
> -+def ALIGNADDR   : VISInst<0b000011000, "alignaddr", I64Regs>;
> -+def ALIGNADDRL  : VISInst<0b000011010, "alignaddrl", I64Regs>;
> -+def FALIGNADATA : VISInst<0b001001000, "faligndata">;
> -+
> -+def FZERO       : VISInstD<0b001100000, "fzero">;
> -+def FZEROS      : VISInstD<0b001100001, "fzeros", FPRegs>;
> -+def FONE        : VISInstD<0b001111110, "fone">;
> -+def FONES       : VISInstD<0b001111111, "fones", FPRegs>;
> -+def FSRC1       : VISInst1<0b001110100, "fsrc1">;
> -+def FSRC1S      : VISInst1<0b001110101, "fsrc1s", FPRegs>;
> -+def FSRC2       : VISInst2<0b001111000, "fsrc2">;
> -+def FSRC2S      : VISInst2<0b001111001, "fsrc2s", FPRegs>;
> -+def FNOT1       : VISInst1<0b001101010, "fnot1">;
> -+def FNOT1S      : VISInst1<0b001101011, "fnot1s", FPRegs>;
> -+def FNOT2       : VISInst2<0b001100110, "fnot2">;
> -+def FNOT2S      : VISInst2<0b001100111, "fnot2s", FPRegs>;
> -+def FOR         : VISInst<0b001111100,  "for">;
> -+def FORS        : VISInst<0b001111101,  "fors",  FPRegs>;
> -+def FNOR        : VISInst<0b001100010,  "fnor">;
> -+def FNORS       : VISInst<0b001100011,  "fnors", FPRegs>;
> -+def FAND        : VISInst<0b001110000,  "fand">;
> -+def FANDS       : VISInst<0b001110001,  "fands", FPRegs>;
> -+def FNAND       : VISInst<0b001101110,  "fnand">;
> -+def FNANDS      : VISInst<0b001101111,  "fnands", FPRegs>;
> -+def FXOR        : VISInst<0b001101100,  "fxor">;
> -+def FXORS       : VISInst<0b001101101,  "fxors", FPRegs>;
> -+def FXNOR       : VISInst<0b001110010,  "fxnor">;
> -+def FXNORS      : VISInst<0b001110011,  "fxnors", FPRegs>;
> -+
> -+def FORNOT1     : VISInst<0b001111010,  "fornot1">;
> -+def FORNOT1S    : VISInst<0b001111011,  "fornot1s",  FPRegs>;
> -+def FORNOT2     : VISInst<0b001110110,  "fornot2">;
> -+def FORNOT2S    : VISInst<0b001110111,  "fornot2s",  FPRegs>;
> -+def FANDNOT1    : VISInst<0b001101000,  "fandnot1">;
> -+def FANDNOT1S   : VISInst<0b001101001,  "fandnot1s", FPRegs>;
> -+def FANDNOT2    : VISInst<0b001100100,  "fandnot2">;
> -+def FANDNOT2S   : VISInst<0b001100101,  "fandnot2s", FPRegs>;
> -+
> -+def FCMPGT16    : VISInstID<0b000101000,  "fcmpgt16">;
> -+def FCMPGT32    : VISInstID<0b000101100,  "fcmpgt32">;
> -+def FCMPLE16    : VISInstID<0b000100000,  "fcmple16">;
> -+def FCMPLE32    : VISInstID<0b000100100,  "fcmple32">;
> -+def FCMPNE16    : VISInstID<0b000100010,  "fcmpne16">;
> -+def FCMPNE32    : VISInstID<0b000100110,  "fcmpne32">;
> -+def FCMPEQ16    : VISInstID<0b000101010,  "fcmpeq16">;
> -+def FCMPEQ32    : VISInstID<0b000101110,  "fcmpeq32">;
> -+
> -+
> -+def EDGE8       : VISInst<0b000000000,  "edge8",   I64Regs>;
> -+def EDGE8L      : VISInst<0b000000010,  "edge8l",  I64Regs>;
> -+def EDGE16      : VISInst<0b000000100,  "edge16",  I64Regs>;
> -+def EDGE16L     : VISInst<0b000000110,  "edge16l", I64Regs>;
> -+def EDGE32      : VISInst<0b000001000,  "edge32",  I64Regs>;
> -+def EDGE32L     : VISInst<0b000001010,  "edge32l", I64Regs>;
> -+
> -+def PDIST       : VISInst<0b00111110, "pdist">;
> -+
> -+def ARRAY8      : VISInst<0b000010000, "array8",  I64Regs>;
> -+def ARRAY16     : VISInst<0b000010010, "array16", I64Regs>;
> -+def ARRAY32     : VISInst<0b000010100, "array32", I64Regs>;
> -+
> -+def SHUTDOWN    : VISInst0<0b010000000, "shutdown">;
> -+
> -+} // Predicates = [HasVIS]
> -+
> -+
> -+// VIS 2 Instructions.
> -+let Predicates = [HasVIS2] in {
> -+
> -+def BMASK     : VISInst<0b000011001, "bmask", I64Regs>;
> -+def BSHUFFLE  : VISInst<0b000011100, "bshuffle">;
> -+
> -+def SIAM      : VISInst0<0b010000001, "siam">;
> -+
> -+def EDGE8N    : VISInst<0b000000001,  "edge8n",   I64Regs>;
> -+def EDGE8LN   : VISInst<0b000000011,  "edge8ln",  I64Regs>;
> -+def EDGE16N   : VISInst<0b000000101,  "edge16n",  I64Regs>;
> -+def EDGE16LN  : VISInst<0b000000111,  "edge16ln", I64Regs>;
> -+def EDGE32N   : VISInst<0b000001001,  "edge32n",  I64Regs>;
> -+def EDGE32LN  : VISInst<0b000001011,  "edge32ln", I64Regs>;
> -+} // Predicates = [HasVIS2]
> -+
> -+
> -+// VIS 3 Instructions.
> -+let Predicates = [HasVIS3] in {
> -+
> -+let Uses = [ICC] in
> -+def ADDXC : VISInst<0b000010001, "addxc", I64Regs>;
> -+
> -+let Defs = [ICC], Uses = [ICC] in
> -+def ADDXCCC : VISInst<0b000010011, "addxccc", I64Regs>;
> -+
> -+let rd = 0, rs1 = 0 in {
> -+def CMASK8  : VISInstFormat<0b000011011, (outs), (ins I64Regs:$rs2),
> -+              "cmask8 $rs2", []>;
> -+def CMASK16  : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2),
> -+              "cmask16 $rs2", []>;
> -+def CMASK32  : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
> -+              "cmask32 $rs2", []>;
> -+
> -+}
> -+
> -+def FCHKSM16 : VISInst<0b01000100, "fchksm16">;
> -+
> -+def FHADDS   : F3_3<0b10, 0b110100, 0b001100001,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fhadds $rs1, $rs2, $rd", []>;
> -+def FHADDD   : F3_3<0b10, 0b110100, 0b001100010,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fhaddd $rs1, $rs2, $rd", []>;
> -+def FHSUBS   : F3_3<0b10, 0b110100, 0b001100101,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fhsubs $rs1, $rs2, $rd", []>;
> -+def FHSUBD   : F3_3<0b10, 0b110100, 0b001100110,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fhsubd $rs1, $rs2, $rd", []>;
> -+def FLCMPS   : VISInstFormat<0b101010001, (outs FCCRegs:$rd),
> -+                     (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                     "flcmps $rd, $rs1, $rs2", []>;
> -+def FLCMPD   : VISInstFormat<0b101010010, (outs FCCRegs:$rd),
> -+                     (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                     "flcmpd $rd, $rs1, $rs2", []>;
> -+
> -+def FMEAN16  : VISInst<0b001000000, "fmean16">;
> -+
> -+def FNADDS   : F3_3<0b10, 0b110100, 0b001010001,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fnadds $rs1, $rs2, $rd", []>;
> -+def FNADDD   : F3_3<0b10, 0b110100, 0b001010010,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fnaddd $rs1, $rs2, $rd", []>;
> -+def FNHADDS  : F3_3<0b10, 0b110100, 0b001110001,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fnhadds $rs1, $rs2, $rd", []>;
> -+def FNHADDD  : F3_3<0b10, 0b110100, 0b001110010,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fnhaddd $rs1, $rs2, $rd", []>;
> -+
> -+def FNMULS   : F3_3<0b10, 0b110100, 0b001011001,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fnhadds $rs1, $rs2, $rd", []>;
> -+def FNMULD   : F3_3<0b10, 0b110100, 0b001011010,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fnhaddd $rs1, $rs2, $rd", []>;
> -+def FNSMULD  : F3_3<0b10, 0b110100, 0b001111001,
> -+                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
> -+                    "fnhadds $rs1, $rs2, $rd", []>;
> -+
> -+def FPADD64   : VISInst<0b001000010, "fpadd64">;
> -+
> -+def FSLL16    : VISInst<0b00100001, "fsll16">;
> -+def FSRL16    : VISInst<0b00100011, "fsrl16">;
> -+def FSLL32    : VISInst<0b00100101, "fsll32">;
> -+def FSRL32    : VISInst<0b00100111, "fsrl32">;
> -+def FSLAS16   : VISInst<0b00101001, "fslas16">;
> -+def FSRA16    : VISInst<0b00101011, "fsra16">;
> -+def FSLAS32   : VISInst<0b00101101, "fslas32">;
> -+def FSRA32    : VISInst<0b00101111, "fsra32">;
> -+
> -+let rs1 = 0 in
> -+def LZCNT     : VISInstFormat<0b000010111, (outs I64Regs:$rd),
> -+                   (ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
> -+
> -+let rs1 = 0 in {
> -+def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
> -+                   (ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;
> -+def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd),
> -+                   (ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>;
> -+def MOVDTOX  : VISInstFormat<0b100010000, (outs I64Regs:$rd),
> -+                   (ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>;
> -+def MOVWTOS  :  VISInstFormat<0b100011001, (outs DFPRegs:$rd),
> -+                   (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
> -+def MOVXTOD  :  VISInstFormat<0b100011000, (outs DFPRegs:$rd),
> -+                   (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
> -+}
> -+
> -+def PDISTN   : VISInst<0b000111111, "pdistn">;
> -+
> -+def UMULXHI  : VISInst<0b000010110, "umulxhi", I64Regs>;
> -+def XMULX    : VISInst<0b100010101, "xmulx",   I64Regs>;
> -+def XMULXHI  : VISInst<0b100010111, "xmulxhi", I64Regs>;
> -+} // Predicates = [IsVIS3]
> Index: patches/patch-lib_Target_Sparc_SparcRegisterInfo_td
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_SparcRegisterInfo_td
> diff -N patches/patch-lib_Target_Sparc_SparcRegisterInfo_td
> --- patches/patch-lib_Target_Sparc_SparcRegisterInfo_td 19 May 2015 05:33:39 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,87 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_SparcRegisterInfo_td,v 1.2 2015/05/19 05:33:39 ajacoutot Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> -r237580
> -Add support for the Sparc implementation-defined "ASR" registers.
> -
> -r237582
> -Sparc: Support PSR, TBR, WIM read/write instructions.
> -
> ---- lib/Target/Sparc/SparcRegisterInfo.td.orig Sun Mar  2 21:57:39 2014
> -+++ lib/Target/Sparc/SparcRegisterInfo.td Mon May 18 18:32:12 2015
> -@@ -16,7 +16,8 @@ class SparcReg<bits<16> Enc, string n> : Register<n> {
> -   let Namespace = "SP";
> - }
> -
> --class SparcCtrlReg<string n>: Register<n> {
> -+class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
> -+  let HWEncoding = Enc;
> -   let Namespace = "SP";
> - }
> -
> -@@ -49,12 +50,50 @@ class Rq<bits<16> Enc, string n, list<Register> subreg
> - }
> -
> - // Control Registers
> --def ICC : SparcCtrlReg<"ICC">; // This represents icc and xcc in 64-bit code.
> --def FCC : SparcCtrlReg<"FCC">;
> -+def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
> -+foreach I = 0-3 in
> -+  def FCC#I : SparcCtrlReg<I, "FCC"#I>;
> -
> - // Y register
> --def Y : SparcCtrlReg<"Y">, DwarfRegNum<[64]>;
> -+def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
> -+// Ancillary state registers (implementation defined)
> -+def ASR1 : SparcCtrlReg<1, "ASR1">;
> -+def ASR2 : SparcCtrlReg<2, "ASR2">;
> -+def ASR3 : SparcCtrlReg<3, "ASR3">;
> -+def ASR4 : SparcCtrlReg<4, "ASR4">;
> -+def ASR5 : SparcCtrlReg<5, "ASR5">;
> -+def ASR6 : SparcCtrlReg<6, "ASR6">;
> -+def ASR7 : SparcCtrlReg<7, "ASR7">;
> -+def ASR8 : SparcCtrlReg<8, "ASR8">;
> -+def ASR9 : SparcCtrlReg<9, "ASR9">;
> -+def ASR10 : SparcCtrlReg<10, "ASR10">;
> -+def ASR11 : SparcCtrlReg<11, "ASR11">;
> -+def ASR12 : SparcCtrlReg<12, "ASR12">;
> -+def ASR13 : SparcCtrlReg<13, "ASR13">;
> -+def ASR14 : SparcCtrlReg<14, "ASR14">;
> -+def ASR15 : SparcCtrlReg<15, "ASR15">;
> -+def ASR16 : SparcCtrlReg<16, "ASR16">;
> -+def ASR17 : SparcCtrlReg<17, "ASR17">;
> -+def ASR18 : SparcCtrlReg<18, "ASR18">;
> -+def ASR19 : SparcCtrlReg<19, "ASR19">;
> -+def ASR20 : SparcCtrlReg<20, "ASR20">;
> -+def ASR21 : SparcCtrlReg<21, "ASR21">;
> -+def ASR22 : SparcCtrlReg<22, "ASR22">;
> -+def ASR23 : SparcCtrlReg<23, "ASR23">;
> -+def ASR24 : SparcCtrlReg<24, "ASR24">;
> -+def ASR25 : SparcCtrlReg<25, "ASR25">;
> -+def ASR26 : SparcCtrlReg<26, "ASR26">;
> -+def ASR27 : SparcCtrlReg<27, "ASR27">;
> -+def ASR28 : SparcCtrlReg<28, "ASR28">;
> -+def ASR29 : SparcCtrlReg<29, "ASR29">;
> -+def ASR30 : SparcCtrlReg<30, "ASR30">;
> -+def ASR31 : SparcCtrlReg<31, "ASR31">;
> -
> -+// Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
> -+def PSR : SparcCtrlReg<0, "PSR">;
> -+def WIM : SparcCtrlReg<0, "WIM">;
> -+def TBR : SparcCtrlReg<0, "TBR">;
> -+
> - // Integer registers
> - def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
> - def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
> -@@ -204,3 +243,10 @@ def FPRegs : RegisterClass<"SP", [f32], 32, (sequence
> - def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
> -
> - def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
> -+
> -+// Floating point control register classes.
> -+def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
> -+
> -+// Ancillary state registers
> -+def ASRRegs : RegisterClass<"SP", [i32], 32,
> -+                            (add Y, (sequence "ASR%u", 1, 31))>;
> Index: patches/patch-lib_Target_Sparc_SparcSubtarget_h
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_SparcSubtarget_h
> diff -N patches/patch-lib_Target_Sparc_SparcSubtarget_h
> --- patches/patch-lib_Target_Sparc_SparcSubtarget_h 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,24 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_SparcSubtarget_h,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/SparcSubtarget.h.orig Sun Jun 15 02:53:17 2014
> -+++ lib/Target/Sparc/SparcSubtarget.h Sun Jun 15 02:58:11 2014
> -@@ -27,7 +27,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
> -   virtual void anchor();
> -   bool IsV9;
> -   bool V8DeprecatedInsts;
> --  bool IsVIS;
> -+  bool IsVIS, IsVIS2, IsVIS3;
> -   bool Is64Bit;
> -   bool HasHardQuad;
> -   bool UsePopc;
> -@@ -38,6 +38,8 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
> -
> -   bool isV9() const { return IsV9; }
> -   bool isVIS() const { return IsVIS; }
> -+  bool isVIS2() const { return IsVIS2; }
> -+  bool isVIS3() const { return IsVIS3; }
> -   bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
> -   bool hasHardQuad() const { return HasHardQuad; }
> -   bool usePopc() const { return UsePopc; }
> Index: patches/patch-lib_Target_Sparc_Sparc_td
> ===================================================================
> RCS file: patches/patch-lib_Target_Sparc_Sparc_td
> diff -N patches/patch-lib_Target_Sparc_Sparc_td
> --- patches/patch-lib_Target_Sparc_Sparc_td 11 Jul 2014 01:05:24 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,43 +0,0 @@
> -$OpenBSD: patch-lib_Target_Sparc_Sparc_td,v 1.1 2014/07/11 01:05:24 brad Exp $
> -
> -Sync up the SPARC backend up to commit r203424.
> -
> ---- lib/Target/Sparc/Sparc.td.orig Sun Jun 15 02:52:51 2014
> -+++ lib/Target/Sparc/Sparc.td Sun Jun 15 02:57:59 2014
> -@@ -29,6 +29,12 @@ def FeatureV8Deprecated
> - def FeatureVIS
> -   : SubtargetFeature<"vis", "IsVIS", "true",
> -                      "Enable UltraSPARC Visual Instruction Set extensions">;
> -+def FeatureVIS2
> -+  : SubtargetFeature<"vis2", "IsVIS2", "true",
> -+                     "Enable Visual Instruction Set extensions II">;
> -+def FeatureVIS3
> -+  : SubtargetFeature<"vis3", "IsVIS3", "true",
> -+                     "Enable Visual Instruction Set extensions III">;
> -
> - def FeatureHardQuad
> -   : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
> -@@ -69,12 +75,17 @@ def : Proc<"sparclite86x",    []>;
> - def : Proc<"sparclet",        []>;
> - def : Proc<"tsc701",          []>;
> - def : Proc<"v9",              [FeatureV9]>;
> --def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated]>;
> --def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated]>;
> --def : Proc<"niagara",         [FeatureV9, FeatureV8Deprecated]>;
> --def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc]>;
> --def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc]>;
> --def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc]>;
> -+def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
> -+def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated, FeatureVIS,
> -+                               FeatureVIS2]>;
> -+def : Proc<"niagara",         [FeatureV9, FeatureV8Deprecated, FeatureVIS,
> -+                               FeatureVIS2]>;
> -+def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc,
> -+                               FeatureVIS, FeatureVIS2]>;
> -+def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc,
> -+                               FeatureVIS, FeatureVIS2]>;
> -+def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
> -+                               FeatureVIS, FeatureVIS2, FeatureVIS3]>;
> -
> -
> - //===----------------------------------------------------------------------===//
> Index: patches/patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp
> diff -N patches/patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp
> --- patches/patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp 6 Jan 2015 00:58:02 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,20 +0,0 @@
> -$OpenBSD: patch-lib_Target_X86_MCTargetDesc_X86MCAsmInfo_cpp,v 1.2 2015/01/06 00:58:02 brad Exp $
> -
> -r225227
> -Remove X86 .quad workaround for buggy GNU assembler on OpenBSD / Bitrig.
> -
> ---- lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp.orig Fri Oct 17 03:18:59 2014
> -+++ lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp Fri Oct 17 03:38:34 2014
> -@@ -111,12 +111,6 @@ X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
> -   // Exceptions handling
> -   ExceptionsType = ExceptionHandling::DwarfCFI;
> -
> --  // OpenBSD and Bitrig have buggy support for .quad in 32-bit mode, just split
> --  // into two .words.
> --  if ((T.getOS() == Triple::OpenBSD || T.getOS() == Triple::Bitrig) &&
> --       T.getArch() == Triple::x86)
> --    Data64bitsDirective = 0;
> --
> -   // Always enable the integrated assembler by default.
> -   // Clang also enabled it when the OS is Solaris but that is redundant here.
> -   UseIntegratedAssembler = true;
> Index: patches/patch-lib_Target_X86_X86AsmPrinter_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_X86_X86AsmPrinter_cpp
> diff -N patches/patch-lib_Target_X86_X86AsmPrinter_cpp
> --- patches/patch-lib_Target_X86_X86AsmPrinter_cpp 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,25 +0,0 @@
> -$OpenBSD: patch-lib_Target_X86_X86AsmPrinter_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r205067
> -Fix printing of register operands with q modifier.
> -
> -Emit 32-bit register names instead of 64-bit register names if the target does
> -not have 64-bit general purpose registers.
> -
> ---- lib/Target/X86/X86AsmPrinter.cpp.orig Sun Mar  2 21:57:40 2014
> -+++ lib/Target/X86/X86AsmPrinter.cpp Sat Jun 14 05:56:09 2014
> -@@ -365,9 +365,11 @@ static bool printAsmMRegister(X86AsmPrinter &P, const
> -   case 'k': // Print SImode register
> -     Reg = getX86SubSuperRegister(Reg, MVT::i32);
> -     break;
> --  case 'q': // Print DImode register
> --    // FIXME: gcc will actually print e instead of r for 32-bit.
> --    Reg = getX86SubSuperRegister(Reg, MVT::i64);
> -+  case 'q':
> -+    // Print 64-bit register names if 64-bit integer registers are available.
> -+    // Otherwise, print 32-bit register names.
> -+    MVT::SimpleValueType Ty = P.getSubtarget().is64Bit() ? MVT::i64 : MVT::i32;
> -+    Reg = getX86SubSuperRegister(Reg, Ty);
> -     break;
> -   }
> -
> Index: patches/patch-lib_Target_X86_X86ISelDAGToDAG_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_X86_X86ISelDAGToDAG_cpp
> diff -N patches/patch-lib_Target_X86_X86ISelDAGToDAG_cpp
> --- patches/patch-lib_Target_X86_X86ISelDAGToDAG_cpp 24 Aug 2015 07:45:56 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,60 +0,0 @@
> -$OpenBSD: patch-lib_Target_X86_X86ISelDAGToDAG_cpp,v 1.1 2015/08/24 07:45:56 ajacoutot Exp $
> -
> -r219009
> -[ISel] Keep matching state consistent when folding during X86 address match
> -
> -In the X86 backend, matching an address is initiated by the 'addr' complex
> -pattern and its friends.  During this process we may reassociate and-of-shift
> -into shift-of-and (FoldMaskedShiftToScaledMask) to allow folding of the
> -shift into the scale of the address.
> -
> -However as demonstrated by the testcase, this can trigger CSE of not only the
> -shift and the AND which the code is prepared for but also the underlying load
> -node.  In the testcase this node is sitting in the RecordedNode and MatchScope
> -data structures of the matcher and becomes a deleted node upon CSE.  Returning
> -from the complex pattern function, we try to access it again hitting an assert
> -because the node is no longer a load even though this was checked before.
> -
> -Now obviously changing the DAG this late is bending the rules but I think it
> -makes sense somewhat.  Outside of addresses we prefer and-of-shift because it
> -may lead to smaller immediates (FoldMaskAndShiftToScale is an even better
> -example because it create a non-canonical node).  We currently don't recognize
> -addresses during DAGCombiner where arguably this canonicalization should be
> -performed.  On the other hand, having this in the matcher allows us to cover
> -all the cases where an address can be used in an instruction.
> -
> -I've also talked a little bit to Dan Gohman on llvm-dev who added the RAUW for
> -the new shift node in FoldMaskedShiftToScaledMask.  This RAUW is responsible
> -for initiating the recursive CSE on users
> -(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-September/076903.html) but it
> -is not strictly necessary since the shift is hooked into the visited user.  Of
> -course it's safer to keep the DAG consistent at all times (e.g. for accurate
> -number of uses, etc.).
> -
> -So rather than changing the fundamentals, I've decided to continue along the
> -previous patches and detect the CSE.  This patch installs a very targeted
> -DAGUpdateListener for the duration of a complex-pattern match and updates the
> -matching state accordingly.  (Previous patches used HandleSDNode to detect the
> -CSE but that's not practical here).  The listener is only installed on X86.
> -
> -I tested that there is no measurable overhead due to this while running
> -through the spec2k BC files with llc.  The only thing we pay for is the
> -creation of the listener.  The callback never ever triggers in spec2k since
> -this is a corner case.
> -
> ---- lib/Target/X86/X86ISelDAGToDAG.cpp.orig Tue Aug  4 22:53:05 2015
> -+++ lib/Target/X86/X86ISelDAGToDAG.cpp Tue Aug  4 22:53:59 2015
> -@@ -290,6 +290,13 @@ namespace {
> -     const X86InstrInfo *getInstrInfo() const {
> -       return getTargetMachine().getInstrInfo();
> -     }
> -+
> -+    /// \brief Address-mode matching performs shift-of-and to and-of-shift
> -+    /// reassociation in order to expose more scaled addressing
> -+    /// opportunities.
> -+    bool ComplexPatternFuncMutatesDAG() const {
> -+      return true;
> -+    }
> -   };
> - }
> -
> Index: patches/patch-lib_Target_X86_X86ISelLowering_cpp
> ===================================================================
> RCS file: patches/patch-lib_Target_X86_X86ISelLowering_cpp
> diff -N patches/patch-lib_Target_X86_X86ISelLowering_cpp
> --- patches/patch-lib_Target_X86_X86ISelLowering_cpp 15 Sep 2014 19:24:16 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,74 +0,0 @@
> -$OpenBSD: patch-lib_Target_X86_X86ISelLowering_cpp,v 1.2 2014/09/15 19:24:16 brad Exp $
> -
> -r203581
> -Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)
> -
> -This fixes the bug where we would bitcast the 64-bit floating point result
> -of cmpneqsd to a 64-bit integer even on 32-bit targets.
> -
> -r217410
> -Set trunc store action to Expand for all X86 targets.
> -
> -When compiling without SSE2, isTruncStoreLegal(F64, F32) would return Legal, whereas
> -with SSE2 it would return Expand. And since the Target doesn't seem to actually
> -handle a truncstore for double -> float, it would just output a store of a full
> -double in the space for a float hence overwriting other bits on the stack.
> -
> ---- lib/Target/X86/X86ISelLowering.cpp.orig Sun Mar  2 21:57:40 2014
> -+++ lib/Target/X86/X86ISelLowering.cpp Sun Sep 14 19:09:50 2014
> -@@ -301,6 +301,8 @@ void X86TargetLowering::resetOperationActions() {
> -   setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
> -   setTruncStoreAction(MVT::i16, MVT::i8,  Expand);
> -
> -+  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
> -+
> -   // SETOEQ and SETUNE require checking two conditions.
> -   setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
> -   setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
> -@@ -1012,8 +1014,6 @@ void X86TargetLowering::resetOperationActions() {
> -       AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
> -     }
> -
> --    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
> --
> -     // Custom lower v2i64 and v2f64 selects.
> -     setOperationAction(ISD::LOAD,               MVT::v2f64, Legal);
> -     setOperationAction(ISD::LOAD,               MVT::v2i64, Legal);
> -@@ -18052,7 +18052,6 @@ static SDValue CMPEQCombine(SDNode *N, SelectionDAG &D
> -
> -         if ((cc0 == X86::COND_E  && cc1 == X86::COND_NP) ||
> -             (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
> --          bool is64BitFP = (CMP00.getValueType() == MVT::f64);
> -           // FIXME: need symbolic constants for these magic numbers.
> -           // See X86ATTInstPrinter.cpp:printSSECC().
> -           unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
> -@@ -18067,9 +18066,26 @@ static SDValue CMPEQCombine(SDNode *N, SelectionDAG &D
> -           SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
> -                                               CMP00.getValueType(), CMP00, CMP01,
> -                                               DAG.getConstant(x86cc, MVT::i8));
> --          MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
> --          SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
> --                                              OnesOrZeroesF);
> -+
> -+          bool is64BitFP = (CMP00.getValueType() == MVT::f64);
> -+          MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
> -+
> -+          if (is64BitFP && !Subtarget->is64Bit()) {
> -+            // On a 32-bit target, we cannot bitcast the 64-bit float to a
> -+            // 64-bit integer, since that's not a legal type. Since
> -+            // OnesOrZeroesF is all ones of all zeroes, we don't need all the
> -+            // bits, but can do this little dance to extract the lowest 32 bits
> -+            // and work with those going forward.
> -+            SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
> -+                                           OnesOrZeroesF);
> -+            SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
> -+                                           Vector64);
> -+            OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
> -+                                        Vector32, DAG.getIntPtrConstant(0));
> -+            IntVT = MVT::i32;
> -+          }
> -+
> -+          SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
> -           SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
> -                                       DAG.getConstant(1, IntVT));
> -           SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
> Index: patches/patch-lib_Transforms_Vectorize_LoopVectorize_cpp
> ===================================================================
> RCS file: patches/patch-lib_Transforms_Vectorize_LoopVectorize_cpp
> diff -N patches/patch-lib_Transforms_Vectorize_LoopVectorize_cpp
> --- patches/patch-lib_Transforms_Vectorize_LoopVectorize_cpp 12 Dec 2014 21:51:39 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,22 +0,0 @@
> -$OpenBSD: patch-lib_Transforms_Vectorize_LoopVectorize_cpp,v 1.1 2014/12/12 21:51:39 brad Exp $
> -
> -r223171
> -PR21302. Vectorize only bottom-tested loops.
> -
> ---- lib/Transforms/Vectorize/LoopVectorize.cpp.orig Thu Dec 11 11:41:59 2014
> -+++ lib/Transforms/Vectorize/LoopVectorize.cpp Thu Dec 11 11:45:56 2014
> -@@ -3247,6 +3247,14 @@ bool LoopVectorizationLegality::canVectorize() {
> -   if (!TheLoop->getExitingBlock())
> -     return false;
> -
> -+  // We only handle bottom-tested loops, i.e. loop in which the condition is
> -+  // checked at the end of each iteration. With that we can assume that all
> -+  // instructions in the loop are executed the same number of times.
> -+  if (TheLoop->getExitingBlock() != TheLoop->getLoopLatch()) {
> -+    DEBUG(dbgs() << "LV: loop control flow is not understood by vectorizer\n");
> -+    return false;
> -+  }
> -+
> -   // We need to have a loop header.
> -   DEBUG(dbgs() << "LV: Found a loop: " <<
> -         TheLoop->getHeader()->getName() << '\n');
> Index: patches/patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td
> ===================================================================
> RCS file: patches/patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td
> diff -N patches/patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td
> --- patches/patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td 9 Apr 2015 22:25:02 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,19 +0,0 @@
> -$OpenBSD: patch-tools_clang_include_clang_Basic_DiagnosticDriverKinds_td,v 1.1 2015/04/09 22:25:02 sthen Exp $
> -
> -r211785
> -Implement the -fuse-ld= option.
> -
> -This commit implements the -fuse-ld= option, so that the user
> -can specify -fuse-ld=bfd to use ld.bfd.
> -
> ---- tools/clang/include/clang/Basic/DiagnosticDriverKinds.td.orig Thu Feb 26 07:01:37 2015
> -+++ tools/clang/include/clang/Basic/DiagnosticDriverKinds.td Thu Feb 26 07:02:16 2015
> -@@ -22,6 +22,8 @@ def err_drv_unknown_stdin_type_clang_cl : Error<
> - def err_drv_unknown_language : Error<"language not recognized: '%0'">;
> - def err_drv_invalid_arch_name : Error<
> -   "invalid arch name '%0'">;
> -+def err_drv_invalid_linker_name : Error<
> -+  "invalid linker name in argument '%0'">;
> - def err_drv_invalid_rtlib_name : Error<
> -   "invalid runtime library name in argument '%0'">;
> - def err_drv_unsupported_rtlib_for_platform : Error<
> Index: patches/patch-tools_clang_include_clang_Driver_Options_td
> ===================================================================
> RCS file: /cvs/ports/devel/llvm/patches/patch-tools_clang_include_clang_Driver_Options_td,v
> retrieving revision 1.4
> diff -u -p -r1.4 patch-tools_clang_include_clang_Driver_Options_td
> --- patches/patch-tools_clang_include_clang_Driver_Options_td 9 Apr 2015 22:25:02 -0000 1.4
> +++ patches/patch-tools_clang_include_clang_Driver_Options_td 23 Jan 2016 18:38:51 -0000
> @@ -2,38 +2,14 @@ $OpenBSD: patch-tools_clang_include_clan
>  
>  Alias the command line parameter -p to -pg.
>  
> -r211785
> -Implement the -fuse-ld= option.
> -
> -This commit implements the -fuse-ld= option, so that the user
> -can specify -fuse-ld=bfd to use ld.bfd.
> -
> ---- tools/clang/include/clang/Driver/Options.td.orig Sun Mar  2 22:03:58 2014
> -+++ tools/clang/include/clang/Driver/Options.td Thu Feb 26 07:03:04 2015
> -@@ -253,7 +253,7 @@ def Qn : Flag<["-"], "Qn">;
> - def Qunused_arguments : Flag<["-"], "Qunused-arguments">, Flags<[DriverOption, CoreOption]>,
> -   HelpText<"Don't emit warning for unused driver arguments">;
> - def Q : Flag<["-"], "Q">;
> --def R : Flag<["-"], "R">;
> -+def R : JoinedOrSeparate<["-"], "R">, Flags<[RenderJoined]>;
> - def S : Flag<["-"], "S">, Flags<[DriverOption,CC1Option]>, Group<Action_Group>,
> -   HelpText<"Only run preprocess and compilation steps">;
> - def Tbss : JoinedOrSeparate<["-"], "Tbss">, Group<T_Group>;
> -@@ -1244,7 +1244,7 @@ def private__bundle : Flag<["-"], "private_bundle">;
> - def pthreads : Flag<["-"], "pthreads">;
> +--- tools/clang/include/clang/Driver/Options.td.orig Fri Jul 31 00:47:41 2015
> ++++ tools/clang/include/clang/Driver/Options.td Wed Sep  9 10:44:20 2015
> +@@ -1560,7 +1560,7 @@ def pthreads : Flag<["-"], "pthreads">;
>   def pthread : Flag<["-"], "pthread">, Flags<[CC1Option]>,
>     HelpText<"Support POSIX threads in generated code">;
> + def no_pthread : Flag<["-"], "no-pthread">, Flags<[CC1Option]>;
>  -def p : Flag<["-"], "p">;
>  +def p : Flag<["-"], "p">, Alias<pg>;
>   def pie : Flag<["-"], "pie">;
>   def read__only__relocs : Separate<["-"], "read_only_relocs">;
>   def remap : Flag<["-"], "remap">;
> -@@ -1495,7 +1495,7 @@ def fprofile_dir : Joined<["-"], "fprofile-dir=">, Gro
> -
> - defm profile_use : BooleanFFlag<"profile-use">, Group<clang_ignored_f_Group>;
> - def fprofile_use_EQ : Joined<["-"], "fprofile-use=">, Group<clang_ignored_f_Group>;
> --def fuse_ld_EQ : Joined<["-"], "fuse-ld=">, Group<clang_ignored_f_Group>;
> -+def fuse_ld_EQ : Joined<["-"], "fuse-ld=">, Group<f_Group>;
> -
> - defm align_functions : BooleanFFlag<"align-functions">, Group<clang_ignored_f_Group>;
> - def falign_functions_EQ : Joined<["-"], "falign-functions=">, Group<clang_ignored_f_Group>;
> Index: patches/patch-tools_clang_include_clang_Driver_ToolChain_h
> ===================================================================
> RCS file: patches/patch-tools_clang_include_clang_Driver_ToolChain_h
> diff -N patches/patch-tools_clang_include_clang_Driver_ToolChain_h
> --- patches/patch-tools_clang_include_clang_Driver_ToolChain_h 9 Apr 2015 22:25:02 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,21 +0,0 @@
> -$OpenBSD: patch-tools_clang_include_clang_Driver_ToolChain_h,v 1.1 2015/04/09 22:25:02 sthen Exp $
> -
> -r211785
> -Implement the -fuse-ld= option.
> -
> -This commit implements the -fuse-ld= option, so that the user
> -can specify -fuse-ld=bfd to use ld.bfd.
> -
> ---- tools/clang/include/clang/Driver/ToolChain.h.orig Thu Feb 26 07:03:30 2015
> -+++ tools/clang/include/clang/Driver/ToolChain.h Thu Feb 26 07:03:53 2015
> -@@ -158,6 +158,10 @@ class ToolChain { (public)
> -   std::string GetFilePath(const char *Name) const;
> -   std::string GetProgramPath(const char *Name) const;
> -
> -+  /// Returns the linker path, respecting the -fuse-ld= argument to determine
> -+  /// the linker suffix or name.
> -+  std::string GetLinkerPath() const;
> -+
> -   /// \brief Dispatch to the specific toolchain for verbose printing.
> -   ///
> -   /// This is used when handling the verbose option to print detailed,
> Index: patches/patch-tools_clang_lib_AST_ASTDumper_cpp
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_AST_ASTDumper_cpp
> diff -N patches/patch-tools_clang_lib_AST_ASTDumper_cpp
> --- patches/patch-tools_clang_lib_AST_ASTDumper_cpp 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,42 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_AST_ASTDumper_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r203050
> -Change the color of comment nodes from bright yellow to blue.  Bright yellow on
> -a white background is difficult to read.  Also include a chart showing which
> -colors are used by which elements in the AST dump.
> -
> ---- tools/clang/lib/AST/ASTDumper.cpp.orig Sun Mar  2 22:03:41 2014
> -+++ tools/clang/lib/AST/ASTDumper.cpp Sat Jun 14 03:54:11 2014
> -@@ -32,12 +32,23 @@ using namespace clang::comments;
> -
> - namespace  {
> -   // Colors used for various parts of the AST dump
> -+  // Do not use bold yellow for any text.  It is hard to read on white screens.
> -
> -   struct TerminalColor {
> -     raw_ostream::Colors Color;
> -     bool Bold;
> -   };
> -
> -+  // Red           - CastColor
> -+  // Green         - TypeColor
> -+  // Bold Green    - DeclKindNameColor, UndeserializedColor
> -+  // Yellow        - AddressColor, LocationColor
> -+  // Blue          - CommentColor, NullColor, IndentColor
> -+  // Bold Blue     - AttrColor
> -+  // Bold Magenta  - StmtColor
> -+  // Cyan          - ValueKindColor, ObjectKindColor
> -+  // Bold Cyan     - ValueColor, DeclNameColor
> -+
> -   // Decl kind names (VarDecl, FunctionDecl, etc)
> -   static const TerminalColor DeclKindNameColor = { raw_ostream::GREEN, true };
> -   // Attr names (CleanupAttr, GuardedByAttr, etc)
> -@@ -45,7 +56,7 @@ namespace  {
> -   // Statement names (DeclStmt, ImplicitCastExpr, etc)
> -   static const TerminalColor StmtColor = { raw_ostream::MAGENTA, true };
> -   // Comment names (FullComment, ParagraphComment, TextComment, etc)
> --  static const TerminalColor CommentColor = { raw_ostream::YELLOW, true };
> -+  static const TerminalColor CommentColor = { raw_ostream::BLUE, false };
> -
> -   // Type names (int, float, etc, plus user defined types)
> -   static const TerminalColor TypeColor = { raw_ostream::GREEN, false };
> Index: patches/patch-tools_clang_lib_AST_ExprConstant_cpp
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_AST_ExprConstant_cpp
> diff -N patches/patch-tools_clang_lib_AST_ExprConstant_cpp
> --- patches/patch-tools_clang_lib_AST_ExprConstant_cpp 10 Jul 2014 22:46:37 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,57 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_AST_ExprConstant_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
> -
> -r203025
> -PR19010: Make sure we initialize (empty) indirect base class subobjects when
> -evaluating trivial default initialization of a literal class type.
> -
> ---- tools/clang/lib/AST/ExprConstant.cpp.orig Sun Mar  2 22:03:41 2014
> -+++ tools/clang/lib/AST/ExprConstant.cpp Sat Jun 14 03:37:45 2014
> -@@ -5117,16 +5117,15 @@ bool RecordExprEvaluator::VisitCXXConstructExpr(const
> -     if (!Result.isUninit())
> -       return true;
> -
> --    if (ZeroInit)
> --      return ZeroInitialization(E);
> --
> --    const CXXRecordDecl *RD = FD->getParent();
> --    if (RD->isUnion())
> --      Result = APValue((FieldDecl*)0);
> --    else
> --      Result = APValue(APValue::UninitStruct(), RD->getNumBases(),
> --                       std::distance(RD->field_begin(), RD->field_end()));
> --    return true;
> -+    // We can get here in two different ways:
> -+    //  1) We're performing value-initialization, and should zero-initialize
> -+    //     the object, or
> -+    //  2) We're performing default-initialization of an object with a trivial
> -+    //     constexpr default constructor, in which case we should start the
> -+    //     lifetimes of all the base subobjects (there can be no data member
> -+    //     subobjects in this case) per [basic.life]p1.
> -+    // Either way, ZeroInitialization is appropriate.
> -+    return ZeroInitialization(E);
> -   }
> -
> -   const FunctionDecl *Definition = 0;
> -@@ -5606,19 +5605,9 @@ bool ArrayExprEvaluator::VisitCXXConstructExpr(const C
> -     if (HadZeroInit)
> -       return true;
> -
> --    if (ZeroInit) {
> --      ImplicitValueInitExpr VIE(Type);
> --      return EvaluateInPlace(*Value, Info, Subobject, &VIE);
> --    }
> --
> --    const CXXRecordDecl *RD = FD->getParent();
> --    if (RD->isUnion())
> --      *Value = APValue((FieldDecl*)0);
> --    else
> --      *Value =
> --          APValue(APValue::UninitStruct(), RD->getNumBases(),
> --                  std::distance(RD->field_begin(), RD->field_end()));
> --    return true;
> -+    // See RecordExprEvaluator::VisitCXXConstructExpr for explanation.
> -+    ImplicitValueInitExpr VIE(Type);
> -+    return EvaluateInPlace(*Value, Info, Subobject, &VIE);
> -   }
> -
> -   const FunctionDecl *Definition = 0;
> Index: patches/patch-tools_clang_lib_Basic_Targets_cpp
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_Basic_Targets_cpp
> diff -N patches/patch-tools_clang_lib_Basic_Targets_cpp
> --- patches/patch-tools_clang_lib_Basic_Targets_cpp 15 Jun 2015 06:20:48 -0000 1.13
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,91 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_Basic_Targets_cpp,v 1.13 2015/06/15 06:20:48 ajacoutot Exp $
> -
> -r236179
> -Propagate a terrible hack to the sparc target feature handling code
> -by erasing the soft-float target feature if the rest of the front
> -end added it because of defaults or the soft float option.
> -
> -r239046
> -[SPARC] Fix types of size_t, intptr_t, and ptrdiff_t on Linux.
> -
> -They should be 'int' instead of 'long int' everywhere else except
> -NetBSD too, from what I gather in GCC's spec files. So, optimistically
> -changing it for everyone else, too.
> -
> ---- tools/clang/lib/Basic/Targets.cpp.orig Sun Mar  2 22:03:40 2014
> -+++ tools/clang/lib/Basic/Targets.cpp Fri Jun  5 00:55:44 2015
> -@@ -4477,9 +4477,12 @@ class SparcTargetInfo : public TargetInfo { (public)
> -   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
> -                                     DiagnosticsEngine &Diags) {
> -     SoftFloat = false;
> --    for (unsigned i = 0, e = Features.size(); i != e; ++i)
> --      if (Features[i] == "+soft-float")
> --        SoftFloat = true;
> -+    std::vector<std::string>::iterator Feature =
> -+      std::find(Features.begin(), Features.end(), "+soft-float");
> -+    if (Feature != Features.end()) {
> -+      SoftFloat = true;
> -+      Features.erase(Feature);
> -+    }
> -     return true;
> -   }
> -   virtual void getTargetDefines(const LangOptions &Opts,
> -@@ -4579,6 +4582,20 @@ class SparcV8TargetInfo : public SparcTargetInfo {
> - public:
> -   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
> -     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
> -+    // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
> -+    switch (getTriple().getOS()) {
> -+    default:
> -+      SizeType = UnsignedInt;
> -+      IntPtrType = SignedInt;
> -+      PtrDiffType = SignedInt;
> -+      break;
> -+    case llvm::Triple::NetBSD:
> -+    case llvm::Triple::OpenBSD:
> -+      SizeType = UnsignedLong;
> -+      IntPtrType = SignedLong;
> -+      PtrDiffType = SignedLong;
> -+      break;
> -+    }
> -   }
> -
> -   virtual void getTargetDefines(const LangOptions &Opts,
> -@@ -4650,25 +4667,6 @@ class SparcV9TargetInfo : public SparcTargetInfo { (pu
> - } // end anonymous namespace.
> -
> - namespace {
> --class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
> --public:
> --  AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
> --      : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
> --    SizeType = UnsignedInt;
> --    PtrDiffType = SignedInt;
> --  }
> --};
> --class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
> --public:
> --  SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
> --      : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
> --    SizeType = UnsignedInt;
> --    PtrDiffType = SignedInt;
> --  }
> --};
> --} // end anonymous namespace.
> --
> --namespace {
> -   class SystemZTargetInfo : public TargetInfo {
> -     static const char *const GCCRegNames[];
> -
> -@@ -5812,9 +5810,9 @@ static TargetInfo *AllocateTarget(const llvm::Triple &
> -     case llvm::Triple::Linux:
> -       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
> -     case llvm::Triple::AuroraUX:
> --      return new AuroraUXSparcV8TargetInfo(Triple);
> -+      return new AuroraUXTargetInfo<SparcV8TargetInfo>(Triple);
> -     case llvm::Triple::Solaris:
> --      return new SolarisSparcV8TargetInfo(Triple);
> -+      return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
> -     case llvm::Triple::NetBSD:
> -       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
> -     case llvm::Triple::OpenBSD:
> Index: patches/patch-tools_clang_lib_CodeGen_CGCXX_cpp
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_CodeGen_CGCXX_cpp
> diff -N patches/patch-tools_clang_lib_CodeGen_CGCXX_cpp
> --- patches/patch-tools_clang_lib_CodeGen_CGCXX_cpp 18 Apr 2014 21:26:56 -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,24 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_CodeGen_CGCXX_cpp,v 1.2 2014/04/18 21:26:56 brad Exp $
> -
> -r203007
> -Don't produce an alias between destructors with different calling conventions.
> -
> -http://llvm.org/bugs/show_bug.cgi?id=19007
> -https://bugzilla.mozilla.org/show_bug.cgi?id=978423
> -
> ---- tools/clang/lib/CodeGen/CGCXX.cpp.orig Fri Apr  4 23:01:26 2014
> -+++ tools/clang/lib/CodeGen/CGCXX.cpp Fri Apr  4 23:02:50 2014
> -@@ -92,7 +92,13 @@ bool CodeGenModule::TryEmitBaseDestructorAsAlias(const
> -   if (!ClassLayout.getBaseClassOffset(UniqueBase).isZero())
> -     return true;
> -
> -+  // Give up if the calling conventions don't match. We could update the call,
> -+  // but it is probably not worth it.
> -   const CXXDestructorDecl *BaseD = UniqueBase->getDestructor();
> -+  if (BaseD->getType()->getAs<FunctionType>()->getCallConv() !=
> -+      D->getType()->getAs<FunctionType>()->getCallConv())
> -+    return true;
> -+
> -   return TryEmitDefinitionAsAlias(GlobalDecl(D, Dtor_Base),
> -                                   GlobalDecl(BaseD, Dtor_Base),
> -                                   false);
> Index: patches/patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp
> diff -N patches/patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp
> --- patches/patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp 12 Sep 2014 12:39:47 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,17 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_CodeGen_CGDebugInfo_cpp,v 1.1 2014/09/12 12:39:47 brad Exp $
> -
> -r205331
> -Debug info: fix a crash when emitting IndirectFieldDecls, which were previously
> -not handled at all.
> -
> ---- tools/clang/lib/CodeGen/CGDebugInfo.cpp.orig Thu Sep 11 20:38:24 2014
> -+++ tools/clang/lib/CodeGen/CGDebugInfo.cpp Thu Sep 11 20:39:09 2014
> -@@ -1258,7 +1258,7 @@ CollectTemplateParams(const TemplateParameterList *TPL
> -         V = CGM.GetAddrOfFunction(FD);
> -       // Member data pointers have special handling too to compute the fixed
> -       // offset within the object.
> --      if (isa<FieldDecl>(D)) {
> -+      if (isa<FieldDecl>(D) || isa<IndirectFieldDecl>(D)) {
> -         // These five lines (& possibly the above member function pointer
> -         // handling) might be able to be refactored to use similar code in
> -         // CodeGenModule::getMemberPointerConstant
> Index: patches/patch-tools_clang_lib_CodeGen_TargetInfo_cpp
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_CodeGen_TargetInfo_cpp
> diff -N patches/patch-tools_clang_lib_CodeGen_TargetInfo_cpp
> --- patches/patch-tools_clang_lib_CodeGen_TargetInfo_cpp 16 Dec 2014 21:10:31 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,129 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_CodeGen_TargetInfo_cpp,v 1.1 2014/12/16 21:10:31 brad Exp $
> -
> -r221170
> -Implement vaarg lowering for ppc32. Lowering of scalars and
> -aggregates is supported. Complex numbers are not.
> -
> ---- tools/clang/lib/CodeGen/TargetInfo.cpp.orig Tue Dec 16 12:53:59 2014
> -+++ tools/clang/lib/CodeGen/TargetInfo.cpp Tue Dec 16 13:53:28 2014
> -@@ -2838,12 +2838,20 @@ llvm::Value *NaClX86_64ABIInfo::EmitVAArg(llvm::Value
> -
> -
> - // PowerPC-32
> --
> - namespace {
> --class PPC32TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
> -+/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
> -+class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
> - public:
> --  PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
> -+  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
> -
> -+  llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
> -+                         CodeGenFunction &CGF) const;
> -+};
> -+
> -+class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
> -+public:
> -+  PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT)) {}
> -+
> -   int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const {
> -     // This is recovered from gcc output.
> -     return 1; // r1 is the dedicated stack pointer
> -@@ -2853,6 +2861,96 @@ class PPC32TargetCodeGenInfo : public DefaultTargetCod
> -                                llvm::Value *Address) const;
> - };
> -
> -+}
> -+
> -+llvm::Value *PPC32_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr,
> -+                                           QualType Ty,
> -+                                           CodeGenFunction &CGF) const {
> -+  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
> -+    // TODO: Implement this. For now ignore.
> -+    (void)CTy;
> -+    return NULL;
> -+  }
> -+
> -+  bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
> -+  bool isInt = Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
> -+  llvm::Type *CharPtr = CGF.Int8PtrTy;
> -+  llvm::Type *CharPtrPtr = CGF.Int8PtrPtrTy;
> -+
> -+  CGBuilderTy &Builder = CGF.Builder;
> -+  llvm::Value *GPRPtr = Builder.CreateBitCast(VAListAddr, CharPtr, "gprptr");
> -+  llvm::Value *GPRPtrAsInt = Builder.CreatePtrToInt(GPRPtr, CGF.Int32Ty);
> -+  llvm::Value *FPRPtrAsInt = Builder.CreateAdd(GPRPtrAsInt, Builder.getInt32(1));
> -+  llvm::Value *FPRPtr = Builder.CreateIntToPtr(FPRPtrAsInt, CharPtr);
> -+  llvm::Value *OverflowAreaPtrAsInt = Builder.CreateAdd(FPRPtrAsInt, Builder.getInt32(3));
> -+  llvm::Value *OverflowAreaPtr = Builder.CreateIntToPtr(OverflowAreaPtrAsInt, CharPtrPtr);
> -+  llvm::Value *RegsaveAreaPtrAsInt = Builder.CreateAdd(OverflowAreaPtrAsInt, Builder.getInt32(4));
> -+  llvm::Value *RegsaveAreaPtr = Builder.CreateIntToPtr(RegsaveAreaPtrAsInt, CharPtrPtr);
> -+  llvm::Value *GPR = Builder.CreateLoad(GPRPtr, false, "gpr");
> -+  // Align GPR when TY is i64.
> -+  if (isI64) {
> -+    llvm::Value *GPRAnd = Builder.CreateAnd(GPR, Builder.getInt8(1));
> -+    llvm::Value *CC64 = Builder.CreateICmpEQ(GPRAnd, Builder.getInt8(1));
> -+    llvm::Value *GPRPlusOne = Builder.CreateAdd(GPR, Builder.getInt8(1));
> -+    GPR = Builder.CreateSelect(CC64, GPRPlusOne, GPR);
> -+  }
> -+  llvm::Value *FPR = Builder.CreateLoad(FPRPtr, false, "fpr");
> -+  llvm::Value *OverflowArea = Builder.CreateLoad(OverflowAreaPtr, false, "overflow_area");
> -+  llvm::Value *OverflowAreaAsInt = Builder.CreatePtrToInt(OverflowArea, CGF.Int32Ty);
> -+  llvm::Value *RegsaveArea = Builder.CreateLoad(RegsaveAreaPtr, false, "regsave_area");
> -+  llvm::Value *RegsaveAreaAsInt = Builder.CreatePtrToInt(RegsaveArea, CGF.Int32Ty);
> -+
> -+  llvm::Value *CC = Builder.CreateICmpULT(isInt ? GPR : FPR,
> -+                                          Builder.getInt8(8), "cond");
> -+
> -+  llvm::Value *RegConstant = Builder.CreateMul(isInt ? GPR : FPR,
> -+                                               Builder.getInt8(isInt ? 4 : 8));
> -+
> -+  llvm::Value *OurReg = Builder.CreateAdd(RegsaveAreaAsInt, Builder.CreateSExt(RegConstant, CGF.Int32Ty));
> -+
> -+  if (Ty->isFloatingType())
> -+    OurReg = Builder.CreateAdd(OurReg, Builder.getInt32(32));
> -+
> -+  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
> -+  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
> -+  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
> -+
> -+  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
> -+
> -+  CGF.EmitBlock(UsingRegs);
> -+
> -+  llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
> -+  llvm::Value *Result1 = Builder.CreateIntToPtr(OurReg, PTy);
> -+  // Increase the GPR/FPR indexes.
> -+  if (isInt) {
> -+    GPR = Builder.CreateAdd(GPR, Builder.getInt8(isI64 ? 2 : 1));
> -+    Builder.CreateStore(GPR, GPRPtr);
> -+  } else {
> -+    FPR = Builder.CreateAdd(FPR, Builder.getInt8(1));
> -+    Builder.CreateStore(FPR, FPRPtr);
> -+  }
> -+  CGF.EmitBranch(Cont);
> -+
> -+  CGF.EmitBlock(UsingOverflow);
> -+
> -+  // Increase the overflow area.
> -+  llvm::Value *Result2 = Builder.CreateIntToPtr(OverflowAreaAsInt, PTy);
> -+  OverflowAreaAsInt = Builder.CreateAdd(OverflowAreaAsInt, Builder.getInt32(isInt ? 4 : 8));
> -+  Builder.CreateStore(Builder.CreateIntToPtr(OverflowAreaAsInt, CharPtr), OverflowAreaPtr);
> -+  CGF.EmitBranch(Cont);
> -+
> -+  CGF.EmitBlock(Cont);
> -+
> -+  llvm::PHINode *Result = CGF.Builder.CreatePHI(PTy, 2, "vaarg.addr");
> -+  Result->addIncoming(Result1, UsingRegs);
> -+  Result->addIncoming(Result2, UsingOverflow);
> -+
> -+  if (Ty->isAggregateType()) {
> -+    llvm::Value *AGGPtr = Builder.CreateBitCast(Result, CharPtrPtr, "aggrptr")  ;
> -+    return Builder.CreateLoad(AGGPtr, false, "aggr");
> -+  }
> -+
> -+  return Result;
> - }
> -
> - bool
> Index: patches/patch-tools_clang_lib_Driver_ToolChain_cpp
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_Driver_ToolChain_cpp
> diff -N patches/patch-tools_clang_lib_Driver_ToolChain_cpp
> --- patches/patch-tools_clang_lib_Driver_ToolChain_cpp 9 Apr 2015 22:25:02 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,48 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_Driver_ToolChain_cpp,v 1.1 2015/04/09 22:25:02 sthen Exp $
> -
> -r211785
> -Implement the -fuse-ld= option.
> -
> -This commit implements the -fuse-ld= option, so that the user
> -can specify -fuse-ld=bfd to use ld.bfd.
> -
> ---- tools/clang/lib/Driver/ToolChain.cpp.orig Thu Feb 26 07:04:19 2015
> -+++ tools/clang/lib/Driver/ToolChain.cpp Thu Feb 26 07:05:21 2015
> -@@ -15,6 +15,7 @@
> - #include "clang/Driver/Options.h"
> - #include "clang/Driver/SanitizerArgs.h"
> - #include "clang/Driver/ToolChain.h"
> -+#include "llvm/ADT/SmallString.h"
> - #include "llvm/ADT/StringSwitch.h"
> - #include "llvm/Option/Arg.h"
> - #include "llvm/Option/ArgList.h"
> -@@ -145,6 +146,29 @@ std::string ToolChain::GetFilePath(const char *Name) c
> -
> - std::string ToolChain::GetProgramPath(const char *Name) const {
> -   return D.GetProgramPath(Name, *this);
> -+}
> -+
> -+std::string ToolChain::GetLinkerPath() const {
> -+  if (Arg *A = Args.getLastArg(options::OPT_fuse_ld_EQ)) {
> -+    StringRef Suffix = A->getValue();
> -+
> -+    // If we're passed -fuse-ld= with no argument, or with the argument ld,
> -+    // then use whatever the default system linker is.
> -+    if (Suffix.empty() || Suffix == "ld")
> -+      return GetProgramPath("ld");
> -+
> -+    llvm::SmallString<8> LinkerName("ld.");
> -+    LinkerName.append(Suffix);
> -+
> -+    std::string LinkerPath(GetProgramPath(LinkerName.c_str()));
> -+    if (llvm::sys::fs::exists(LinkerPath))
> -+      return LinkerPath;
> -+
> -+    getDriver().Diag(diag::err_drv_invalid_linker_name) << A->getAsString(Args);
> -+    return "";
> -+  }
> -+
> -+  return GetProgramPath("ld");
> - }
> -
> - types::ID ToolChain::LookupTypeForExtension(const char *Ext) const {
> Index: patches/patch-tools_clang_lib_Driver_ToolChains_cpp
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_Driver_ToolChains_cpp
> diff -N patches/patch-tools_clang_lib_Driver_ToolChains_cpp
> --- patches/patch-tools_clang_lib_Driver_ToolChains_cpp 9 Apr 2015 22:25:02 -0000 1.4
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,36 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_Driver_ToolChains_cpp,v 1.4 2015/04/09 22:25:02 sthen Exp $
> -
> -r225958
> -Use the integrated assembler by default on 32-bit PowerPC and SPARC.
> -
> -r211785
> -Implement the -fuse-ld= option.
> -
> -This commit implements the -fuse-ld= option, so that the user
> -can specify -fuse-ld=bfd to use ld.bfd.
> -
> ---- tools/clang/lib/Driver/ToolChains.cpp.orig Sun Mar  2 22:03:41 2014
> -+++ tools/clang/lib/Driver/ToolChains.cpp Thu Feb 26 07:06:45 2015
> -@@ -2035,7 +2035,12 @@ bool Generic_GCC::IsIntegratedAssemblerDefault() const
> -          getTriple().getArch() == llvm::Triple::aarch64 ||
> -          getTriple().getArch() == llvm::Triple::aarch64_be ||
> -          getTriple().getArch() == llvm::Triple::arm ||
> --         getTriple().getArch() == llvm::Triple::thumb;
> -+         getTriple().getArch() == llvm::Triple::thumb ||
> -+         getTriple().getArch() == llvm::Triple::ppc ||
> -+         getTriple().getArch() == llvm::Triple::ppc64 ||
> -+         getTriple().getArch() == llvm::Triple::ppc64le ||
> -+         getTriple().getArch() == llvm::Triple::sparc ||
> -+         getTriple().getArch() == llvm::Triple::sparcv9;
> - }
> -
> - void Generic_ELF::addClangTargetOptions(const ArgList &DriverArgs,
> -@@ -2850,7 +2855,7 @@ Linux::Linux(const Driver &D, const llvm::Triple &Trip
> -   PPaths.push_back(Twine(GCCInstallation.getParentLibPath() + "/../" +
> -                          GCCInstallation.getTriple().str() + "/bin").str());
> -
> --  Linker = GetProgramPath("ld");
> -+  Linker = GetLinkerPath();
> -
> -   Distro Distro = DetectDistro(Arch);
> -
> Index: patches/patch-tools_clang_lib_Driver_ToolChains_h
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_Driver_ToolChains_h
> diff -N patches/patch-tools_clang_lib_Driver_ToolChains_h
> --- patches/patch-tools_clang_lib_Driver_ToolChains_h 11 Feb 2015 00:29:05 -0000 1.11
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,44 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_Driver_ToolChains_h,v 1.11 2015/02/11 00:29:05 brad Exp $
> -
> -r209432
> -Use stack protector strong by default on OpenBSD
> -
> -r225958
> -Use the integrated assembler by default on 32-bit PowerPC and SPARC.
> -
> ---- tools/clang/lib/Driver/ToolChains.h.orig Sun Mar  2 22:03:41 2014
> -+++ tools/clang/lib/Driver/ToolChains.h Mon Feb  2 11:05:30 2015
> -@@ -538,7 +538,7 @@ class LLVM_LIBRARY_VISIBILITY OpenBSD : public Generic
> -   virtual bool isPIEDefault() const { return true; }
> -
> -   virtual unsigned GetDefaultStackProtectorLevel(bool KernelOrKext) const {
> --    return 1;
> -+    return 2;
> -   }
> -
> - protected:
> -@@ -582,12 +582,6 @@ class LLVM_LIBRARY_VISIBILITY FreeBSD : public Generic
> -   virtual void
> -   AddClangCXXStdlibIncludeArgs(const llvm::opt::ArgList &DriverArgs,
> -                                llvm::opt::ArgStringList &CC1Args) const;
> --  virtual bool IsIntegratedAssemblerDefault() const {
> --    if (getTriple().getArch() == llvm::Triple::ppc ||
> --        getTriple().getArch() == llvm::Triple::ppc64)
> --      return true;
> --    return Generic_ELF::IsIntegratedAssemblerDefault();
> --  }
> -
> -   virtual bool UseSjLjExceptions() const;
> -   virtual bool isPIEDefault() const;
> -@@ -611,11 +605,6 @@ class LLVM_LIBRARY_VISIBILITY NetBSD : public Generic_
> -                                llvm::opt::ArgStringList &CC1Args) const;
> -   virtual bool IsUnwindTablesDefault() const {
> -     return true;
> --  }
> --  virtual bool IsIntegratedAssemblerDefault() const {
> --    if (getTriple().getArch() == llvm::Triple::ppc)
> --      return true;
> --    return Generic_ELF::IsIntegratedAssemblerDefault();
> -   }
> -
> - protected:
> Index: patches/patch-tools_clang_lib_Driver_Tools_cpp
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_Driver_Tools_cpp
> diff -N patches/patch-tools_clang_lib_Driver_Tools_cpp
> --- patches/patch-tools_clang_lib_Driver_Tools_cpp 4 Jun 2015 09:04:44 -0000 1.26
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,219 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_Driver_Tools_cpp,v 1.26 2015/06/04 09:04:44 ajacoutot Exp $
> -
> -r212838
> -Handle SPARC float command line parameters for SPARCv9.
> -
> -r216029
> -Handle SPARC float command line parameters for SPARCv9.
> -
> -r211624
> -Use appropriate default PIE settings for OpenBSD.
> -
> -r239028
> -Use the appropriate PIE level for OpenBSD/sparc.
> -
> -r210883
> -Use dwarf-2 by default on OpenBSD and FreeBSD.
> -
> -r209479
> -Don't reduce the stack protector level given -fstack-protector.
> -
> -r211785
> -Implement the -fuse-ld= option.
> -
> -This commit implements the -fuse-ld= option, so that the user
> -can specify -fuse-ld=bfd to use ld.bfd.
> -
> ---- tools/clang/lib/Driver/Tools.cpp.orig Sun Mar  2 22:03:41 2014
> -+++ tools/clang/lib/Driver/Tools.cpp Tue Jun  2 16:46:10 2015
> -@@ -1150,7 +1150,7 @@ static std::string getR600TargetGPU(const ArgList &Arg
> - }
> -
> - static void getSparcTargetFeatures(const ArgList &Args,
> --                                   std::vector<const char *> Features) {
> -+                                   std::vector<const char *> &Features) {
> -   bool SoftFloatABI = true;
> -   if (Arg *A =
> -           Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float)) {
> -@@ -1165,7 +1165,7 @@ void Clang::AddSparcTargetArgs(const ArgList &Args,
> -                              ArgStringList &CmdArgs) const {
> -   const Driver &D = getToolChain().getDriver();
> -
> --  // Select the float ABI as determined by -msoft-float, -mhard-float, and
> -+  // Select the float ABI as determined by -msoft-float and -mhard-float.
> -   StringRef FloatABI;
> -   if (Arg *A = Args.getLastArg(options::OPT_msoft_float,
> -                                options::OPT_mhard_float)) {
> -@@ -1486,6 +1486,7 @@ static void getTargetFeatures(const Driver &D, const l
> -     getPPCTargetFeatures(Args, Features);
> -     break;
> -   case llvm::Triple::sparc:
> -+  case llvm::Triple::sparcv9:
> -     getSparcTargetFeatures(Args, Features);
> -     break;
> -   case llvm::Triple::aarch64:
> -@@ -2261,6 +2262,27 @@ void Clang::ConstructJob(Compilation &C, const JobActi
> -     }
> -   }
> -
> -+  // OpenBSD-specific defaults for PIE
> -+  if (getToolChain().getTriple().getOS() == llvm::Triple::OpenBSD) {
> -+    switch (getToolChain().getTriple().getArch()) {
> -+    case llvm::Triple::mips64:
> -+    case llvm::Triple::mips64el:
> -+    case llvm::Triple::x86:
> -+    case llvm::Triple::x86_64:
> -+      IsPICLevelTwo = false; // "-fpie"
> -+      break;
> -+
> -+    case llvm::Triple::ppc:
> -+    case llvm::Triple::sparc:
> -+    case llvm::Triple::sparcv9:
> -+      IsPICLevelTwo = true; // "-fPIE"
> -+      break;
> -+
> -+    default:
> -+      break;
> -+    }
> -+  }
> -+
> -   // For the PIC and PIE flag options, this logic is different from the
> -   // legacy logic in very old versions of GCC, as that logic was just
> -   // a bug no one had ever fixed. This logic is both more rational and
> -@@ -2631,6 +2653,7 @@ void Clang::ConstructJob(Compilation &C, const JobActi
> -     break;
> -
> -   case llvm::Triple::sparc:
> -+  case llvm::Triple::sparcv9:
> -     AddSparcTargetArgs(Args, CmdArgs);
> -     break;
> -
> -@@ -2696,8 +2719,10 @@ void Clang::ConstructJob(Compilation &C, const JobActi
> -       // FIXME: we should support specifying dwarf version with
> -       // -gline-tables-only.
> -       CmdArgs.push_back("-gline-tables-only");
> --      // Default is dwarf-2 for darwin.
> --      if (getToolChain().getTriple().isOSDarwin())
> -+      // Default is dwarf-2 for Darwin, OpenBSD and FreeBSD.
> -+      const llvm::Triple &Triple = getToolChain().getTriple();
> -+      if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::OpenBSD ||
> -+          Triple.getOS() == llvm::Triple::FreeBSD)
> -         CmdArgs.push_back("-gdwarf-2");
> -     } else if (A->getOption().matches(options::OPT_gdwarf_2))
> -       CmdArgs.push_back("-gdwarf-2");
> -@@ -2707,8 +2732,10 @@ void Clang::ConstructJob(Compilation &C, const JobActi
> -       CmdArgs.push_back("-gdwarf-4");
> -     else if (!A->getOption().matches(options::OPT_g0) &&
> -              !A->getOption().matches(options::OPT_ggdb0)) {
> --      // Default is dwarf-2 for darwin.
> --      if (getToolChain().getTriple().isOSDarwin())
> -+      // Default is dwarf-2 for Darwin, OpenBSD and FreeBSD.
> -+      const llvm::Triple &Triple = getToolChain().getTriple();
> -+      if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::OpenBSD ||
> -+          Triple.getOS() == llvm::Triple::FreeBSD)
> -         CmdArgs.push_back("-gdwarf-2");
> -       else
> -         CmdArgs.push_back("-g");
> -@@ -3197,9 +3224,10 @@ void Clang::ConstructJob(Compilation &C, const JobActi
> -                                options::OPT_fstack_protector_all,
> -                                options::OPT_fstack_protector_strong,
> -                                options::OPT_fstack_protector)) {
> --    if (A->getOption().matches(options::OPT_fstack_protector))
> --      StackProtectorLevel = LangOptions::SSPOn;
> --    else if (A->getOption().matches(options::OPT_fstack_protector_strong))
> -+    if (A->getOption().matches(options::OPT_fstack_protector)) {
> -+      StackProtectorLevel = std::max<unsigned>(LangOptions::SSPOn,
> -+        getToolChain().GetDefaultStackProtectorLevel(KernelOrKext));
> -+    } else if (A->getOption().matches(options::OPT_fstack_protector_strong))
> -       StackProtectorLevel = LangOptions::SSPStrong;
> -     else if (A->getOption().matches(options::OPT_fstack_protector_all))
> -       StackProtectorLevel = LangOptions::SSPReq;
> -@@ -5281,7 +5309,7 @@ void darwin::Link::ConstructJob(Compilation &C, const
> -   Args.AddAllArgs(CmdArgs, options::OPT_F);
> -
> -   const char *Exec =
> --    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
> -+    Args.MakeArgString(getToolChain().GetLinkerPath());
> -   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
> - }
> -
> -@@ -5478,7 +5506,7 @@ void solaris::Link::ConstructJob(Compilation &C, const
> -   addProfileRT(getToolChain(), Args, CmdArgs);
> -
> -   const char *Exec =
> --    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
> -+    Args.MakeArgString(getToolChain().GetLinkerPath());
> -   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
> - }
> -
> -@@ -5590,7 +5618,7 @@ void auroraux::Link::ConstructJob(Compilation &C, cons
> -   addProfileRT(getToolChain(), Args, CmdArgs);
> -
> -   const char *Exec =
> --    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
> -+    Args.MakeArgString(getToolChain().GetLinkerPath());
> -   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
> - }
> -
> -@@ -5743,6 +5771,7 @@ void openbsd::Link::ConstructJob(Compilation &C, const
> -                                        "/4.2.1"));
> -
> -   Args.AddAllArgs(CmdArgs, options::OPT_L);
> -+  Args.AddAllArgs(CmdArgs, options::OPT_R);
> -   Args.AddAllArgs(CmdArgs, options::OPT_T_Group);
> -   Args.AddAllArgs(CmdArgs, options::OPT_e);
> -   Args.AddAllArgs(CmdArgs, options::OPT_s);
> -@@ -5795,7 +5824,7 @@ void openbsd::Link::ConstructJob(Compilation &C, const
> -   }
> -
> -   const char *Exec =
> --    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
> -+    Args.MakeArgString(getToolChain().GetLinkerPath());
> -   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
> - }
> -
> -@@ -5935,7 +5964,7 @@ void bitrig::Link::ConstructJob(Compilation &C, const
> -   }
> -
> -   const char *Exec =
> --    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
> -+    Args.MakeArgString(getToolChain().GetLinkerPath());
> -   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
> - }
> -
> -@@ -6200,7 +6229,7 @@ void freebsd::Link::ConstructJob(Compilation &C, const
> -   addProfileRT(ToolChain, Args, CmdArgs);
> -
> -   const char *Exec =
> --    Args.MakeArgString(ToolChain.GetProgramPath("ld"));
> -+    Args.MakeArgString(ToolChain.GetLinkerPath());
> -   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
> - }
> -
> -@@ -6448,7 +6477,7 @@ void netbsd::Link::ConstructJob(Compilation &C, const
> -
> -   addProfileRT(getToolChain(), Args, CmdArgs);
> -
> --  const char *Exec = Args.MakeArgString(getToolChain().GetProgramPath("ld"));
> -+  const char *Exec = Args.MakeArgString(getToolChain().GetLinkerPath());
> -   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
> - }
> -
> -@@ -6964,7 +6993,7 @@ void minix::Link::ConstructJob(Compilation &C, const J
> -          Args.MakeArgString(getToolChain().GetFilePath("crtend.o")));
> -   }
> -
> --  const char *Exec = Args.MakeArgString(getToolChain().GetProgramPath("ld"));
> -+  const char *Exec = Args.MakeArgString(getToolChain().GetLinkerPath());
> -   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
> - }
> -
> -@@ -7148,7 +7177,7 @@ void dragonfly::Link::ConstructJob(Compilation &C, con
> -   addProfileRT(getToolChain(), Args, CmdArgs);
> -
> -   const char *Exec =
> --    Args.MakeArgString(getToolChain().GetProgramPath("ld"));
> -+    Args.MakeArgString(getToolChain().GetLinkerPath());
> -   C.addCommand(new Command(JA, *this, Exec, CmdArgs));
> - }
> -
> Index: patches/patch-tools_clang_lib_Headers_xmmintrin_h
> ===================================================================
> RCS file: patches/patch-tools_clang_lib_Headers_xmmintrin_h
> diff -N patches/patch-tools_clang_lib_Headers_xmmintrin_h
> --- patches/patch-tools_clang_lib_Headers_xmmintrin_h 13 Jun 2014 22:29:40 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,18 +0,0 @@
> -$OpenBSD: patch-tools_clang_lib_Headers_xmmintrin_h,v 1.1 2014/06/13 22:29:40 brad Exp $
> -
> -r209489
> -The last step of _mm_cvtps_pi16 should use _mm_packs_pi32, which is a function
> -that reads two __m64 values and packs four 32-bit values into four 16-bit
> -values.
> -
> ---- tools/clang/lib/Headers/xmmintrin.h.orig Thu Jun  5 00:06:01 2014
> -+++ tools/clang/lib/Headers/xmmintrin.h Thu Jun  5 00:06:36 2014
> -@@ -905,7 +905,7 @@ _mm_cvtps_pi16(__m128 __a)
> -   __a = _mm_movehl_ps(__a, __a);
> -   __c = _mm_cvtps_pi32(__a);
> -  
> --  return _mm_packs_pi16(__b, __c);
> -+  return _mm_packs_pi32(__b, __c);
> - }
> -
> - static __inline__ __m64 __attribute__((__always_inline__, __nodebug__))
> Index: patches/patch-tools_clang_tools_scan-build_scan-build
> ===================================================================
> RCS file: /cvs/ports/devel/llvm/patches/patch-tools_clang_tools_scan-build_scan-build,v
> retrieving revision 1.6
> diff -u -p -r1.6 patch-tools_clang_tools_scan-build_scan-build
> --- patches/patch-tools_clang_tools_scan-build_scan-build 18 Apr 2014 09:30:48 -0000 1.6
> +++ patches/patch-tools_clang_tools_scan-build_scan-build 23 Jan 2016 18:38:52 -0000
> @@ -1,7 +1,7 @@
>  $OpenBSD: patch-tools_clang_tools_scan-build_scan-build,v 1.6 2014/04/18 09:30:48 brad Exp $
> ---- tools/clang/tools/scan-build/scan-build.orig Mon Feb 24 21:55:37 2014
> -+++ tools/clang/tools/scan-build/scan-build Mon Feb 24 22:03:55 2014
> -@@ -419,7 +419,7 @@ sub CopyFiles {
> +--- tools/clang/tools/scan-build/scan-build.orig Thu Jul  2 00:35:29 2015
> ++++ tools/clang/tools/scan-build/scan-build Tue Sep  8 21:55:38 2015
> +@@ -437,7 +437,7 @@ sub CopyFiles {
>  
>     my $Dir = shift;
>  
> @@ -10,7 +10,7 @@ $OpenBSD: patch-tools_clang_tools_scan-b
>  
>     DieDiag("Cannot find 'sorttable.js'.\n")
>       if (! -r $JS);
> -@@ -429,7 +429,7 @@ sub CopyFiles {
> +@@ -447,7 +447,7 @@ sub CopyFiles {
>     DieDiag("Could not copy 'sorttable.js' to '$Dir'.\n")
>       if (! -r "$Dir/sorttable.js");
>  
> Index: patches/patch-tools_llvm-config_llvm-config_cpp
> ===================================================================
> RCS file: patches/patch-tools_llvm-config_llvm-config_cpp
> diff -N patches/patch-tools_llvm-config_llvm-config_cpp
> --- patches/patch-tools_llvm-config_llvm-config_cpp 22 Jan 2015 12:29:36 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,54 +0,0 @@
> -$OpenBSD: patch-tools_llvm-config_llvm-config_cpp,v 1.1 2015/01/22 12:29:36 brad Exp $
> -
> -r202719
> -Don't emit a blank line when running llvm-config --system-libs.
> -
> ---- tools/llvm-config/llvm-config.cpp.orig Thu Jan 22 06:25:33 2015
> -+++ tools/llvm-config/llvm-config.cpp Thu Jan 22 06:30:40 2015
> -@@ -345,27 +345,29 @@ int main(int argc, char **argv) {
> -     ComputeLibsForComponents(Components, RequiredLibs,
> -                              /*IncludeNonInstalled=*/IsInDevelopmentTree);
> -
> --    for (unsigned i = 0, e = RequiredLibs.size(); i != e; ++i) {
> --      StringRef Lib = RequiredLibs[i];
> --      if (i)
> --        OS << ' ';
> -+    if (PrintLibs || PrintLibNames || PrintLibFiles) {
> -+      for (unsigned i = 0, e = RequiredLibs.size(); i != e; ++i) {
> -+        StringRef Lib = RequiredLibs[i];
> -+        if (i)
> -+          OS << ' ';
> -
> --      if (PrintLibNames) {
> --        OS << Lib;
> --      } else if (PrintLibFiles) {
> --        OS << ActiveLibDir << '/' << Lib;
> --      } else if (PrintLibs) {
> --        // If this is a typical library name, include it using -l.
> --        if (Lib.startswith("lib") && Lib.endswith(".a")) {
> --          OS << "-l" << Lib.slice(3, Lib.size()-2);
> --          continue;
> --        }
> -+        if (PrintLibNames) {
> -+          OS << Lib;
> -+        } else if (PrintLibFiles) {
> -+          OS << ActiveLibDir << '/' << Lib;
> -+        } else if (PrintLibs) {
> -+          // If this is a typical library name, include it using -l.
> -+          if (Lib.startswith("lib") && Lib.endswith(".a")) {
> -+            OS << "-l" << Lib.slice(3, Lib.size()-2);
> -+            continue;
> -+          }
> -
> --        // Otherwise, print the full path.
> --        OS << ActiveLibDir << '/' << Lib;
> -+          // Otherwise, print the full path.
> -+          OS << ActiveLibDir << '/' << Lib;
> -+        }
> -       }
> -+      OS << '\n';
> -     }
> --    OS << '\n';
> -
> -     // Print SYSTEM_LIBS after --libs.
> -     // FIXME: Each LLVM component may have its dependent system libs.
> Index: pkg/PLIST
> ===================================================================
> RCS file: /cvs/ports/devel/llvm/pkg/PLIST,v
> retrieving revision 1.21
> diff -u -p -r1.21 PLIST
> --- pkg/PLIST 18 Apr 2014 09:30:48 -0000 1.21
> +++ pkg/PLIST 23 Jan 2016 18:38:52 -0000
> @@ -4,7 +4,7 @@ bin/c++-analyzer
>  bin/ccc-analyzer
>  bin/clang
>  bin/clang++
> -@bin bin/clang-${LLVM_V}
> +@bin bin/clang-3.7
>  @bin bin/clang-check
>  bin/clang-cl
>  @bin bin/clang-format
> @@ -17,17 +17,22 @@ bin/git-clang-format
>  @bin bin/llvm-c-test
>  @bin bin/llvm-config
>  @bin bin/llvm-cov
> +@bin bin/llvm-cxxdump
>  @bin bin/llvm-diff
>  @bin bin/llvm-dis
> +@bin bin/llvm-dsymutil
>  @bin bin/llvm-dwarfdump
>  @bin bin/llvm-extract
> +bin/llvm-lib
>  @bin bin/llvm-link
>  @bin bin/llvm-lto
>  @bin bin/llvm-mc
>  @bin bin/llvm-mcmarkup
>  @bin bin/llvm-nm
>  @bin bin/llvm-objdump
> +@bin bin/llvm-pdbdump
>  @bin bin/llvm-profdata
> +bin/llvm-ranlib
>  @bin bin/llvm-readobj
>  @bin bin/llvm-rtdyld
>  @bin bin/llvm-size
> @@ -35,14 +40,18 @@ bin/git-clang-format
>  @bin bin/llvm-symbolizer
>  @bin bin/llvm-tblgen
>  @bin bin/macho-dump
> +@bin bin/obj2yaml
>  @bin bin/opt
>  bin/scan-build
> +@bin bin/verify-uselistorder
> +@bin bin/yaml2obj
>  include/clang/
>  include/clang-c/
>  include/clang-c/BuildSystem.h
>  include/clang-c/CXCompilationDatabase.h
>  include/clang-c/CXErrorCode.h
>  include/clang-c/CXString.h
> +include/clang-c/Documentation.h
>  include/clang-c/Index.h
>  include/clang-c/Platform.h
>  include/clang/ARCMigrate/
> @@ -109,6 +118,7 @@ include/clang/AST/ExprCXX.h
>  include/clang/AST/ExprObjC.h
>  include/clang/AST/ExternalASTSource.h
>  include/clang/AST/GlobalDecl.h
> +include/clang/AST/LambdaCapture.h
>  include/clang/AST/Mangle.h
>  include/clang/AST/MangleNumberingContext.h
>  include/clang/AST/NSAPI.h
> @@ -163,17 +173,23 @@ include/clang/Analysis/Analyses/PostOrde
>  include/clang/Analysis/Analyses/PseudoConstantAnalysis.h
>  include/clang/Analysis/Analyses/ReachableCode.h
>  include/clang/Analysis/Analyses/ThreadSafety.h
> +include/clang/Analysis/Analyses/ThreadSafetyCommon.h
> +include/clang/Analysis/Analyses/ThreadSafetyLogical.h
> +include/clang/Analysis/Analyses/ThreadSafetyOps.def
> +include/clang/Analysis/Analyses/ThreadSafetyTIL.h
> +include/clang/Analysis/Analyses/ThreadSafetyTraverse.h
> +include/clang/Analysis/Analyses/ThreadSafetyUtil.h
>  include/clang/Analysis/Analyses/UninitializedValues.h
>  include/clang/Analysis/AnalysisContext.h
>  include/clang/Analysis/AnalysisDiagnostic.h
>  include/clang/Analysis/CFG.h
>  include/clang/Analysis/CFGStmtMap.h
>  include/clang/Analysis/CallGraph.h
> +include/clang/Analysis/CodeInjector.h
>  include/clang/Analysis/DomainSpecific/
>  include/clang/Analysis/DomainSpecific/CocoaConventions.h
>  include/clang/Analysis/DomainSpecific/ObjCNoReturn.h
>  include/clang/Analysis/FlowSensitive/
> -include/clang/Analysis/FlowSensitive/DataflowSolver.h
>  include/clang/Analysis/FlowSensitive/DataflowValues.h
>  include/clang/Analysis/ProgramPoint.h
>  include/clang/Analysis/Support/
> @@ -182,16 +198,22 @@ include/clang/Basic/
>  include/clang/Basic/ABI.h
>  include/clang/Basic/AddressSpaces.h
>  include/clang/Basic/AllDiagnostics.h
> +include/clang/Basic/AttrHasAttributeImpl.inc
>  include/clang/Basic/AttrKinds.h
>  include/clang/Basic/AttrList.inc
> +include/clang/Basic/Attributes.h
>  include/clang/Basic/Builtins.def
>  include/clang/Basic/Builtins.h
>  include/clang/Basic/BuiltinsAArch64.def
> +include/clang/Basic/BuiltinsAMDGPU.def
>  include/clang/Basic/BuiltinsARM.def
>  include/clang/Basic/BuiltinsHexagon.def
> +include/clang/Basic/BuiltinsLe64.def
>  include/clang/Basic/BuiltinsMips.def
> +include/clang/Basic/BuiltinsNEON.def
>  include/clang/Basic/BuiltinsNVPTX.def
>  include/clang/Basic/BuiltinsPPC.def
> +include/clang/Basic/BuiltinsSystemZ.def
>  include/clang/Basic/BuiltinsX86.def
>  include/clang/Basic/BuiltinsXCore.def
>  include/clang/Basic/CapturedStmt.h
> @@ -228,7 +250,6 @@ include/clang/Basic/Linkage.h
>  include/clang/Basic/MacroBuilder.h
>  include/clang/Basic/Module.h
>  include/clang/Basic/ObjCRuntime.h
> -include/clang/Basic/OnDiskHashTable.h
>  include/clang/Basic/OpenCLExtensions.def
>  include/clang/Basic/OpenMPKinds.def
>  include/clang/Basic/OpenMPKinds.h
> @@ -238,7 +259,9 @@ include/clang/Basic/OperatorPrecedence.h
>  include/clang/Basic/PartialDiagnostic.h
>  include/clang/Basic/PlistSupport.h
>  include/clang/Basic/PrettyStackTrace.h
> +include/clang/Basic/SanitizerBlacklist.h
>  include/clang/Basic/Sanitizers.def
> +include/clang/Basic/Sanitizers.h
>  include/clang/Basic/SourceLocation.h
>  include/clang/Basic/SourceManager.h
>  include/clang/Basic/SourceManagerInternals.h
> @@ -263,11 +286,11 @@ include/clang/CodeGen/CGFunctionInfo.h
>  include/clang/CodeGen/Cod