Interrupts handling in SMP

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Interrupts handling in SMP

Sylvain COUTANT
Hi all,

We run some router/firewall boxes and will probably face a load problem soon. CPU takes much time in interrupt processing and I wonder if adding a second one (going to SMP) would help to speed interrupts processing ?

How will the interrupt handling load would share between CPUs if we migrate to mp kernel with 2 or 4 CPUs ?


Thanks for tips.

BR,

--
Sylvain COUTANT

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Re: Interrupts handling in SMP

Alexandre Ratchov
On Sun, Mar 05, 2006 at 10:51:23AM +0100, Sylvain Coutant wrote:

> Hi all,
>
> We run some router/firewall boxes and will probably face a load problem
> soon. CPU takes much time in interrupt processing and I wonder if adding a
> second one (going to SMP) would help to speed interrupts processing ?
>
> How will the interrupt handling load would share between CPUs if we
> migrate to mp kernel with 2 or 4 CPUs ?
>
>

i'm not absolutely sure, but the current implementation uses the same cpu
for all interrupts. Imo, adding cpus will not speed interrupts processing.

--
Alexandre

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Re: Interrupts handling in SMP

Michael Shalayeff-2
In reply to this post by Sylvain COUTANT
On Sun, Mar 05, 2006 at 10:51:23AM +0100, Sylvain Coutant wrote:
> Hi all,
>
> We run some router/firewall boxes and will probably face a load problem soon. CPU takes much time in interrupt processing and I wonder if adding a second one (going to SMP) would help to speed interrupts processing ?
>
> How will the interrupt handling load would share between CPUs if we migrate to mp kernel with 2 or 4 CPUs ?

you can try and run an smp kernel on even one cpu.
it will make use of the ioapic(s) if present that
should make better interrupts processing. also depending
on your hw some hw supports interrupts coalescing
such as em(4) for example that you can play w/ #defines
in the driver to make less interrupts and high pkt/int...

cu
--
    paranoic mickey       (my employers have changed but, the name has remained)