Intel 82801EB in enhanced mode

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Intel 82801EB in enhanced mode

Ulrik Holmén
Hi OpenBSD team.

Thanks for a great secure operating system.

We have a cluster of HP Proliant DL140 G2 servers with the intel 82801EB
SATA controller inside. This controller has two modes of operation, the
Compatibility Mode and the Enhanced Mode. Usually you can configure the
mode from within BIOS but the HP BIOS does not have any options
regarding the mode in the setup. According to the specification of the
chip the SATA device has to be setup for Native PCI mode if the
controller is in enhanced mode. The specification is quoted below.

"Enhanced Configuration
The enhanced configuration is intended for those operating systems
(e.g., Microsoft Windows* 2000, Windows* XP) that comprehend both legacy
and native modes of operation. It is the preferred configuration for
system software due to the maximum flexibility that it offers. Enhanced
mode allows both the P-ATA and SATA host controllers to be used,
providing a maximum of six ATA (4 P-ATA + 2 SATA) devices that can be
used simultaneously.

Note: In this configuration, the P-ATA controller must be programmed for
legacy mode while the SATA controller must be programmed for native mode
of operation."

Both NetBSD and OpenBSD has had reports regarding this problem on
mailinglists but as far as I can see no solutions have been provided. If
the controller is in Legacy PCI mode the devices times out like this:

cd0(pciide0:0:0): timeout
    type: atapi
    type: atapi
    c_bcount: 32
    c_bcount: 32
    c_skip: 0
    c_skip: 0
pciide0:0:0: device timeout, c_bcount=32, c_skip=0,
status=0x58<DRDY,DSC,DRQ>, ireason=0x2

I've made a small patch to fix the problem in the pciide.c and
pciide_piix_reg.h files. I am not a developer so the code is bad and
ugly but you can see it as a hint.

--- pciide_orig.c       Tue Dec 13 14:40:27 2005
+++ pciide.c    Tue Dec 13 15:50:20 2005
@@ -1843,6 +1843,7 @@
         struct pciide_channel *cp;
         int channel;
         u_int32_t idetim;
+       u_int8_t reg;
         bus_size_t cmdsize, ctlsize;

         pcireg_t interface = PCI_INTERFACE(pa->pa_class);
@@ -1914,6 +1915,19 @@
                 sc->sc_wdcdev.UDMA_cap = 2;
                 break;
         }
+       if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_SATA) {
+                reg = pciide_pci_read(sc->sc_pc, sc->sc_tag,
ICH5_SATA_MAP); /* Check the mode of the controller */
+                if ( reg & ICH5_SATA_COMBINED) {
+                        printf(", Combined mode");
+                } else {
+                       printf(", Enhanced mode");
+                       reg = (pciide_pci_read(pa->pa_pc, pa->pa_tag,
ICH5_SATA_PI) | 0x05);
+                       pciide_pci_write(pa->pa_pc, pa->pa_tag,
ICH5_SATA_PI, reg); /* Set the SATA device to Native PCI */
+                       interface |= PCIIDE_INTERFACE_PCI(0) |
PCIIDE_INTERFACE_PCI(1);
+                }
+       }
+
         if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_SATA ||
             sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801ER_SATA ||
             sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_SATA ||
--- pciide_piix_reg_orig.h      Tue Dec 13 14:44:50 2005
+++ pciide_piix_reg.h   Tue Dec 13 15:07:26 2005
@@ -128,6 +128,9 @@
   */
  #define ICH5_SATA_MAP          0x90 /* Address Map Register */
  #define ICH5_SATA_MAP_MV_MASK  0x07 /* Map Value mask */
+#define ICH5_SATA_COMBINED     0x02 /* Combined mode */
+#define ICH5_SATA_PI           0x09 /* Program Intergace register */

  #define ICH_SATA_PCS           0x92 /* Port Control and Status Register */
  #define ICH_SATA_PCS_P0E       0x01 /* Port 0 enabled */