Allwinner H3: other UART ports (not console UART0) support

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Allwinner H3: other UART ports (not console UART0) support

SASANO Takayoshi
On Allwinner H3, currently we can use UART0 for debug/console port.
To use UART1-3 port, we have to make proper device tree blob
and fix kernel code like this.

- com_fdt.c needs to add reset signal de-assert code
- sciccmu_clocks.h requires to add reset signal definition

If there is no problem, I want to commit.

Index: com_fdt.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/com_fdt.c,v
retrieving revision 1.3
diff -u -p -r1.3 com_fdt.c
--- com_fdt.c 6 Aug 2018 10:52:30 -0000 1.3
+++ com_fdt.c 23 Mar 2020 13:02:26 -0000
@@ -105,6 +105,7 @@ com_fdt_attach(struct device *parent, st
  return;
 
  clock_enable(faa->fa_node, NULL);
+ reset_deassert_all(faa->fa_node);
 
  /*
  * Determine the clock frequency after enabling the clock.
Index: sxiccmu_clocks.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
retrieving revision 1.28
diff -u -p -r1.28 sxiccmu_clocks.h
--- sxiccmu_clocks.h 20 Sep 2019 22:42:05 -0000 1.28
+++ sxiccmu_clocks.h 23 Mar 2020 13:02:26 -0000
@@ -746,6 +746,10 @@ struct sxiccmu_ccu_bit sun9i_a80_mmc_res
 #define H3_RST_BUS_I2C0 46
 #define H3_RST_BUS_I2C1 47
 #define H3_RST_BUS_I2C2 48
+#define H3_RST_BUS_UART0 49
+#define H3_RST_BUS_UART1 50
+#define H3_RST_BUS_UART2 51
+#define H3_RST_BUS_UART3 52
 
 struct sxiccmu_ccu_bit sun8i_h3_resets[] = {
  [H3_RST_USB_PHY0] =  { 0x00cc, 0 },
@@ -769,6 +773,10 @@ struct sxiccmu_ccu_bit sun8i_h3_resets[]
  [H3_RST_BUS_I2C0]  = { 0x02d8, 0 },
  [H3_RST_BUS_I2C1]  = { 0x02d8, 1 },
  [H3_RST_BUS_I2C2]  = { 0x02d8, 2 },
+ [H3_RST_BUS_UART0] = { 0x02d8, 16 },
+ [H3_RST_BUS_UART1] = { 0x02d8, 17 },
+ [H3_RST_BUS_UART2] = { 0x02d8, 18 },
+ [H3_RST_BUS_UART3] = { 0x02d8, 19 },
 };
 
 #define H3_R_RST_APB0_RSB 2

--
SASANO Takayoshi (JG1UAA) <[hidden email]>

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Re: Allwinner H3: other UART ports (not console UART0) support

Mark Kettenis
> Date: Mon, 23 Mar 2020 22:51:05 +0900
> From: SASANO Takayoshi <[hidden email]>
>
> On Allwinner H3, currently we can use UART0 for debug/console port.
> To use UART1-3 port, we have to make proper device tree blob
> and fix kernel code like this.
>
> - com_fdt.c needs to add reset signal de-assert code
> - sciccmu_clocks.h requires to add reset signal definition
>
> If there is no problem, I want to commit.

ok kettenis@

> Index: com_fdt.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/fdt/com_fdt.c,v
> retrieving revision 1.3
> diff -u -p -r1.3 com_fdt.c
> --- com_fdt.c 6 Aug 2018 10:52:30 -0000 1.3
> +++ com_fdt.c 23 Mar 2020 13:02:26 -0000
> @@ -105,6 +105,7 @@ com_fdt_attach(struct device *parent, st
>   return;
>  
>   clock_enable(faa->fa_node, NULL);
> + reset_deassert_all(faa->fa_node);
>  
>   /*
>   * Determine the clock frequency after enabling the clock.
> Index: sxiccmu_clocks.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
> retrieving revision 1.28
> diff -u -p -r1.28 sxiccmu_clocks.h
> --- sxiccmu_clocks.h 20 Sep 2019 22:42:05 -0000 1.28
> +++ sxiccmu_clocks.h 23 Mar 2020 13:02:26 -0000
> @@ -746,6 +746,10 @@ struct sxiccmu_ccu_bit sun9i_a80_mmc_res
>  #define H3_RST_BUS_I2C0 46
>  #define H3_RST_BUS_I2C1 47
>  #define H3_RST_BUS_I2C2 48
> +#define H3_RST_BUS_UART0 49
> +#define H3_RST_BUS_UART1 50
> +#define H3_RST_BUS_UART2 51
> +#define H3_RST_BUS_UART3 52
>  
>  struct sxiccmu_ccu_bit sun8i_h3_resets[] = {
>   [H3_RST_USB_PHY0] =  { 0x00cc, 0 },
> @@ -769,6 +773,10 @@ struct sxiccmu_ccu_bit sun8i_h3_resets[]
>   [H3_RST_BUS_I2C0]  = { 0x02d8, 0 },
>   [H3_RST_BUS_I2C1]  = { 0x02d8, 1 },
>   [H3_RST_BUS_I2C2]  = { 0x02d8, 2 },
> + [H3_RST_BUS_UART0] = { 0x02d8, 16 },
> + [H3_RST_BUS_UART1] = { 0x02d8, 17 },
> + [H3_RST_BUS_UART2] = { 0x02d8, 18 },
> + [H3_RST_BUS_UART3] = { 0x02d8, 19 },
>  };
>  
>  #define H3_R_RST_APB0_RSB 2
>
> --
> SASANO Takayoshi (JG1UAA) <[hidden email]>
>
>